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GET /api/patches/2196924/?format=api
{ "id": 2196924, "url": "http://patchwork.ozlabs.org/api/patches/2196924/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216145219.1959-3-alireza.sanaee@huawei.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216145219.1959-3-alireza.sanaee@huawei.com>", "list_archive_url": null, "date": "2026-02-16T14:52:18", "name": "[v3,2/2] hw/cxl: Add a performant (and correct) path for the non interleaved cases", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "673d8c1f49581c5d0febb470d12748984fb550b1", "submitter": { "id": 90159, "url": "http://patchwork.ozlabs.org/api/people/90159/?format=api", "name": "Alireza Sanaee", "email": "alireza.sanaee@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216145219.1959-3-alireza.sanaee@huawei.com/mbox/", "series": [ { "id": 492317, "url": "http://patchwork.ozlabs.org/api/series/492317/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492317", "date": "2026-02-16T14:52:17", "name": "Performant CXL type 3 non-interleaved regions", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/492317/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196924/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196924/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fF5Pv1XjXz1xpY\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 17 Feb 2026 01:53:55 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vrzyh-0006lV-HD; Mon, 16 Feb 2026 09:53:35 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alireza.sanaee@huawei.com>)\n id 1vrzyf-0006l3-Fi\n for qemu-devel@nongnu.org; Mon, 16 Feb 2026 09:53:33 -0500", "from frasgout.his.huawei.com ([185.176.79.56])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alireza.sanaee@huawei.com>)\n id 1vrzyc-0005EM-KW\n for qemu-devel@nongnu.org; Mon, 16 Feb 2026 09:53:33 -0500", "from mail.maildlp.com (unknown [172.18.224.150])\n by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4fF5PC6ZBhzJ4680;\n Mon, 16 Feb 2026 22:53:19 +0800 (CST)", "from dubpeml500005.china.huawei.com (unknown [7.214.145.207])\n by mail.maildlp.com (Postfix) with ESMTPS id 7FF8B40539;\n Mon, 16 Feb 2026 22:53:28 +0800 (CST)", "from a2303103017.china.huawei.com (10.47.67.55) by\n dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.11; Mon, 16 Feb 2026 14:53:27 +0000" ], "To": "<qemu-devel@nongnu.org>, <lizhijian@fujitsu.com>", "CC": "<anisa.su887@gmail.com>, <armbru@redhat.com>, <david@kernel.org>,\n <gourry@gourry.net>, <imammedo@redhat.com>, <jonathan.cameron@huawei.com>,\n <linuxarm@huawei.com>, <mst@redhat.com>, <nifan.cxl@gmail.com>,\n <peterx@redhat.com>, <philmd@linaro.org>, <ppbonzini@redhat.com>,\n <venkataravis@micron.com>, <xiaoguangrong.eric@gmail.com>", "Subject": "[PATCH v3 2/2] hw/cxl: Add a performant (and correct) path for the\n non interleaved cases", "Date": "Mon, 16 Feb 2026 14:52:18 +0000", "Message-ID": "<20260216145219.1959-3-alireza.sanaee@huawei.com>", "X-Mailer": "git-send-email 2.51.0.windows.2", "In-Reply-To": "<20260216145219.1959-1-alireza.sanaee@huawei.com>", "References": "<20260216145219.1959-1-alireza.sanaee@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.47.67.55]", "X-ClientProxiedBy": "lhrpeml100009.china.huawei.com (7.191.174.83) To\n dubpeml500005.china.huawei.com (7.214.145.207)", "Received-SPF": "pass client-ip=185.176.79.56;\n envelope-from=alireza.sanaee@huawei.com; helo=frasgout.his.huawei.com", "X-Spam_score_int": "-41", "X-Spam_score": "-4.2", "X-Spam_bar": "----", "X-Spam_report": "(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-to": "Alireza Sanaee <alireza.sanaee@huawei.com>", "From": "Alireza Sanaee via qemu development <qemu-devel@nongnu.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The CXL address to device decoding logic is complex because of the need\nto correctly decode fine grained interleave. The current implementation\nprevents use with KVM where executed instructions may reside in that\nmemory and gives very slow performance even in TCG.\n\nIn many real cases non interleaved memory configurations are useful and\nfor those we can use a more conventional memory region alias allowing\nsimilar performance to other memory in the system.\n\nWhether this fast path is applicable can be established once the full\nset of HDM decoders has been committed (in whatever order the guest\ndecides to commit them). As such a check is performed on each\ncommit/uncommit of HDM decoder to establish if the alias should be added\nor removed.\n\nCo-developed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\nSigned-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>\nSigned-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>\nTested-by: Gregory Price <gourry@gourry.net>\n---\n hw/cxl/cxl-component-utils.c | 6 ++\n hw/cxl/cxl-host.c | 194 ++++++++++++++++++++++++++++++++++-\n hw/mem/cxl_type3.c | 4 +\n include/hw/cxl/cxl.h | 1 +\n include/hw/cxl/cxl_device.h | 1 +\n 5 files changed, 202 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c\nindex d36162e91b..a10fdb0cc2 100644\n--- a/hw/cxl/cxl-component-utils.c\n+++ b/hw/cxl/cxl-component-utils.c\n@@ -142,6 +142,12 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,\n value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);\n }\n stl_le_p((uint8_t *)cache_mem + offset, value);\n+\n+ if (should_commit) {\n+ cfmws_update_non_interleaved(true);\n+ } else if (should_uncommit) {\n+ cfmws_update_non_interleaved(false);\n+ }\n }\n \n static void bi_handler(CXLComponentState *cxl_cstate, hwaddr offset,\ndiff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c\nindex 415a792380..1fcfe01164 100644\n--- a/hw/cxl/cxl-host.c\n+++ b/hw/cxl/cxl-host.c\n@@ -104,7 +104,7 @@ void cxl_fmws_link_targets(Error **errp)\n }\n \n static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,\n- uint8_t *target)\n+ uint8_t *target, bool *interleaved)\n {\n int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;\n unsigned int hdm_count;\n@@ -138,6 +138,11 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,\n found = true;\n ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);\n iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);\n+\n+ if (interleaved) {\n+ *interleaved = iw_enc != 0;\n+ }\n+\n target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);\n \n if (target_idx < 4) {\n@@ -166,9 +171,12 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr,\n int rb_index;\n uint32_t *cache_mem;\n uint8_t target;\n- bool target_found;\n+ bool target_found, interleaved;\n PCIDevice *rp, *d;\n \n+ if ((fw->num_targets > 1) && !allow_interleave) {\n+ return NULL;\n+ }\n \n rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;\n hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl_host_bridge);\n@@ -189,11 +197,16 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr,\n \n cache_mem = hb_cstate->crb.cache_mem_registers;\n \n- target_found = cxl_hdm_find_target(cache_mem, addr, &target);\n+ target_found = cxl_hdm_find_target(cache_mem, addr, &target,\n+ &interleaved);\n if (!target_found) {\n return NULL;\n }\n \n+ if (interleaved && !allow_interleave) {\n+ return NULL;\n+ }\n+\n rp = pcie_find_port_by_pn(hb->bus, target);\n if (!rp) {\n return NULL;\n@@ -225,11 +238,15 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr,\n \n cache_mem = usp_cstate->crb.cache_mem_registers;\n \n- target_found = cxl_hdm_find_target(cache_mem, addr, &target);\n+ target_found = cxl_hdm_find_target(cache_mem, addr, &target, &interleaved);\n if (!target_found) {\n return NULL;\n }\n \n+ if (interleaved && !allow_interleave) {\n+ return NULL;\n+ }\n+\n d = pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target);\n if (!d) {\n return NULL;\n@@ -247,6 +264,175 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr,\n return d;\n }\n \n+typedef struct CXLDirectPTState {\n+ CXLType3Dev *ct3d;\n+ hwaddr decoder_base;\n+ hwaddr decoder_size;\n+ hwaddr dpa_base;\n+ unsigned int hdm_decoder_idx;\n+ bool commit;\n+} CXLDirectPTState;\n+\n+static void cxl_fmws_direct_passthrough_setup(CXLDirectPTState *state,\n+ CXLFixedWindow *fw)\n+{\n+ CXLType3Dev *ct3d = state->ct3d;\n+ MemoryRegion *mr = NULL;\n+ uint64_t vmr_size = 0, pmr_size = 0, offset = 0;\n+ MemoryRegion *direct_mr;\n+\n+ if (ct3d->hostvmem) {\n+ MemoryRegion *vmr = host_memory_backend_get_memory(ct3d->hostvmem);\n+\n+ vmr_size = memory_region_size(vmr);\n+ if (state->dpa_base < vmr_size) {\n+ mr = vmr;\n+ offset = state->dpa_base;\n+ }\n+ }\n+ if (!mr && ct3d->hostpmem) {\n+ MemoryRegion *pmr = host_memory_backend_get_memory(ct3d->hostpmem);\n+\n+ pmr_size = memory_region_size(pmr);\n+ if (state->dpa_base - vmr_size < pmr_size) {\n+ mr = pmr;\n+ offset = state->dpa_base - vmr_size;\n+ }\n+ }\n+ if (!mr) {\n+ return;\n+ }\n+\n+ direct_mr = &ct3d->direct_mr[state->hdm_decoder_idx];\n+ if (memory_region_is_mapped(direct_mr)) {\n+ return;\n+ }\n+\n+ memory_region_init_alias(direct_mr, OBJECT(ct3d), \"direct-mapping\", mr,\n+ offset, state->decoder_size);\n+ memory_region_add_subregion(&fw->mr,\n+ state->decoder_base - fw->base, direct_mr);\n+}\n+\n+static void cxl_fmws_direct_passthrough_teardown(CXLDirectPTState *state,\n+ CXLFixedWindow *fw)\n+{\n+ CXLType3Dev *ct3d = state->ct3d;\n+ MemoryRegion *direct_mr = &ct3d->direct_mr[state->hdm_decoder_idx];\n+\n+ if (memory_region_is_mapped(direct_mr)) {\n+ memory_region_del_subregion(&fw->mr, direct_mr);\n+ }\n+}\n+\n+static int cxl_fmws_direct_passthrough(Object *obj, void *opaque)\n+{\n+ CXLDirectPTState *state = opaque;\n+ CXLFixedWindow *fw;\n+\n+ if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) {\n+ return 0;\n+ }\n+\n+ fw = CXL_FMW(obj);\n+\n+ /* Verify not interleaved */\n+ if (!cxl_cfmws_find_device(fw, state->decoder_base, false)) {\n+ return 0;\n+ }\n+\n+ if (state->commit) {\n+ cxl_fmws_direct_passthrough_setup(state, fw);\n+ } else {\n+ cxl_fmws_direct_passthrough_teardown(state, fw);\n+ }\n+\n+ return 0;\n+}\n+\n+static int update_non_interleaved(Object *obj, void *opaque)\n+{\n+ const int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;\n+ bool commit = *(bool *)opaque;\n+ CXLType3Dev *ct3d;\n+ uint32_t *cache_mem;\n+ unsigned int hdm_count, i;\n+ uint32_t cap;\n+ uint64_t dpa_base = 0;\n+\n+ if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) {\n+ return 0;\n+ }\n+\n+ ct3d = CXL_TYPE3(obj);\n+ cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers;\n+ cap = ldl_le_p(cache_mem + R_CXL_HDM_DECODER_CAPABILITY);\n+ hdm_count = cxl_decoder_count_dec(FIELD_EX32(cap,\n+ CXL_HDM_DECODER_CAPABILITY,\n+ DECODER_COUNT));\n+ /*\n+ * Walk the decoders and find any committed with iw set to 0\n+ * (non interleaved).\n+ */\n+ for (i = 0; i < hdm_count; i++) {\n+ uint64_t decoder_base, decoder_size, skip;\n+ uint32_t hdm_ctrl, low, high;\n+ int iw, committed;\n+\n+ hdm_ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + i * hdm_inc);\n+ committed = FIELD_EX32(hdm_ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED);\n+ if (commit ^ committed) {\n+ return 0;\n+ }\n+\n+ low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_DPA_SKIP_LO +\n+ i * hdm_inc);\n+ high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_DPA_SKIP_HI +\n+ i * hdm_inc);\n+ skip = ((uint64_t)high << 32) | (low & 0xf0000000);\n+ dpa_base += skip;\n+\n+ low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc);\n+ high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc);\n+ decoder_size = ((uint64_t)high << 32) | (low & 0xf0000000);\n+\n+ low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc);\n+ high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc);\n+ decoder_base = ((uint64_t)high << 32) | (low & 0xf0000000);\n+\n+ iw = FIELD_EX32(hdm_ctrl, CXL_HDM_DECODER0_CTRL, IW);\n+\n+ if (iw == 0) {\n+ CXLDirectPTState state = {\n+ .ct3d = ct3d,\n+ .decoder_base = decoder_base,\n+ .decoder_size = decoder_size,\n+ .dpa_base = dpa_base,\n+ .hdm_decoder_idx = i,\n+ .commit = commit,\n+ };\n+\n+ object_child_foreach_recursive(object_get_root(),\n+ cxl_fmws_direct_passthrough, &state);\n+ }\n+ dpa_base += decoder_size / cxl_interleave_ways_dec(iw, &error_fatal);\n+ }\n+\n+ return 0;\n+}\n+\n+bool cfmws_update_non_interleaved(bool commit)\n+{\n+ /*\n+ * Walk endpoints to find committed decoders then check if they are not\n+ * interleaved (but path is fully set up).\n+ */\n+ object_child_foreach_recursive(object_get_root(),\n+ update_non_interleaved, &commit);\n+\n+ return false;\n+}\n+\n static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,\n unsigned size, MemTxAttrs attrs)\n {\ndiff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c\nindex 3f09c589ae..a95f6a4014 100644\n--- a/hw/mem/cxl_type3.c\n+++ b/hw/mem/cxl_type3.c\n@@ -427,6 +427,8 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)\n ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);\n \n stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl);\n+\n+ cfmws_update_non_interleaved(true);\n }\n \n static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int which)\n@@ -442,6 +444,8 @@ static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int which)\n ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);\n \n stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl);\n+\n+ cfmws_update_non_interleaved(false);\n }\n \n static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)\ndiff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h\nindex 998f495a98..931f5680bd 100644\n--- a/include/hw/cxl/cxl.h\n+++ b/include/hw/cxl/cxl.h\n@@ -71,4 +71,5 @@ CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp);\n typedef struct CXLDownstreamPort CXLDownstreamPort;\n DECLARE_INSTANCE_CHECKER(CXLDownstreamPort, CXL_DSP, TYPE_CXL_DSP)\n \n+bool cfmws_update_non_interleaved(bool commit);\n #endif\ndiff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h\nindex 393f312217..d295469301 100644\n--- a/include/hw/cxl/cxl_device.h\n+++ b/include/hw/cxl/cxl_device.h\n@@ -712,6 +712,7 @@ struct CXLType3Dev {\n uint64_t sn;\n \n /* State */\n+ MemoryRegion direct_mr[CXL_HDM_DECODER_COUNT];\n AddressSpace hostvmem_as;\n AddressSpace hostpmem_as;\n CXLComponentState cxl_cstate;\n", "prefixes": [ "v3", "2/2" ] }