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GET /api/patches/2196907/?format=api
{ "id": 2196907, "url": "http://patchwork.ozlabs.org/api/patches/2196907/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260216-eliza-pinctrl-v3-2-a7b086595651@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216-eliza-pinctrl-v3-2-a7b086595651@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-16T13:44:04", "name": "[v3,2/2] pinctrl: qcom: Add Eliza pinctrl driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cb32d0d1775a88c7982b9703de03da0105a4bbc2", "submitter": { "id": 92383, "url": "http://patchwork.ozlabs.org/api/people/92383/?format=api", "name": "Abel Vesa", "email": "abel.vesa@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260216-eliza-pinctrl-v3-2-a7b086595651@oss.qualcomm.com/mbox/", "series": [ { "id": 492312, "url": "http://patchwork.ozlabs.org/api/series/492312/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=492312", "date": "2026-02-16T13:44:03", "name": "pinctrl: qcom: Add support for Qualcomm Eliza SoC", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/492312/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196907/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196907/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-31718-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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"<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260216-eliza-pinctrl-v3-2-a7b086595651@oss.qualcomm.com>", "References": "<20260216-eliza-pinctrl-v3-0-a7b086595651@oss.qualcomm.com>", "In-Reply-To": "<20260216-eliza-pinctrl-v3-0-a7b086595651@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Abel Vesa <abel.vesa@oss.qualcomm.com>,\n Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,\n Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>", "X-Mailer": "b4 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a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22\n a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=tXnM-DOrMupGi_pzBnoA:9 a=QEXdDO2ut3YA:10\n a=NFOGd7dJGGMPyQGDc5-O:22", "X-Proofpoint-ORIG-GUID": "uPsz9U9GdbOeEZ0bZOPoIq0wZvsdBP0W", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-16_04,2026-02-16_03,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0\n lowpriorityscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602160116" }, "content": "Add pinctrl driver for TLMM block found in the Eliza SoC.\n\nReviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>\nReviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>\nReviewed-by: Bjorn Andersson <andersson@kernel.org>\nSigned-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>\n---\n drivers/pinctrl/qcom/Kconfig.msm | 10 +\n drivers/pinctrl/qcom/Makefile | 1 +\n drivers/pinctrl/qcom/pinctrl-eliza.c | 1548 ++++++++++++++++++++++++++++++++++\n 3 files changed, 1559 insertions(+)", "diff": "diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm\nindex 3e9e02774001..6df6159fa5f8 100644\n--- a/drivers/pinctrl/qcom/Kconfig.msm\n+++ b/drivers/pinctrl/qcom/Kconfig.msm\n@@ -15,6 +15,16 @@ config PINCTRL_APQ8084\n \t This is the pinctrl, pinmux, pinconf and gpiolib driver for the\n \t Qualcomm TLMM block found in the Qualcomm APQ8084 platform.\n \n+config PINCTRL_ELIZA\n+\ttristate \"Qualcomm Technologies Inc Eliza pin controller driver\"\n+\tdepends on ARM64 || COMPILE_TEST\n+\thelp\n+\t This is the pinctrl, pinmux, pinconf and gpiolib driver for the\n+\t Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)\n+\t block found on the Qualcomm Technologies Inc Eliza platform.\n+\t Say Y here to compile statically, or M here to compile it as a module.\n+\t If unsure, say N.\n+\n config PINCTRL_GLYMUR\n \ttristate \"Qualcomm Technologies Inc Glymur pin controller driver\"\n \tdepends on ARM64 || COMPILE_TEST\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex 4269d1781015..831103b3827b 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -3,6 +3,7 @@\n obj-$(CONFIG_PINCTRL_MSM)\t+= pinctrl-msm.o\n obj-$(CONFIG_PINCTRL_APQ8064)\t+= pinctrl-apq8064.o\n obj-$(CONFIG_PINCTRL_APQ8084)\t+= pinctrl-apq8084.o\n+obj-$(CONFIG_PINCTRL_ELIZA)\t+= pinctrl-eliza.o\n obj-$(CONFIG_PINCTRL_GLYMUR)\t+= pinctrl-glymur.o\n obj-$(CONFIG_PINCTRL_IPQ4019)\t+= pinctrl-ipq4019.o\n obj-$(CONFIG_PINCTRL_IPQ5018)\t+= pinctrl-ipq5018.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c\nnew file mode 100644\nindex 000000000000..1a2e6461a69b\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-eliza.c\n@@ -0,0 +1,1548 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+\n+#include \"pinctrl-msm.h\"\n+\n+#define REG_SIZE 0x1000\n+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)\t\\\n+\t{\t\t\t\t\t \\\n+\t\t.grp = PINCTRL_PINGROUP(\"gpio\" #id,\t\\\n+\t\t\tgpio##id##_pins,\t\t\\\n+\t\t\tARRAY_SIZE(gpio##id##_pins)),\t\\\n+\t\t.funcs = (int[]){\t\t\t\\\n+\t\t\tmsm_mux_gpio, /* gpio mode */\t\\\n+\t\t\tmsm_mux_##f1,\t\t\t\\\n+\t\t\tmsm_mux_##f2,\t\t\t\\\n+\t\t\tmsm_mux_##f3,\t\t\t\\\n+\t\t\tmsm_mux_##f4,\t\t\t\\\n+\t\t\tmsm_mux_##f5,\t\t\t\\\n+\t\t\tmsm_mux_##f6,\t\t\t\\\n+\t\t\tmsm_mux_##f7,\t\t\t\\\n+\t\t\tmsm_mux_##f8,\t\t\t\\\n+\t\t\tmsm_mux_##f9,\t\t\t\\\n+\t\t\tmsm_mux_##f10,\t\t\t\\\n+\t\t\tmsm_mux_##f11 /* egpio mode */\t\\\n+\t\t},\t\t\t\t\t\\\n+\t\t.nfuncs = 12,\t\t\t\t\\\n+\t\t.ctl_reg = REG_SIZE * id,\t\t\\\n+\t\t.io_reg = 0x4 + REG_SIZE * id,\t\t\\\n+\t\t.intr_cfg_reg = 0x8 + REG_SIZE * id,\t\\\n+\t\t.intr_status_reg = 0xc + REG_SIZE * id,\t\\\n+\t\t.intr_target_reg = 0x8 + REG_SIZE * id,\t\\\n+\t\t.mux_bit = 2,\t\t\t\\\n+\t\t.pull_bit = 0,\t\t\t\\\n+\t\t.drv_bit = 6,\t\t\t\\\n+\t\t.egpio_enable = 12,\t\t\\\n+\t\t.egpio_present = 11,\t\t\\\n+\t\t.oe_bit = 9,\t\t\t\\\n+\t\t.in_bit = 0,\t\t\t\\\n+\t\t.out_bit = 1,\t\t\t\\\n+\t\t.intr_enable_bit = 0,\t\t\\\n+\t\t.intr_status_bit = 0,\t\t\\\n+\t\t.intr_wakeup_present_bit = 6,\t\\\n+\t\t.intr_wakeup_enable_bit = 7,\t\\\n+\t\t.intr_target_bit = 5,\t\t\\\n+\t\t.intr_target_kpss_val = 3,\t\\\n+\t\t.intr_raw_status_bit = 4,\t\\\n+\t\t.intr_polarity_bit = 1,\t\t\\\n+\t\t.intr_detection_bit = 2,\t\\\n+\t\t.intr_detection_width = 2,\t\\\n+\t}\n+\n+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)\t\\\n+\t{\t\t\t\t\t \\\n+\t\t.grp = PINCTRL_PINGROUP(#pg_name,\t\\\n+\t\t\tpg_name##_pins,\t\t\t\\\n+\t\t\tARRAY_SIZE(pg_name##_pins)),\t\\\n+\t\t.ctl_reg = ctl,\t\t\t\t\\\n+\t\t.io_reg = 0,\t\t\t\t\\\n+\t\t.intr_cfg_reg = 0,\t\t\t\\\n+\t\t.intr_status_reg = 0,\t\t\t\\\n+\t\t.intr_target_reg = 0,\t\t\t\\\n+\t\t.mux_bit = -1,\t\t\t\t\\\n+\t\t.pull_bit = pull,\t\t\t\\\n+\t\t.drv_bit = drv,\t\t\t\t\\\n+\t\t.oe_bit = -1,\t\t\t\t\\\n+\t\t.in_bit = -1,\t\t\t\t\\\n+\t\t.out_bit = -1,\t\t\t\t\\\n+\t\t.intr_enable_bit = -1,\t\t\t\\\n+\t\t.intr_status_bit = -1,\t\t\t\\\n+\t\t.intr_target_bit = -1,\t\t\t\\\n+\t\t.intr_raw_status_bit = -1,\t\t\\\n+\t\t.intr_polarity_bit = -1,\t\t\\\n+\t\t.intr_detection_bit = -1,\t\t\\\n+\t\t.intr_detection_width = -1,\t\t\\\n+\t}\n+\n+#define UFS_RESET(pg_name, ctl, io)\t\t\t\\\n+\t{\t\t\t\t\t \\\n+\t\t.grp = PINCTRL_PINGROUP(#pg_name,\t\\\n+\t\t\tpg_name##_pins,\t\t\t\\\n+\t\t\tARRAY_SIZE(pg_name##_pins)), \\\n+\t\t.ctl_reg = ctl,\t\t\t\t\\\n+\t\t.io_reg = io,\t\t\t\t\\\n+\t\t.intr_cfg_reg = 0,\t\t\t\\\n+\t\t.intr_status_reg = 0,\t\t\t\\\n+\t\t.intr_target_reg = 0,\t\t\t\\\n+\t\t.mux_bit = -1,\t\t\t\t\\\n+\t\t.pull_bit = 3,\t\t\t\t\\\n+\t\t.drv_bit = 0,\t\t\t\t\\\n+\t\t.oe_bit = -1,\t\t\t\t\\\n+\t\t.in_bit = -1,\t\t\t\t\\\n+\t\t.out_bit = 0,\t\t\t\t\\\n+\t\t.intr_enable_bit = -1,\t\t\t\\\n+\t\t.intr_status_bit = -1,\t\t\t\\\n+\t\t.intr_target_bit = -1,\t\t\t\\\n+\t\t.intr_raw_status_bit = -1,\t\t\\\n+\t\t.intr_polarity_bit = -1,\t\t\\\n+\t\t.intr_detection_bit = -1,\t\t\\\n+\t\t.intr_detection_width = -1,\t\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc eliza_pins[] = {\n+\tPINCTRL_PIN(0, \"GPIO_0\"),\n+\tPINCTRL_PIN(1, \"GPIO_1\"),\n+\tPINCTRL_PIN(2, \"GPIO_2\"),\n+\tPINCTRL_PIN(3, \"GPIO_3\"),\n+\tPINCTRL_PIN(4, \"GPIO_4\"),\n+\tPINCTRL_PIN(5, \"GPIO_5\"),\n+\tPINCTRL_PIN(6, \"GPIO_6\"),\n+\tPINCTRL_PIN(7, \"GPIO_7\"),\n+\tPINCTRL_PIN(8, \"GPIO_8\"),\n+\tPINCTRL_PIN(9, \"GPIO_9\"),\n+\tPINCTRL_PIN(10, \"GPIO_10\"),\n+\tPINCTRL_PIN(11, \"GPIO_11\"),\n+\tPINCTRL_PIN(12, \"GPIO_12\"),\n+\tPINCTRL_PIN(13, \"GPIO_13\"),\n+\tPINCTRL_PIN(14, \"GPIO_14\"),\n+\tPINCTRL_PIN(15, \"GPIO_15\"),\n+\tPINCTRL_PIN(16, \"GPIO_16\"),\n+\tPINCTRL_PIN(17, \"GPIO_17\"),\n+\tPINCTRL_PIN(18, \"GPIO_18\"),\n+\tPINCTRL_PIN(19, \"GPIO_19\"),\n+\tPINCTRL_PIN(20, \"GPIO_20\"),\n+\tPINCTRL_PIN(21, \"GPIO_21\"),\n+\tPINCTRL_PIN(22, \"GPIO_22\"),\n+\tPINCTRL_PIN(23, \"GPIO_23\"),\n+\tPINCTRL_PIN(24, \"GPIO_24\"),\n+\tPINCTRL_PIN(25, \"GPIO_25\"),\n+\tPINCTRL_PIN(26, \"GPIO_26\"),\n+\tPINCTRL_PIN(27, \"GPIO_27\"),\n+\tPINCTRL_PIN(28, \"GPIO_28\"),\n+\tPINCTRL_PIN(29, \"GPIO_29\"),\n+\tPINCTRL_PIN(30, \"GPIO_30\"),\n+\tPINCTRL_PIN(31, \"GPIO_31\"),\n+\tPINCTRL_PIN(32, \"GPIO_32\"),\n+\tPINCTRL_PIN(33, \"GPIO_33\"),\n+\tPINCTRL_PIN(34, \"GPIO_34\"),\n+\tPINCTRL_PIN(35, \"GPIO_35\"),\n+\tPINCTRL_PIN(36, \"GPIO_36\"),\n+\tPINCTRL_PIN(37, \"GPIO_37\"),\n+\tPINCTRL_PIN(38, \"GPIO_38\"),\n+\tPINCTRL_PIN(39, \"GPIO_39\"),\n+\tPINCTRL_PIN(40, \"GPIO_40\"),\n+\tPINCTRL_PIN(41, \"GPIO_41\"),\n+\tPINCTRL_PIN(42, \"GPIO_42\"),\n+\tPINCTRL_PIN(43, \"GPIO_43\"),\n+\tPINCTRL_PIN(44, \"GPIO_44\"),\n+\tPINCTRL_PIN(45, \"GPIO_45\"),\n+\tPINCTRL_PIN(46, \"GPIO_46\"),\n+\tPINCTRL_PIN(47, \"GPIO_47\"),\n+\tPINCTRL_PIN(48, \"GPIO_48\"),\n+\tPINCTRL_PIN(49, \"GPIO_49\"),\n+\tPINCTRL_PIN(50, \"GPIO_50\"),\n+\tPINCTRL_PIN(51, \"GPIO_51\"),\n+\tPINCTRL_PIN(52, \"GPIO_52\"),\n+\tPINCTRL_PIN(53, \"GPIO_53\"),\n+\tPINCTRL_PIN(54, \"GPIO_54\"),\n+\tPINCTRL_PIN(55, \"GPIO_55\"),\n+\tPINCTRL_PIN(56, \"GPIO_56\"),\n+\tPINCTRL_PIN(57, \"GPIO_57\"),\n+\tPINCTRL_PIN(58, \"GPIO_58\"),\n+\tPINCTRL_PIN(59, \"GPIO_59\"),\n+\tPINCTRL_PIN(60, \"GPIO_60\"),\n+\tPINCTRL_PIN(61, \"GPIO_61\"),\n+\tPINCTRL_PIN(62, \"GPIO_62\"),\n+\tPINCTRL_PIN(63, \"GPIO_63\"),\n+\tPINCTRL_PIN(64, \"GPIO_64\"),\n+\tPINCTRL_PIN(65, \"GPIO_65\"),\n+\tPINCTRL_PIN(66, \"GPIO_66\"),\n+\tPINCTRL_PIN(67, \"GPIO_67\"),\n+\tPINCTRL_PIN(68, \"GPIO_68\"),\n+\tPINCTRL_PIN(69, \"GPIO_69\"),\n+\tPINCTRL_PIN(70, \"GPIO_70\"),\n+\tPINCTRL_PIN(71, \"GPIO_71\"),\n+\tPINCTRL_PIN(72, \"GPIO_72\"),\n+\tPINCTRL_PIN(73, \"GPIO_73\"),\n+\tPINCTRL_PIN(74, \"GPIO_74\"),\n+\tPINCTRL_PIN(75, \"GPIO_75\"),\n+\tPINCTRL_PIN(76, \"GPIO_76\"),\n+\tPINCTRL_PIN(77, \"GPIO_77\"),\n+\tPINCTRL_PIN(78, \"GPIO_78\"),\n+\tPINCTRL_PIN(79, \"GPIO_79\"),\n+\tPINCTRL_PIN(80, \"GPIO_80\"),\n+\tPINCTRL_PIN(81, \"GPIO_81\"),\n+\tPINCTRL_PIN(82, \"GPIO_82\"),\n+\tPINCTRL_PIN(83, \"GPIO_83\"),\n+\tPINCTRL_PIN(84, \"GPIO_84\"),\n+\tPINCTRL_PIN(85, \"GPIO_85\"),\n+\tPINCTRL_PIN(86, \"GPIO_86\"),\n+\tPINCTRL_PIN(87, \"GPIO_87\"),\n+\tPINCTRL_PIN(88, \"GPIO_88\"),\n+\tPINCTRL_PIN(89, \"GPIO_89\"),\n+\tPINCTRL_PIN(90, \"GPIO_90\"),\n+\tPINCTRL_PIN(91, \"GPIO_91\"),\n+\tPINCTRL_PIN(92, \"GPIO_92\"),\n+\tPINCTRL_PIN(93, \"GPIO_93\"),\n+\tPINCTRL_PIN(94, \"GPIO_94\"),\n+\tPINCTRL_PIN(95, \"GPIO_95\"),\n+\tPINCTRL_PIN(96, \"GPIO_96\"),\n+\tPINCTRL_PIN(97, \"GPIO_97\"),\n+\tPINCTRL_PIN(98, \"GPIO_98\"),\n+\tPINCTRL_PIN(99, \"GPIO_99\"),\n+\tPINCTRL_PIN(100, \"GPIO_100\"),\n+\tPINCTRL_PIN(101, \"GPIO_101\"),\n+\tPINCTRL_PIN(102, \"GPIO_102\"),\n+\tPINCTRL_PIN(103, \"GPIO_103\"),\n+\tPINCTRL_PIN(104, \"GPIO_104\"),\n+\tPINCTRL_PIN(105, \"GPIO_105\"),\n+\tPINCTRL_PIN(106, \"GPIO_106\"),\n+\tPINCTRL_PIN(107, \"GPIO_107\"),\n+\tPINCTRL_PIN(108, \"GPIO_108\"),\n+\tPINCTRL_PIN(109, \"GPIO_109\"),\n+\tPINCTRL_PIN(110, \"GPIO_110\"),\n+\tPINCTRL_PIN(111, \"GPIO_111\"),\n+\tPINCTRL_PIN(112, \"GPIO_112\"),\n+\tPINCTRL_PIN(113, \"GPIO_113\"),\n+\tPINCTRL_PIN(114, \"GPIO_114\"),\n+\tPINCTRL_PIN(115, \"GPIO_115\"),\n+\tPINCTRL_PIN(116, \"GPIO_116\"),\n+\tPINCTRL_PIN(117, \"GPIO_117\"),\n+\tPINCTRL_PIN(118, \"GPIO_118\"),\n+\tPINCTRL_PIN(119, \"GPIO_119\"),\n+\tPINCTRL_PIN(120, \"GPIO_120\"),\n+\tPINCTRL_PIN(121, \"GPIO_121\"),\n+\tPINCTRL_PIN(122, \"GPIO_122\"),\n+\tPINCTRL_PIN(123, \"GPIO_123\"),\n+\tPINCTRL_PIN(124, \"GPIO_124\"),\n+\tPINCTRL_PIN(125, \"GPIO_125\"),\n+\tPINCTRL_PIN(126, \"GPIO_126\"),\n+\tPINCTRL_PIN(127, \"GPIO_127\"),\n+\tPINCTRL_PIN(128, \"GPIO_128\"),\n+\tPINCTRL_PIN(129, \"GPIO_129\"),\n+\tPINCTRL_PIN(130, \"GPIO_130\"),\n+\tPINCTRL_PIN(131, \"GPIO_131\"),\n+\tPINCTRL_PIN(132, \"GPIO_132\"),\n+\tPINCTRL_PIN(133, \"GPIO_133\"),\n+\tPINCTRL_PIN(134, \"GPIO_134\"),\n+\tPINCTRL_PIN(135, \"GPIO_135\"),\n+\tPINCTRL_PIN(136, \"GPIO_136\"),\n+\tPINCTRL_PIN(137, \"GPIO_137\"),\n+\tPINCTRL_PIN(138, \"GPIO_138\"),\n+\tPINCTRL_PIN(139, \"GPIO_139\"),\n+\tPINCTRL_PIN(140, \"GPIO_140\"),\n+\tPINCTRL_PIN(141, \"GPIO_141\"),\n+\tPINCTRL_PIN(142, \"GPIO_142\"),\n+\tPINCTRL_PIN(143, \"GPIO_143\"),\n+\tPINCTRL_PIN(144, \"GPIO_144\"),\n+\tPINCTRL_PIN(145, \"GPIO_145\"),\n+\tPINCTRL_PIN(146, \"GPIO_146\"),\n+\tPINCTRL_PIN(147, \"GPIO_147\"),\n+\tPINCTRL_PIN(148, \"GPIO_148\"),\n+\tPINCTRL_PIN(149, \"GPIO_149\"),\n+\tPINCTRL_PIN(150, \"GPIO_150\"),\n+\tPINCTRL_PIN(151, \"GPIO_151\"),\n+\tPINCTRL_PIN(152, \"GPIO_152\"),\n+\tPINCTRL_PIN(153, \"GPIO_153\"),\n+\tPINCTRL_PIN(154, \"GPIO_154\"),\n+\tPINCTRL_PIN(155, \"GPIO_155\"),\n+\tPINCTRL_PIN(156, \"GPIO_156\"),\n+\tPINCTRL_PIN(157, \"GPIO_157\"),\n+\tPINCTRL_PIN(158, \"GPIO_158\"),\n+\tPINCTRL_PIN(159, \"GPIO_159\"),\n+\tPINCTRL_PIN(160, \"GPIO_160\"),\n+\tPINCTRL_PIN(161, \"GPIO_161\"),\n+\tPINCTRL_PIN(162, \"GPIO_162\"),\n+\tPINCTRL_PIN(163, \"GPIO_163\"),\n+\tPINCTRL_PIN(164, \"GPIO_164\"),\n+\tPINCTRL_PIN(165, \"GPIO_165\"),\n+\tPINCTRL_PIN(166, \"GPIO_166\"),\n+\tPINCTRL_PIN(167, \"GPIO_167\"),\n+\tPINCTRL_PIN(168, \"GPIO_168\"),\n+\tPINCTRL_PIN(169, \"GPIO_169\"),\n+\tPINCTRL_PIN(170, \"GPIO_170\"),\n+\tPINCTRL_PIN(171, \"GPIO_171\"),\n+\tPINCTRL_PIN(172, \"GPIO_172\"),\n+\tPINCTRL_PIN(173, \"GPIO_173\"),\n+\tPINCTRL_PIN(174, \"GPIO_174\"),\n+\tPINCTRL_PIN(175, \"GPIO_175\"),\n+\tPINCTRL_PIN(176, \"GPIO_176\"),\n+\tPINCTRL_PIN(177, \"GPIO_177\"),\n+\tPINCTRL_PIN(178, \"GPIO_178\"),\n+\tPINCTRL_PIN(179, \"GPIO_179\"),\n+\tPINCTRL_PIN(180, \"GPIO_180\"),\n+\tPINCTRL_PIN(181, \"GPIO_181\"),\n+\tPINCTRL_PIN(182, \"GPIO_182\"),\n+\tPINCTRL_PIN(183, \"GPIO_183\"),\n+\tPINCTRL_PIN(184, \"GPIO_184\"),\n+\tPINCTRL_PIN(185, \"UFS_RESET\"),\n+};\n+\n+#define DECLARE_MSM_GPIO_PINS(pin) \\\n+\tstatic const unsigned int gpio##pin##_pins[] = { pin }\n+DECLARE_MSM_GPIO_PINS(0);\n+DECLARE_MSM_GPIO_PINS(1);\n+DECLARE_MSM_GPIO_PINS(2);\n+DECLARE_MSM_GPIO_PINS(3);\n+DECLARE_MSM_GPIO_PINS(4);\n+DECLARE_MSM_GPIO_PINS(5);\n+DECLARE_MSM_GPIO_PINS(6);\n+DECLARE_MSM_GPIO_PINS(7);\n+DECLARE_MSM_GPIO_PINS(8);\n+DECLARE_MSM_GPIO_PINS(9);\n+DECLARE_MSM_GPIO_PINS(10);\n+DECLARE_MSM_GPIO_PINS(11);\n+DECLARE_MSM_GPIO_PINS(12);\n+DECLARE_MSM_GPIO_PINS(13);\n+DECLARE_MSM_GPIO_PINS(14);\n+DECLARE_MSM_GPIO_PINS(15);\n+DECLARE_MSM_GPIO_PINS(16);\n+DECLARE_MSM_GPIO_PINS(17);\n+DECLARE_MSM_GPIO_PINS(18);\n+DECLARE_MSM_GPIO_PINS(19);\n+DECLARE_MSM_GPIO_PINS(20);\n+DECLARE_MSM_GPIO_PINS(21);\n+DECLARE_MSM_GPIO_PINS(22);\n+DECLARE_MSM_GPIO_PINS(23);\n+DECLARE_MSM_GPIO_PINS(24);\n+DECLARE_MSM_GPIO_PINS(25);\n+DECLARE_MSM_GPIO_PINS(26);\n+DECLARE_MSM_GPIO_PINS(27);\n+DECLARE_MSM_GPIO_PINS(28);\n+DECLARE_MSM_GPIO_PINS(29);\n+DECLARE_MSM_GPIO_PINS(30);\n+DECLARE_MSM_GPIO_PINS(31);\n+DECLARE_MSM_GPIO_PINS(32);\n+DECLARE_MSM_GPIO_PINS(33);\n+DECLARE_MSM_GPIO_PINS(34);\n+DECLARE_MSM_GPIO_PINS(35);\n+DECLARE_MSM_GPIO_PINS(36);\n+DECLARE_MSM_GPIO_PINS(37);\n+DECLARE_MSM_GPIO_PINS(38);\n+DECLARE_MSM_GPIO_PINS(39);\n+DECLARE_MSM_GPIO_PINS(40);\n+DECLARE_MSM_GPIO_PINS(41);\n+DECLARE_MSM_GPIO_PINS(42);\n+DECLARE_MSM_GPIO_PINS(43);\n+DECLARE_MSM_GPIO_PINS(44);\n+DECLARE_MSM_GPIO_PINS(45);\n+DECLARE_MSM_GPIO_PINS(46);\n+DECLARE_MSM_GPIO_PINS(47);\n+DECLARE_MSM_GPIO_PINS(48);\n+DECLARE_MSM_GPIO_PINS(49);\n+DECLARE_MSM_GPIO_PINS(50);\n+DECLARE_MSM_GPIO_PINS(51);\n+DECLARE_MSM_GPIO_PINS(52);\n+DECLARE_MSM_GPIO_PINS(53);\n+DECLARE_MSM_GPIO_PINS(54);\n+DECLARE_MSM_GPIO_PINS(55);\n+DECLARE_MSM_GPIO_PINS(56);\n+DECLARE_MSM_GPIO_PINS(57);\n+DECLARE_MSM_GPIO_PINS(58);\n+DECLARE_MSM_GPIO_PINS(59);\n+DECLARE_MSM_GPIO_PINS(60);\n+DECLARE_MSM_GPIO_PINS(61);\n+DECLARE_MSM_GPIO_PINS(62);\n+DECLARE_MSM_GPIO_PINS(63);\n+DECLARE_MSM_GPIO_PINS(64);\n+DECLARE_MSM_GPIO_PINS(65);\n+DECLARE_MSM_GPIO_PINS(66);\n+DECLARE_MSM_GPIO_PINS(67);\n+DECLARE_MSM_GPIO_PINS(68);\n+DECLARE_MSM_GPIO_PINS(69);\n+DECLARE_MSM_GPIO_PINS(70);\n+DECLARE_MSM_GPIO_PINS(71);\n+DECLARE_MSM_GPIO_PINS(72);\n+DECLARE_MSM_GPIO_PINS(73);\n+DECLARE_MSM_GPIO_PINS(74);\n+DECLARE_MSM_GPIO_PINS(75);\n+DECLARE_MSM_GPIO_PINS(76);\n+DECLARE_MSM_GPIO_PINS(77);\n+DECLARE_MSM_GPIO_PINS(78);\n+DECLARE_MSM_GPIO_PINS(79);\n+DECLARE_MSM_GPIO_PINS(80);\n+DECLARE_MSM_GPIO_PINS(81);\n+DECLARE_MSM_GPIO_PINS(82);\n+DECLARE_MSM_GPIO_PINS(83);\n+DECLARE_MSM_GPIO_PINS(84);\n+DECLARE_MSM_GPIO_PINS(85);\n+DECLARE_MSM_GPIO_PINS(86);\n+DECLARE_MSM_GPIO_PINS(87);\n+DECLARE_MSM_GPIO_PINS(88);\n+DECLARE_MSM_GPIO_PINS(89);\n+DECLARE_MSM_GPIO_PINS(90);\n+DECLARE_MSM_GPIO_PINS(91);\n+DECLARE_MSM_GPIO_PINS(92);\n+DECLARE_MSM_GPIO_PINS(93);\n+DECLARE_MSM_GPIO_PINS(94);\n+DECLARE_MSM_GPIO_PINS(95);\n+DECLARE_MSM_GPIO_PINS(96);\n+DECLARE_MSM_GPIO_PINS(97);\n+DECLARE_MSM_GPIO_PINS(98);\n+DECLARE_MSM_GPIO_PINS(99);\n+DECLARE_MSM_GPIO_PINS(100);\n+DECLARE_MSM_GPIO_PINS(101);\n+DECLARE_MSM_GPIO_PINS(102);\n+DECLARE_MSM_GPIO_PINS(103);\n+DECLARE_MSM_GPIO_PINS(104);\n+DECLARE_MSM_GPIO_PINS(105);\n+DECLARE_MSM_GPIO_PINS(106);\n+DECLARE_MSM_GPIO_PINS(107);\n+DECLARE_MSM_GPIO_PINS(108);\n+DECLARE_MSM_GPIO_PINS(109);\n+DECLARE_MSM_GPIO_PINS(110);\n+DECLARE_MSM_GPIO_PINS(111);\n+DECLARE_MSM_GPIO_PINS(112);\n+DECLARE_MSM_GPIO_PINS(113);\n+DECLARE_MSM_GPIO_PINS(114);\n+DECLARE_MSM_GPIO_PINS(115);\n+DECLARE_MSM_GPIO_PINS(116);\n+DECLARE_MSM_GPIO_PINS(117);\n+DECLARE_MSM_GPIO_PINS(118);\n+DECLARE_MSM_GPIO_PINS(119);\n+DECLARE_MSM_GPIO_PINS(120);\n+DECLARE_MSM_GPIO_PINS(121);\n+DECLARE_MSM_GPIO_PINS(122);\n+DECLARE_MSM_GPIO_PINS(123);\n+DECLARE_MSM_GPIO_PINS(124);\n+DECLARE_MSM_GPIO_PINS(125);\n+DECLARE_MSM_GPIO_PINS(126);\n+DECLARE_MSM_GPIO_PINS(127);\n+DECLARE_MSM_GPIO_PINS(128);\n+DECLARE_MSM_GPIO_PINS(129);\n+DECLARE_MSM_GPIO_PINS(130);\n+DECLARE_MSM_GPIO_PINS(131);\n+DECLARE_MSM_GPIO_PINS(132);\n+DECLARE_MSM_GPIO_PINS(133);\n+DECLARE_MSM_GPIO_PINS(134);\n+DECLARE_MSM_GPIO_PINS(135);\n+DECLARE_MSM_GPIO_PINS(136);\n+DECLARE_MSM_GPIO_PINS(137);\n+DECLARE_MSM_GPIO_PINS(138);\n+DECLARE_MSM_GPIO_PINS(139);\n+DECLARE_MSM_GPIO_PINS(140);\n+DECLARE_MSM_GPIO_PINS(141);\n+DECLARE_MSM_GPIO_PINS(142);\n+DECLARE_MSM_GPIO_PINS(143);\n+DECLARE_MSM_GPIO_PINS(144);\n+DECLARE_MSM_GPIO_PINS(145);\n+DECLARE_MSM_GPIO_PINS(146);\n+DECLARE_MSM_GPIO_PINS(147);\n+DECLARE_MSM_GPIO_PINS(148);\n+DECLARE_MSM_GPIO_PINS(149);\n+DECLARE_MSM_GPIO_PINS(150);\n+DECLARE_MSM_GPIO_PINS(151);\n+DECLARE_MSM_GPIO_PINS(152);\n+DECLARE_MSM_GPIO_PINS(153);\n+DECLARE_MSM_GPIO_PINS(154);\n+DECLARE_MSM_GPIO_PINS(155);\n+DECLARE_MSM_GPIO_PINS(156);\n+DECLARE_MSM_GPIO_PINS(157);\n+DECLARE_MSM_GPIO_PINS(158);\n+DECLARE_MSM_GPIO_PINS(159);\n+DECLARE_MSM_GPIO_PINS(160);\n+DECLARE_MSM_GPIO_PINS(161);\n+DECLARE_MSM_GPIO_PINS(162);\n+DECLARE_MSM_GPIO_PINS(163);\n+DECLARE_MSM_GPIO_PINS(164);\n+DECLARE_MSM_GPIO_PINS(165);\n+DECLARE_MSM_GPIO_PINS(166);\n+DECLARE_MSM_GPIO_PINS(167);\n+DECLARE_MSM_GPIO_PINS(168);\n+DECLARE_MSM_GPIO_PINS(169);\n+DECLARE_MSM_GPIO_PINS(170);\n+DECLARE_MSM_GPIO_PINS(171);\n+DECLARE_MSM_GPIO_PINS(172);\n+DECLARE_MSM_GPIO_PINS(173);\n+DECLARE_MSM_GPIO_PINS(174);\n+DECLARE_MSM_GPIO_PINS(175);\n+DECLARE_MSM_GPIO_PINS(176);\n+DECLARE_MSM_GPIO_PINS(177);\n+DECLARE_MSM_GPIO_PINS(178);\n+DECLARE_MSM_GPIO_PINS(179);\n+DECLARE_MSM_GPIO_PINS(180);\n+DECLARE_MSM_GPIO_PINS(181);\n+DECLARE_MSM_GPIO_PINS(182);\n+DECLARE_MSM_GPIO_PINS(183);\n+DECLARE_MSM_GPIO_PINS(184);\n+\n+static const unsigned int ufs_reset_pins[] = { 185 };\n+\n+enum eliza_functions {\n+\tmsm_mux_gpio,\n+\tmsm_mux_aoss_cti,\n+\tmsm_mux_atest_char,\n+\tmsm_mux_atest_usb,\n+\tmsm_mux_audio_ext_mclk0,\n+\tmsm_mux_audio_ref_clk,\n+\tmsm_mux_cam_mclk,\n+\tmsm_mux_cci_async_in,\n+\tmsm_mux_cci_i2c_scl,\n+\tmsm_mux_cci_i2c_sda,\n+\tmsm_mux_cci_timer,\n+\tmsm_mux_coex_uart1_rx,\n+\tmsm_mux_coex_uart1_tx,\n+\tmsm_mux_coex_uart2_rx,\n+\tmsm_mux_coex_uart2_tx,\n+\tmsm_mux_dbg_out_clk,\n+\tmsm_mux_ddr_bist_complete,\n+\tmsm_mux_ddr_bist_fail,\n+\tmsm_mux_ddr_bist_start,\n+\tmsm_mux_ddr_bist_stop,\n+\tmsm_mux_ddr_pxi0,\n+\tmsm_mux_ddr_pxi1,\n+\tmsm_mux_dp0_hot,\n+\tmsm_mux_egpio,\n+\tmsm_mux_gcc_gp1,\n+\tmsm_mux_gcc_gp2,\n+\tmsm_mux_gcc_gp3,\n+\tmsm_mux_gnss_adc0,\n+\tmsm_mux_gnss_adc1,\n+\tmsm_mux_hdmi_ddc_scl,\n+\tmsm_mux_hdmi_ddc_sda,\n+\tmsm_mux_hdmi_dtest0,\n+\tmsm_mux_hdmi_dtest1,\n+\tmsm_mux_hdmi_hot_plug,\n+\tmsm_mux_hdmi_pixel_clk,\n+\tmsm_mux_hdmi_rcv_det,\n+\tmsm_mux_hdmi_tx_cec,\n+\tmsm_mux_host2wlan_sol,\n+\tmsm_mux_i2s0_data0,\n+\tmsm_mux_i2s0_data1,\n+\tmsm_mux_i2s0_sck,\n+\tmsm_mux_i2s0_ws,\n+\tmsm_mux_ibi_i3c,\n+\tmsm_mux_jitter_bist,\n+\tmsm_mux_mdp_esync0_out,\n+\tmsm_mux_mdp_esync1_out,\n+\tmsm_mux_mdp_vsync,\n+\tmsm_mux_mdp_vsync0_out,\n+\tmsm_mux_mdp_vsync11_out,\n+\tmsm_mux_mdp_vsync1_out,\n+\tmsm_mux_mdp_vsync2_out,\n+\tmsm_mux_mdp_vsync3_out,\n+\tmsm_mux_mdp_vsync_e,\n+\tmsm_mux_nav_gpio0,\n+\tmsm_mux_nav_gpio1,\n+\tmsm_mux_nav_gpio2,\n+\tmsm_mux_nav_gpio3,\n+\tmsm_mux_pcie0_clk_req_n,\n+\tmsm_mux_pcie1_clk_req_n,\n+\tmsm_mux_phase_flag,\n+\tmsm_mux_pll_bist_sync,\n+\tmsm_mux_pll_clk_aux,\n+\tmsm_mux_prng_rosc0,\n+\tmsm_mux_prng_rosc1,\n+\tmsm_mux_prng_rosc2,\n+\tmsm_mux_prng_rosc3,\n+\tmsm_mux_qdss_cti,\n+\tmsm_mux_qdss_gpio_traceclk,\n+\tmsm_mux_qdss_gpio_tracectl,\n+\tmsm_mux_qdss_gpio_tracedata,\n+\tmsm_mux_qlink_big_enable,\n+\tmsm_mux_qlink_big_request,\n+\tmsm_mux_qlink_little_enable,\n+\tmsm_mux_qlink_little_request,\n+\tmsm_mux_qlink_wmss,\n+\tmsm_mux_qspi0,\n+\tmsm_mux_qspi_clk,\n+\tmsm_mux_qspi_cs,\n+\tmsm_mux_qup1_se0,\n+\tmsm_mux_qup1_se1,\n+\tmsm_mux_qup1_se2,\n+\tmsm_mux_qup1_se3,\n+\tmsm_mux_qup1_se4,\n+\tmsm_mux_qup1_se5,\n+\tmsm_mux_qup1_se6,\n+\tmsm_mux_qup1_se7,\n+\tmsm_mux_qup2_se0,\n+\tmsm_mux_qup2_se1,\n+\tmsm_mux_qup2_se2,\n+\tmsm_mux_qup2_se3,\n+\tmsm_mux_qup2_se4,\n+\tmsm_mux_qup2_se5,\n+\tmsm_mux_qup2_se6,\n+\tmsm_mux_qup2_se7,\n+\tmsm_mux_resout_gpio,\n+\tmsm_mux_sd_write_protect,\n+\tmsm_mux_sdc1,\n+\tmsm_mux_sdc2,\n+\tmsm_mux_sdc2_fb_clk,\n+\tmsm_mux_tb_trig_sdc1,\n+\tmsm_mux_tb_trig_sdc2,\n+\tmsm_mux_tmess_prng0,\n+\tmsm_mux_tmess_prng1,\n+\tmsm_mux_tmess_prng2,\n+\tmsm_mux_tmess_prng3,\n+\tmsm_mux_tsense_pwm1,\n+\tmsm_mux_tsense_pwm2,\n+\tmsm_mux_tsense_pwm3,\n+\tmsm_mux_tsense_pwm4,\n+\tmsm_mux_uim0_clk,\n+\tmsm_mux_uim0_data,\n+\tmsm_mux_uim0_present,\n+\tmsm_mux_uim0_reset,\n+\tmsm_mux_uim1_clk,\n+\tmsm_mux_uim1_data,\n+\tmsm_mux_uim1_present,\n+\tmsm_mux_uim1_reset,\n+\tmsm_mux_usb0_hs,\n+\tmsm_mux_usb_phy,\n+\tmsm_mux_vfr_0,\n+\tmsm_mux_vfr_1,\n+\tmsm_mux_vsense_trigger_mirnat,\n+\tmsm_mux_wcn_sw_ctrl,\n+\tmsm_mux__,\n+};\n+\n+static const char *const gpio_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\",\t \"gpio3\", \"gpio4\", \"gpio5\",\n+\t\"gpio6\", \"gpio7\", \"gpio8\",\t \"gpio9\", \"gpio10\", \"gpio11\",\n+\t\"gpio12\", \"gpio13\", \"gpio16\",\t \"gpio17\", \"gpio18\", \"gpio19\",\n+\t\"gpio20\", \"gpio21\", \"gpio22\",\t \"gpio23\", \"gpio26\", \"gpio27\",\n+\t\"gpio28\", \"gpio29\", \"gpio30\",\t \"gpio31\", \"gpio32\", \"gpio33\",\n+\t\"gpio34\", \"gpio35\", \"gpio36\",\t \"gpio37\", \"gpio38\", \"gpio39\",\n+\t\"gpio40\", \"gpio42\", \"gpio44\",\t \"gpio45\", \"gpio46\", \"gpio47\",\n+\t\"gpio48\", \"gpio49\", \"gpio50\",\t \"gpio51\", \"gpio52\", \"gpio53\",\n+\t\"gpio54\", \"gpio55\", \"gpio56\",\t \"gpio57\", \"gpio58\", \"gpio59\",\n+\t\"gpio60\", \"gpio61\", \"gpio62\",\t \"gpio63\", \"gpio64\", \"gpio65\",\n+\t\"gpio66\", \"gpio67\", \"gpio68\",\t \"gpio69\", \"gpio70\", \"gpio71\",\n+\t\"gpio72\", \"gpio73\", \"gpio74\",\t \"gpio75\", \"gpio76\", \"gpio77\",\n+\t\"gpio78\", \"gpio79\", \"gpio80\",\t \"gpio81\", \"gpio82\", \"gpio84\",\n+\t\"gpio85\", \"gpio86\", \"gpio87\",\t \"gpio88\", \"gpio89\", \"gpio90\",\n+\t\"gpio91\", \"gpio92\", \"gpio93\",\t \"gpio94\", \"gpio95\", \"gpio96\",\n+\t\"gpio97\", \"gpio98\", \"gpio99\",\t \"gpio100\", \"gpio101\", \"gpio102\",\n+\t\"gpio103\", \"gpio104\", \"gpio105\", \"gpio106\", \"gpio107\", \"gpio108\",\n+\t\"gpio109\", \"gpio110\", \"gpio111\", \"gpio112\", \"gpio113\", \"gpio114\",\n+\t\"gpio115\", \"gpio116\", \"gpio117\", \"gpio118\", \"gpio119\", \"gpio120\",\n+\t\"gpio121\", \"gpio122\", \"gpio123\", \"gpio124\", \"gpio125\", \"gpio126\",\n+\t\"gpio127\", \"gpio128\", \"gpio129\", \"gpio130\", \"gpio131\", \"gpio132\",\n+\t\"gpio133\", \"gpio134\", \"gpio135\", \"gpio138\", \"gpio139\", \"gpio140\",\n+\t\"gpio141\", \"gpio142\", \"gpio143\", \"gpio144\", \"gpio145\", \"gpio146\",\n+\t\"gpio147\", \"gpio148\", \"gpio149\", \"gpio150\", \"gpio151\", \"gpio152\",\n+\t\"gpio153\", \"gpio154\", \"gpio155\", \"gpio156\", \"gpio157\", \"gpio158\",\n+\t\"gpio159\", \"gpio160\", \"gpio161\", \"gpio162\", \"gpio163\", \"gpio164\",\n+\t\"gpio165\", \"gpio166\", \"gpio167\", \"gpio168\", \"gpio169\", \"gpio170\",\n+\t\"gpio171\", \"gpio172\", \"gpio173\", \"gpio174\", \"gpio175\", \"gpio176\",\n+\t\"gpio177\", \"gpio178\", \"gpio179\", \"gpio180\", \"gpio181\", \"gpio182\",\n+\t\"gpio184\",\n+};\n+\n+static const char *const aoss_cti_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio26\", \"gpio27\",\n+};\n+\n+static const char *const atest_char_groups[] = {\n+\t\"gpio71\", \"gpio70\", \"gpio72\", \"gpio74\", \"gpio73\",\n+};\n+\n+static const char *const atest_usb_groups[] = {\n+\t\"gpio55\", \"gpio54\",\n+};\n+\n+static const char *const audio_ext_mclk0_groups[] = {\n+\t\"gpio69\",\n+};\n+\n+static const char *const audio_ref_clk_groups[] = {\n+\t\"gpio32\",\n+};\n+\n+static const char *const cam_mclk_groups[] = {\n+\t\"gpio65\", \"gpio66\", \"gpio67\", \"gpio68\", \"gpio69\",\n+};\n+\n+static const char *const cci_async_in_groups[] = {\n+\t\"gpio115\", \"gpio31\", \"gpio30\",\n+};\n+\n+static const char *const cci_i2c_scl_groups[] = {\n+\t\"gpio71\", \"gpio73\", \"gpio75\", \"gpio77\",\n+};\n+\n+static const char *const cci_i2c_sda_groups[] = {\n+\t\"gpio70\", \"gpio72\", \"gpio74\", \"gpio76\",\n+};\n+\n+static const char *const cci_timer_groups[] = {\n+\t\"gpio76\", \"gpio63\", \"gpio125\", \"gpio126\", \"gpio127\",\n+};\n+\n+static const char *const coex_uart1_rx_groups[] = {\n+\t\"gpio112\",\n+};\n+\n+static const char *const coex_uart1_tx_groups[] = {\n+\t\"gpio111\",\n+};\n+\n+static const char *const coex_uart2_rx_groups[] = {\n+\t\"gpio116\",\n+};\n+\n+static const char *const coex_uart2_tx_groups[] = {\n+\t\"gpio100\",\n+};\n+\n+static const char *const dbg_out_clk_groups[] = {\n+\t\"gpio81\",\n+};\n+\n+static const char *const ddr_bist_complete_groups[] = {\n+\t\"gpio52\",\n+};\n+\n+static const char *const ddr_bist_fail_groups[] = {\n+\t\"gpio147\",\n+};\n+\n+static const char *const ddr_bist_start_groups[] = {\n+\t\"gpio34\",\n+};\n+\n+static const char *const ddr_bist_stop_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const ddr_pxi0_groups[] = {\n+\t\"gpio54\", \"gpio55\",\n+};\n+\n+static const char *const ddr_pxi1_groups[] = {\n+\t\"gpio40\", \"gpio42\",\n+};\n+\n+static const char *const dp0_hot_groups[] = {\n+\t\"gpio55\",\n+};\n+\n+static const char *const egpio_groups[] = {\n+\t\"gpio28\", \"gpio29\", \"gpio30\",\t \"gpio31\", \"gpio138\", \"gpio139\",\n+\t\"gpio140\", \"gpio141\", \"gpio142\", \"gpio143\", \"gpio144\", \"gpio145\",\n+\t\"gpio146\", \"gpio147\", \"gpio148\", \"gpio149\", \"gpio150\", \"gpio151\",\n+\t\"gpio152\", \"gpio153\", \"gpio154\", \"gpio155\", \"gpio156\", \"gpio157\",\n+\t\"gpio158\", \"gpio159\", \"gpio160\", \"gpio161\", \"gpio162\", \"gpio163\",\n+\t\"gpio164\", \"gpio165\", \"gpio166\", \"gpio167\", \"gpio168\", \"gpio169\",\n+\t\"gpio170\", \"gpio171\", \"gpio172\", \"gpio173\", \"gpio174\", \"gpio175\",\n+\t\"gpio176\", \"gpio177\", \"gpio178\", \"gpio179\", \"gpio180\", \"gpio181\",\n+\t\"gpio182\", \"gpio184\",\n+};\n+\n+static const char *const gcc_gp1_groups[] = {\n+\t\"gpio27\", \"gpio53\",\n+};\n+\n+static const char *const gcc_gp2_groups[] = {\n+\t\"gpio32\", \"gpio35\",\n+};\n+\n+static const char *const gcc_gp3_groups[] = {\n+\t\"gpio30\", \"gpio33\",\n+};\n+\n+static const char *const gnss_adc0_groups[] = {\n+\t\"gpio42\", \"gpio55\",\n+};\n+\n+static const char *const gnss_adc1_groups[] = {\n+\t\"gpio40\", \"gpio54\",\n+};\n+\n+static const char *const hdmi_ddc_scl_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char *const hdmi_ddc_sda_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char *const hdmi_dtest0_groups[] = {\n+\t\"gpio132\",\n+};\n+\n+static const char *const hdmi_dtest1_groups[] = {\n+\t\"gpio133\",\n+};\n+\n+static const char *const hdmi_hot_plug_groups[] = {\n+\t\"gpio47\",\n+};\n+\n+static const char *const hdmi_pixel_clk_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char *const hdmi_rcv_det_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char *const hdmi_tx_cec_groups[] = {\n+\t\"gpio46\",\n+};\n+\n+static const char *const host2wlan_sol_groups[] = {\n+\t\"gpio33\",\n+};\n+\n+static const char *const i2s0_data0_groups[] = {\n+\t\"gpio64\",\n+};\n+\n+static const char *const i2s0_data1_groups[] = {\n+\t\"gpio63\",\n+};\n+\n+static const char *const i2s0_sck_groups[] = {\n+\t\"gpio60\",\n+};\n+\n+static const char *const i2s0_ws_groups[] = {\n+\t\"gpio61\",\n+};\n+\n+static const char *const ibi_i3c_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio4\", \"gpio5\",\t\"gpio12\", \"gpio13\",\n+\t\"gpio28\", \"gpio29\", \"gpio32\", \"gpio33\", \"gpio36\", \"gpio37\",\n+};\n+\n+static const char *const jitter_bist_groups[] = {\n+\t\"gpio77\",\n+};\n+\n+static const char *const mdp_esync0_out_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char *const mdp_esync1_out_groups[] = {\n+\t\"gpio12\",\n+};\n+\n+static const char *const mdp_vsync_groups[] = {\n+\t\"gpio16\", \"gpio17\", \"gpio79\", \"gpio100\", \"gpio120\", \"gpio121\",\n+};\n+\n+static const char *const mdp_vsync0_out_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char *const mdp_vsync11_out_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char *const mdp_vsync1_out_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char *const mdp_vsync2_out_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char *const mdp_vsync3_out_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char *const mdp_vsync_e_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char *const nav_gpio0_groups[] = {\n+\t\"gpio119\",\n+};\n+\n+static const char *const nav_gpio1_groups[] = {\n+\t\"gpio117\",\n+};\n+\n+static const char *const nav_gpio2_groups[] = {\n+\t\"gpio118\",\n+};\n+\n+static const char *const nav_gpio3_groups[] = {\n+\t\"gpio113\",\n+};\n+\n+static const char *const pcie0_clk_req_n_groups[] = {\n+\t\"gpio80\",\n+};\n+\n+static const char *const pcie1_clk_req_n_groups[] = {\n+\t\"gpio52\",\n+};\n+\n+static const char *const phase_flag_groups[] = {\n+\t\"gpio71\", \"gpio70\", \"gpio174\", \"gpio175\", \"gpio172\", \"gpio171\",\n+\t\"gpio170\", \"gpio169\", \"gpio168\", \"gpio167\", \"gpio166\", \"gpio165\",\n+\t\"gpio182\", \"gpio164\", \"gpio163\", \"gpio162\", \"gpio161\", \"gpio160\",\n+\t\"gpio159\", \"gpio158\", \"gpio157\", \"gpio80\", \"gpio78\", \"gpio181\",\n+\t\"gpio76\", \"gpio75\", \"gpio180\", \"gpio179\", \"gpio178\", \"gpio177\",\n+\t\"gpio176\", \"gpio173\",\n+};\n+\n+static const char *const pll_bist_sync_groups[] = {\n+\t\"gpio184\",\n+};\n+\n+static const char *const pll_clk_aux_groups[] = {\n+\t\"gpio135\",\n+};\n+\n+static const char *const prng_rosc0_groups[] = {\n+\t\"gpio67\",\n+};\n+\n+static const char *const prng_rosc1_groups[] = {\n+\t\"gpio69\",\n+};\n+\n+static const char *const prng_rosc2_groups[] = {\n+\t\"gpio76\",\n+};\n+\n+static const char *const prng_rosc3_groups[] = {\n+\t\"gpio74\",\n+};\n+\n+static const char *const qdss_cti_groups[] = {\n+\t\"gpio18\", \"gpio19\", \"gpio32\",\t\"gpio73\",\n+\t\"gpio74\", \"gpio154\", \"gpio176\", \"gpio184\",\n+};\n+\n+static const char *const qdss_gpio_traceclk_groups[] = {\n+\t\"gpio54\", \"gpio147\",\n+};\n+\n+static const char *const qdss_gpio_tracectl_groups[] = {\n+\t\"gpio72\", \"gpio144\",\n+};\n+\n+static const char *const qdss_gpio_tracedata_groups[] = {\n+\t\"gpio30\", \"gpio31\", \"gpio34\", \"gpio35\", \"gpio40\", \"gpio42\",\n+\t\"gpio52\", \"gpio53\", \"gpio65\", \"gpio66\", \"gpio67\", \"gpio114\",\n+\t\"gpio132\", \"gpio133\", \"gpio134\", \"gpio135\", \"gpio145\", \"gpio146\",\n+\t\"gpio155\", \"gpio156\", \"gpio163\", \"gpio164\", \"gpio167\", \"gpio168\",\n+\t\"gpio169\", \"gpio170\", \"gpio178\", \"gpio179\", \"gpio180\", \"gpio181\",\n+\t\"gpio182\",\n+};\n+\n+static const char *const qlink_big_enable_groups[] = {\n+\t\"gpio96\",\n+};\n+\n+static const char *const qlink_big_request_groups[] = {\n+\t\"gpio95\",\n+};\n+\n+static const char *const qlink_little_enable_groups[] = {\n+\t\"gpio93\",\n+};\n+\n+static const char *const qlink_little_request_groups[] = {\n+\t\"gpio92\",\n+};\n+\n+static const char *const qlink_wmss_groups[] = {\n+\t\"gpio94\",\n+};\n+\n+static const char *const qspi0_groups[] = {\n+\t\"gpio79\", \"gpio116\", \"gpio115\", \"gpio97\", \"gpio98\",\n+};\n+\n+static const char *const qspi_clk_groups[] = {\n+\t\"gpio99\",\n+};\n+\n+static const char *const qspi_cs_groups[] = {\n+\t\"gpio100\",\n+};\n+\n+static const char *const qup1_se0_groups[] = {\n+\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\",\n+};\n+\n+static const char *const qup1_se1_groups[] = {\n+\t\"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n+};\n+\n+static const char *const qup1_se2_groups[] = {\n+\t\"gpio52\", \"gpio53\", \"gpio54\", \"gpio52\", \"gpio55\", \"gpio53\", \"gpio40\", \"gpio42\", \"gpio30\",\n+};\n+\n+static const char *const qup1_se3_groups[] = {\n+\t\"gpio44\", \"gpio45\", \"gpio46\", \"gpio47\",\n+};\n+\n+static const char *const qup1_se4_groups[] = {\n+\t\"gpio36\", \"gpio37\", \"gpio37\", \"gpio36\",\n+};\n+\n+static const char *const qup1_se5_groups[] = {\n+\t\"gpio132\", \"gpio133\", \"gpio134\", \"gpio135\", \"gpio34\", \"gpio35\",\n+};\n+\n+static const char *const qup1_se6_groups[] = {\n+\t\"gpio40\", \"gpio42\", \"gpio54\", \"gpio42\", \"gpio40\", \"gpio55\",\n+};\n+\n+static const char *const qup1_se7_groups[] = {\n+\t\"gpio81\", \"gpio78\", \"gpio80\", \"gpio114\", \"gpio114\", \"gpio78\",\n+};\n+\n+static const char *const qup2_se0_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\n+};\n+\n+static const char *const qup2_se1_groups[] = {\n+\t\"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\",\n+};\n+\n+static const char *const qup2_se2_groups[] = {\n+\t\"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio16\", \"gpio17\", \"gpio18\",\n+};\n+\n+static const char *const qup2_se3_groups[] = {\n+\t\"gpio79\", \"gpio116\", \"gpio97\", \"gpio100\", \"gpio100\", \"gpio116\",\n+};\n+\n+static const char *const qup2_se4_groups[] = {\n+\t\"gpio12\", \"gpio13\", \"gpio26\", \"gpio27\",\n+};\n+\n+static const char *const qup2_se5_groups[] = {\n+\t\"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\",\n+};\n+\n+static const char *const qup2_se6_groups[] = {\n+\t\"gpio20\", \"gpio21\", \"gpio22\", \"gpio23\",\n+};\n+\n+static const char *const qup2_se7_groups[] = {\n+\t\"gpio27\", \"gpio26\", \"gpio13\", \"gpio12\",\n+};\n+\n+static const char *const resout_gpio_groups[] = {\n+\t\"gpio63\",\n+\t\"gpio69\",\n+\t\"gpio175\",\n+};\n+\n+static const char *const sd_write_protect_groups[] = {\n+\t\"gpio57\",\n+};\n+\n+static const char *const sdc1_groups[] = {\n+\t\"gpio121\", \"gpio123\", \"gpio124\", \"gpio125\",\n+\t\"gpio126\", \"gpio127\", \"gpio128\", \"gpio129\",\n+\t\"gpio130\", \"gpio131\", \"gpio120\",\n+};\n+\n+static const char *const sdc2_groups[] = {\n+\t\"gpio38\", \"gpio39\", \"gpio48\", \"gpio49\",\n+\t\"gpio51\", \"gpio62\",\n+};\n+\n+static const char *const sdc2_fb_clk_groups[] = {\n+\t\"gpio50\",\n+};\n+\n+static const char *const tb_trig_sdc1_groups[] = {\n+\t\"gpio34\",\n+};\n+\n+static const char *const tb_trig_sdc2_groups[] = {\n+\t\"gpio35\",\n+};\n+\n+static const char *const tmess_prng0_groups[] = {\n+\t\"gpio73\",\n+};\n+\n+static const char *const tmess_prng1_groups[] = {\n+\t\"gpio72\",\n+};\n+\n+static const char *const tmess_prng2_groups[] = {\n+\t\"gpio70\",\n+};\n+\n+static const char *const tmess_prng3_groups[] = {\n+\t\"gpio71\",\n+};\n+\n+static const char *const tsense_pwm1_groups[] = {\n+\t\"gpio56\",\n+};\n+\n+static const char *const tsense_pwm2_groups[] = {\n+\t\"gpio56\",\n+};\n+\n+static const char *const tsense_pwm3_groups[] = {\n+\t\"gpio56\",\n+};\n+\n+static const char *const tsense_pwm4_groups[] = {\n+\t\"gpio56\",\n+};\n+\n+static const char *const uim0_clk_groups[] = {\n+\t\"gpio85\",\n+};\n+\n+static const char *const uim0_data_groups[] = {\n+\t\"gpio84\",\n+};\n+\n+static const char *const uim0_present_groups[] = {\n+\t\"gpio87\",\n+};\n+\n+static const char *const uim0_reset_groups[] = {\n+\t\"gpio86\",\n+};\n+\n+static const char *const uim1_clk_groups[] = {\n+\t\"gpio98\", \"gpio89\",\n+};\n+\n+static const char *const uim1_data_groups[] = {\n+\t\"gpio97\", \"gpio88\",\n+};\n+\n+static const char *const uim1_present_groups[] = {\n+\t\"gpio100\", \"gpio91\",\n+};\n+\n+static const char *const uim1_reset_groups[] = {\n+\t\"gpio99\", \"gpio90\",\n+};\n+\n+static const char *const usb0_hs_groups[] = {\n+\t\"gpio56\",\n+};\n+\n+static const char *const usb_phy_groups[] = {\n+\t\"gpio122\",\n+};\n+\n+static const char *const vfr_0_groups[] = {\n+\t\"gpio63\",\n+};\n+\n+static const char *const vfr_1_groups[] = {\n+\t\"gpio117\",\n+};\n+\n+static const char *const vsense_trigger_mirnat_groups[] = {\n+\t\"gpio52\",\n+};\n+\n+static const char *const wcn_sw_ctrl_groups[] = {\n+\t\"gpio81\",\n+};\n+\n+static const struct pinfunction eliza_functions[] = {\n+\tMSM_GPIO_PIN_FUNCTION(gpio),\n+\tMSM_PIN_FUNCTION(aoss_cti),\n+\tMSM_PIN_FUNCTION(atest_char),\n+\tMSM_PIN_FUNCTION(atest_usb),\n+\tMSM_PIN_FUNCTION(audio_ext_mclk0),\n+\tMSM_PIN_FUNCTION(audio_ref_clk),\n+\tMSM_PIN_FUNCTION(cam_mclk),\n+\tMSM_PIN_FUNCTION(cci_async_in),\n+\tMSM_PIN_FUNCTION(cci_i2c_scl),\n+\tMSM_PIN_FUNCTION(cci_i2c_sda),\n+\tMSM_PIN_FUNCTION(cci_timer),\n+\tMSM_PIN_FUNCTION(coex_uart1_rx),\n+\tMSM_PIN_FUNCTION(coex_uart1_tx),\n+\tMSM_PIN_FUNCTION(coex_uart2_rx),\n+\tMSM_PIN_FUNCTION(coex_uart2_tx),\n+\tMSM_PIN_FUNCTION(dbg_out_clk),\n+\tMSM_PIN_FUNCTION(ddr_bist_complete),\n+\tMSM_PIN_FUNCTION(ddr_bist_fail),\n+\tMSM_PIN_FUNCTION(ddr_bist_start),\n+\tMSM_PIN_FUNCTION(ddr_bist_stop),\n+\tMSM_PIN_FUNCTION(ddr_pxi0),\n+\tMSM_PIN_FUNCTION(ddr_pxi1),\n+\tMSM_PIN_FUNCTION(dp0_hot),\n+\tMSM_PIN_FUNCTION(egpio),\n+\tMSM_PIN_FUNCTION(gcc_gp1),\n+\tMSM_PIN_FUNCTION(gcc_gp2),\n+\tMSM_PIN_FUNCTION(gcc_gp3),\n+\tMSM_PIN_FUNCTION(gnss_adc0),\n+\tMSM_PIN_FUNCTION(gnss_adc1),\n+\tMSM_PIN_FUNCTION(hdmi_ddc_scl),\n+\tMSM_PIN_FUNCTION(hdmi_ddc_sda),\n+\tMSM_PIN_FUNCTION(hdmi_dtest0),\n+\tMSM_PIN_FUNCTION(hdmi_dtest1),\n+\tMSM_PIN_FUNCTION(hdmi_hot_plug),\n+\tMSM_PIN_FUNCTION(hdmi_pixel_clk),\n+\tMSM_PIN_FUNCTION(hdmi_rcv_det),\n+\tMSM_PIN_FUNCTION(hdmi_tx_cec),\n+\tMSM_PIN_FUNCTION(host2wlan_sol),\n+\tMSM_PIN_FUNCTION(i2s0_data0),\n+\tMSM_PIN_FUNCTION(i2s0_data1),\n+\tMSM_PIN_FUNCTION(i2s0_sck),\n+\tMSM_PIN_FUNCTION(i2s0_ws),\n+\tMSM_PIN_FUNCTION(ibi_i3c),\n+\tMSM_PIN_FUNCTION(jitter_bist),\n+\tMSM_PIN_FUNCTION(mdp_esync0_out),\n+\tMSM_PIN_FUNCTION(mdp_esync1_out),\n+\tMSM_PIN_FUNCTION(mdp_vsync),\n+\tMSM_PIN_FUNCTION(mdp_vsync0_out),\n+\tMSM_PIN_FUNCTION(mdp_vsync11_out),\n+\tMSM_PIN_FUNCTION(mdp_vsync1_out),\n+\tMSM_PIN_FUNCTION(mdp_vsync2_out),\n+\tMSM_PIN_FUNCTION(mdp_vsync3_out),\n+\tMSM_PIN_FUNCTION(mdp_vsync_e),\n+\tMSM_PIN_FUNCTION(nav_gpio0),\n+\tMSM_PIN_FUNCTION(nav_gpio1),\n+\tMSM_PIN_FUNCTION(nav_gpio2),\n+\tMSM_PIN_FUNCTION(nav_gpio3),\n+\tMSM_PIN_FUNCTION(pcie0_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie1_clk_req_n),\n+\tMSM_PIN_FUNCTION(phase_flag),\n+\tMSM_PIN_FUNCTION(pll_bist_sync),\n+\tMSM_PIN_FUNCTION(pll_clk_aux),\n+\tMSM_PIN_FUNCTION(prng_rosc0),\n+\tMSM_PIN_FUNCTION(prng_rosc1),\n+\tMSM_PIN_FUNCTION(prng_rosc2),\n+\tMSM_PIN_FUNCTION(prng_rosc3),\n+\tMSM_PIN_FUNCTION(qdss_cti),\n+\tMSM_PIN_FUNCTION(qdss_gpio_traceclk),\n+\tMSM_PIN_FUNCTION(qdss_gpio_tracectl),\n+\tMSM_PIN_FUNCTION(qdss_gpio_tracedata),\n+\tMSM_PIN_FUNCTION(qlink_big_enable),\n+\tMSM_PIN_FUNCTION(qlink_big_request),\n+\tMSM_PIN_FUNCTION(qlink_little_enable),\n+\tMSM_PIN_FUNCTION(qlink_little_request),\n+\tMSM_PIN_FUNCTION(qlink_wmss),\n+\tMSM_PIN_FUNCTION(qspi0),\n+\tMSM_PIN_FUNCTION(qspi_clk),\n+\tMSM_PIN_FUNCTION(qspi_cs),\n+\tMSM_PIN_FUNCTION(qup1_se0),\n+\tMSM_PIN_FUNCTION(qup1_se1),\n+\tMSM_PIN_FUNCTION(qup1_se2),\n+\tMSM_PIN_FUNCTION(qup1_se3),\n+\tMSM_PIN_FUNCTION(qup1_se4),\n+\tMSM_PIN_FUNCTION(qup1_se5),\n+\tMSM_PIN_FUNCTION(qup1_se6),\n+\tMSM_PIN_FUNCTION(qup1_se7),\n+\tMSM_PIN_FUNCTION(qup2_se0),\n+\tMSM_PIN_FUNCTION(qup2_se1),\n+\tMSM_PIN_FUNCTION(qup2_se2),\n+\tMSM_PIN_FUNCTION(qup2_se3),\n+\tMSM_PIN_FUNCTION(qup2_se4),\n+\tMSM_PIN_FUNCTION(qup2_se5),\n+\tMSM_PIN_FUNCTION(qup2_se6),\n+\tMSM_PIN_FUNCTION(qup2_se7),\n+\tMSM_PIN_FUNCTION(resout_gpio),\n+\tMSM_PIN_FUNCTION(sd_write_protect),\n+\tMSM_PIN_FUNCTION(sdc1),\n+\tMSM_PIN_FUNCTION(sdc2),\n+\tMSM_PIN_FUNCTION(sdc2_fb_clk),\n+\tMSM_PIN_FUNCTION(tb_trig_sdc1),\n+\tMSM_PIN_FUNCTION(tb_trig_sdc2),\n+\tMSM_PIN_FUNCTION(tmess_prng0),\n+\tMSM_PIN_FUNCTION(tmess_prng1),\n+\tMSM_PIN_FUNCTION(tmess_prng2),\n+\tMSM_PIN_FUNCTION(tmess_prng3),\n+\tMSM_PIN_FUNCTION(tsense_pwm1),\n+\tMSM_PIN_FUNCTION(tsense_pwm2),\n+\tMSM_PIN_FUNCTION(tsense_pwm3),\n+\tMSM_PIN_FUNCTION(tsense_pwm4),\n+\tMSM_PIN_FUNCTION(uim0_clk),\n+\tMSM_PIN_FUNCTION(uim0_data),\n+\tMSM_PIN_FUNCTION(uim0_present),\n+\tMSM_PIN_FUNCTION(uim0_reset),\n+\tMSM_PIN_FUNCTION(uim1_clk),\n+\tMSM_PIN_FUNCTION(uim1_data),\n+\tMSM_PIN_FUNCTION(uim1_present),\n+\tMSM_PIN_FUNCTION(uim1_reset),\n+\tMSM_PIN_FUNCTION(usb0_hs),\n+\tMSM_PIN_FUNCTION(usb_phy),\n+\tMSM_PIN_FUNCTION(vfr_0),\n+\tMSM_PIN_FUNCTION(vfr_1),\n+\tMSM_PIN_FUNCTION(vsense_trigger_mirnat),\n+\tMSM_PIN_FUNCTION(wcn_sw_ctrl),\n+};\n+\n+/* Every pin is maintained as a single group, and missing or non-existing pin\n+ * would be maintained as dummy group to synchronize pin group index with\n+ * pin descriptor registered with pinctrl core.\n+ * Clients would not be able to request these dummy pin groups.\n+ */\n+static const struct msm_pingroup eliza_groups[] = {\n+\t[0] = PINGROUP(0, qup2_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _),\n+\t[1] = PINGROUP(1, qup2_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _),\n+\t[2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, _),\n+\t[3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, _),\n+\t[4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),\n+\t[5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),\n+\t[6] = PINGROUP(6, qup2_se1, hdmi_ddc_scl, _, _, _, _, _, _, _, _, _),\n+\t[7] = PINGROUP(7, qup2_se1, hdmi_ddc_sda, _, _, _, _, _, _, _, _, _),\n+\t[8] = PINGROUP(8, qup2_se2, _, _, _, _, _, _, _, _, _, _),\n+\t[9] = PINGROUP(9, qup2_se2, _, _, _, _, _, _, _, _, _, _),\n+\t[10] = PINGROUP(10, qup2_se2, _, _, _, _, _, _, _, _, _, _),\n+\t[11] = PINGROUP(11, qup2_se2, _, _, _, _, _, _, _, _, _, _),\n+\t[12] = PINGROUP(12, qup2_se4, ibi_i3c, mdp_esync1_out, qup2_se7, _, _, _, _, _, _, _),\n+\t[13] = PINGROUP(13, qup2_se4, ibi_i3c, mdp_vsync_e, mdp_esync0_out, qup2_se7, _, _, _, _, _, _),\n+\t[14] = PINGROUP(14, _, _, _, _, _, _, _, _, _, _, _),\n+\t[15] = PINGROUP(15, _, _, _, _, _, _, _, _, _, _, _),\n+\t[16] = PINGROUP(16, qup2_se5, qup2_se2, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, _, _, _, _, _, _),\n+\t[17] = PINGROUP(17, qup2_se5, qup2_se2, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, _, _, _, _, _, _),\n+\t[18] = PINGROUP(18, qup2_se5, qup2_se2, hdmi_pixel_clk, _, qdss_cti, _, _, _, _, _, _),\n+\t[19] = PINGROUP(19, qup2_se5, hdmi_rcv_det, _, qdss_cti, _, _, _, _, _, _, _),\n+\t[20] = PINGROUP(20, qup2_se6, _, _, _, _, _, _, _, _, _, _),\n+\t[21] = PINGROUP(21, qup2_se6, _, _, _, _, _, _, _, _, _, _),\n+\t[22] = PINGROUP(22, qup2_se6, _, _, _, _, _, _, _, _, _, _),\n+\t[23] = PINGROUP(23, qup2_se6, _, _, _, _, _, _, _, _, _, _),\n+\t[24] = PINGROUP(24, _, _, _, _, _, _, _, _, _, _, _),\n+\t[25] = PINGROUP(25, _, _, _, _, _, _, _, _, _, _, _),\n+\t[26] = PINGROUP(26, qup2_se4, aoss_cti, qup2_se7, _, _, _, _, _, _, _, _),\n+\t[27] = PINGROUP(27, qup2_se4, aoss_cti, mdp_vsync11_out, qup2_se7, gcc_gp1, _, _, _, _, _, _),\n+\t[28] = PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n+\t[29] = PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n+\t[30] = PINGROUP(30, qup1_se0, qup1_se2, cci_async_in, gcc_gp3, qdss_gpio_tracedata, _, _, _, _, _, egpio),\n+\t[31] = PINGROUP(31, qup1_se0, cci_async_in, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[32] = PINGROUP(32, qup1_se1, ibi_i3c, audio_ref_clk, gcc_gp2, qdss_cti, _, _, _, _, _, _),\n+\t[33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),\n+\t[34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),\n+\t[35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),\n+\t[36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),\n+\t[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),\n+\t[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),\n+\t[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),\n+\t[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),\n+\t[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _),\n+\t[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),\n+\t[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _),\n+\t[44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _),\n+\t[45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _),\n+\t[46] = PINGROUP(46, qup1_se3, hdmi_tx_cec, _, _, _, _, _, _, _, _, _),\n+\t[47] = PINGROUP(47, qup1_se3, hdmi_hot_plug, _, _, _, _, _, _, _, _, _),\n+\t[48] = PINGROUP(48, _, _, _, _, _, _, _, _, _, _, _),\n+\t[49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _),\n+\t[50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),\n+\t[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _),\n+\t[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),\n+\t[53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),\n+\t[54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),\n+\t[55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),\n+\t[56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),\n+\t[57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),\n+\t[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _),\n+\t[59] = PINGROUP(59, _, _, _, _, _, _, _, _, _, _, _),\n+\t[60] = PINGROUP(60, i2s0_sck, _, _, _, _, _, _, _, _, _, _),\n+\t[61] = PINGROUP(61, i2s0_ws, _, _, _, _, _, _, _, _, _, _),\n+\t[62] = PINGROUP(62, _, _, _, _, _, _, _, _, _, _, _),\n+\t[63] = PINGROUP(63, resout_gpio, i2s0_data1, cci_timer, vfr_0, _, _, _, _, _, _, _),\n+\t[64] = PINGROUP(64, i2s0_data0, _, _, _, _, _, _, _, _, _, _),\n+\t[65] = PINGROUP(65, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _),\n+\t[66] = PINGROUP(66, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _),\n+\t[67] = PINGROUP(67, cam_mclk, prng_rosc0, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),\n+\t[68] = PINGROUP(68, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n+\t[69] = PINGROUP(69, cam_mclk, audio_ext_mclk0, resout_gpio, prng_rosc1, _, _, _, _, _, _, _),\n+\t[70] = PINGROUP(70, cci_i2c_sda, tmess_prng2, _, phase_flag, atest_char, _, _, _, _, _, _),\n+\t[71] = PINGROUP(71, cci_i2c_scl, tmess_prng3, _, phase_flag, atest_char, _, _, _, _, _, _),\n+\t[72] = PINGROUP(72, cci_i2c_sda, tmess_prng1, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _),\n+\t[73] = PINGROUP(73, cci_i2c_scl, tmess_prng0, qdss_cti, atest_char, _, _, _, _, _, _, _),\n+\t[74] = PINGROUP(74, cci_i2c_sda, prng_rosc3, qdss_cti, atest_char, _, _, _, _, _, _, _),\n+\t[75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),\n+\t[76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _),\n+\t[77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _),\n+\t[78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),\n+\t[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _),\n+\t[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),\n+\t[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _),\n+\t[82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _),\n+\t[83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _),\n+\t[84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _),\n+\t[85] = PINGROUP(85, uim0_clk, _, _, _, _, _, _, _, _, _, _),\n+\t[86] = PINGROUP(86, uim0_reset, _, _, _, _, _, _, _, _, _, _),\n+\t[87] = PINGROUP(87, uim0_present, _, _, _, _, _, _, _, _, _, _),\n+\t[88] = PINGROUP(88, uim1_data, _, _, _, _, _, _, _, _, _, _),\n+\t[89] = PINGROUP(89, uim1_clk, _, _, _, _, _, _, _, _, _, _),\n+\t[90] = PINGROUP(90, uim1_reset, _, _, _, _, _, _, _, _, _, _),\n+\t[91] = PINGROUP(91, uim1_present, _, _, _, _, _, _, _, _, _, _),\n+\t[92] = PINGROUP(92, qlink_little_request, _, _, _, _, _, _, _, _, _, _),\n+\t[93] = PINGROUP(93, qlink_little_enable, _, _, _, _, _, _, _, _, _, _),\n+\t[94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _),\n+\t[95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _),\n+\t[96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _),\n+\t[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _),\n+\t[98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _),\n+\t[99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _),\n+\t[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _),\n+\t[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),\n+\t[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _),\n+\t[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _),\n+\t[104] = PINGROUP(104, _, _, _, _, _, _, _, _, _, _, _),\n+\t[105] = PINGROUP(105, _, _, _, _, _, _, _, _, _, _, _),\n+\t[106] = PINGROUP(106, _, _, _, _, _, _, _, _, _, _, _),\n+\t[107] = PINGROUP(107, _, _, _, _, _, _, _, _, _, _, _),\n+\t[108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _, _),\n+\t[109] = PINGROUP(109, _, _, _, _, _, _, _, _, _, _, _),\n+\t[110] = PINGROUP(110, _, _, _, _, _, _, _, _, _, _, _),\n+\t[111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _),\n+\t[112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _),\n+\t[113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _),\n+\t[114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),\n+\t[115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _),\n+\t[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _),\n+\t[117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _),\n+\t[118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _),\n+\t[119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _),\n+\t[120] = PINGROUP(120, sdc1, mdp_vsync, _, _, _, _, _, _, _, _, _),\n+\t[121] = PINGROUP(121, sdc1, mdp_vsync, _, _, _, _, _, _, _, _, _),\n+\t[122] = PINGROUP(122, usb_phy, _, _, _, _, _, _, _, _, _, _),\n+\t[123] = PINGROUP(123, sdc1, _, _, _, _, _, _, _, _, _, _),\n+\t[124] = PINGROUP(124, sdc1, _, _, _, _, _, _, _, _, _, _),\n+\t[125] = PINGROUP(125, sdc1, cci_timer, _, _, _, _, _, _, _, _, _),\n+\t[126] = PINGROUP(126, sdc1, cci_timer, _, _, _, _, _, _, _, _, _),\n+\t[127] = PINGROUP(127, sdc1, cci_timer, _, _, _, _, _, _, _, _, _),\n+\t[128] = PINGROUP(128, sdc1, _, _, _, _, _, _, _, _, _, _),\n+\t[129] = PINGROUP(129, sdc1, _, _, _, _, _, _, _, _, _, _),\n+\t[130] = PINGROUP(130, sdc1, _, _, _, _, _, _, _, _, _, _),\n+\t[131] = PINGROUP(131, sdc1, _, _, _, _, _, _, _, _, _, _),\n+\t[132] = PINGROUP(132, qup1_se5, _, qdss_gpio_tracedata, hdmi_dtest0, _, _, _, _, _, _, _),\n+\t[133] = PINGROUP(133, qup1_se5, _, qdss_gpio_tracedata, hdmi_dtest1, _, _, _, _, _, _, _),\n+\t[134] = PINGROUP(134, qup1_se5, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _),\n+\t[135] = PINGROUP(135, qup1_se5, _, pll_clk_aux, qdss_gpio_tracedata, _, _, _, _, _, _, _),\n+\t[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _),\n+\t[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _),\n+\t[138] = PINGROUP(138, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[139] = PINGROUP(139, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[144] = PINGROUP(144, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),\n+\t[145] = PINGROUP(145, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _, egpio),\n+\t[146] = PINGROUP(146, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),\n+\t[147] = PINGROUP(147, ddr_bist_fail, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[149] = PINGROUP(149, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[150] = PINGROUP(150, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, egpio),\n+\t[154] = PINGROUP(154, qdss_cti, _, _, _, _, _, _, _, _, _, egpio),\n+\t[155] = PINGROUP(155, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),\n+\t[156] = PINGROUP(156, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),\n+\t[157] = PINGROUP(157, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[158] = PINGROUP(158, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[159] = PINGROUP(159, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[160] = PINGROUP(160, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[161] = PINGROUP(161, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[162] = PINGROUP(162, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[163] = PINGROUP(163, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[164] = PINGROUP(164, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[165] = PINGROUP(165, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[166] = PINGROUP(166, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[167] = PINGROUP(167, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[168] = PINGROUP(168, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[169] = PINGROUP(169, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[170] = PINGROUP(170, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[171] = PINGROUP(171, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[172] = PINGROUP(172, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[173] = PINGROUP(173, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[174] = PINGROUP(174, _, phase_flag, _, _, _, _, _, _, _, _, egpio),\n+\t[175] = PINGROUP(175, resout_gpio, _, phase_flag, _, _, _, _, _, _, _, egpio),\n+\t[176] = PINGROUP(176, _, phase_flag, qdss_cti, _, _, _, _, _, _, _, egpio),\n+\t[177] = PINGROUP(177, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[178] = PINGROUP(178, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[179] = PINGROUP(179, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[180] = PINGROUP(180, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[181] = PINGROUP(181, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[182] = PINGROUP(182, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n+\t[183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, _),\n+\t[184] = PINGROUP(184, pll_bist_sync, qdss_cti, _, _, _, _, _, _, _, _, egpio),\n+\t[185] = UFS_RESET(ufs_reset, 0xc9004, 0xca000),\n+};\n+\n+static const struct msm_gpio_wakeirq_map eliza_pdc_map[] = {\n+\t{ 0, 82 }, { 3, 87 }, { 4, 90 },\t { 6, 68 },\t{ 7, 153 },\n+\t{ 11, 85 }, { 12, 107 }, { 13, 106 }, { 16, 88 },\t{ 17, 70 },\n+\t{ 18, 134 }, { 19, 79 }, { 23, 80 },\t { 26, 91 },\t{ 27, 74 },\n+\t{ 28, 137 }, { 29, 138 }, { 30, 139 }, { 31, 140 },\t{ 32, 117 },\n+\t{ 34, 100 }, { 35, 98 }, { 36, 141 }, { 39, 89 },\t{ 40, 142 },\n+\t{ 42, 143 }, { 44, 101 }, { 45, 144 }, { 46, 145 },\t{ 47, 146 },\n+\t{ 49, 75 }, { 51, 147 }, { 52, 148 }, { 53, 149 },\t{ 54, 150 },\n+\t{ 55, 151 }, { 56, 152 }, { 58, 71 },\t { 59, 155 },\t{ 63, 99 },\n+\t{ 78, 156 }, { 79, 76 }, { 80, 157 }, { 81, 69 },\t{ 87, 158 },\n+\t{ 91, 67 }, { 92, 159 }, { 95, 160 }, { 98, 161 },\t{ 99, 162 },\n+\t{ 100, 83 }, { 108, 154 }, { 109, 84 }, { 112, 86 },\t{ 113, 92 },\n+\t{ 114, 93 }, { 115, 110 }, { 116, 94 }, { 117, 77 },\t{ 118, 108 },\n+\t{ 119, 95 }, { 120, 81 }, { 121, 96 }, { 122, 97 },\t{ 123, 102 },\n+\t{ 125, 103 }, { 127, 104 }, { 128, 105 }, { 129, 78 },\t{ 130, 112 },\n+\t{ 131, 113 }, { 133, 114 }, { 135, 115 }, { 139, 116 }, { 142, 118 },\n+\t{ 145, 109 }, { 147, 72 }, { 149, 111 }, { 154, 122 }, { 157, 119 },\n+\t{ 159, 120 }, { 161, 121 }, { 164, 123 }, { 165, 124 }, { 167, 125 },\n+\t{ 170, 126 }, { 171, 73 }, { 172, 127 }, { 173, 128 }, { 174, 129 },\n+\t{ 175, 130 }, { 176, 131 }, { 177, 132 }, { 179, 133 }, { 182, 135 },\n+\t{ 184, 136 },\n+};\n+\n+static const struct msm_pinctrl_soc_data eliza_tlmm = {\n+\t.pins = eliza_pins,\n+\t.npins = ARRAY_SIZE(eliza_pins),\n+\t.functions = eliza_functions,\n+\t.nfunctions = ARRAY_SIZE(eliza_functions),\n+\t.groups = eliza_groups,\n+\t.ngroups = ARRAY_SIZE(eliza_groups),\n+\t.ngpios = 186,\n+\t.wakeirq_map = eliza_pdc_map,\n+\t.nwakeirq_map = ARRAY_SIZE(eliza_pdc_map),\n+\t.egpio_func = 11,\n+};\n+\n+static int eliza_tlmm_probe(struct platform_device *pdev)\n+{\n+\treturn msm_pinctrl_probe(pdev, &eliza_tlmm);\n+}\n+\n+static const struct of_device_id eliza_tlmm_of_match[] = {\n+\t{ .compatible = \"qcom,eliza-tlmm\", },\n+\t{},\n+};\n+\n+static struct platform_driver eliza_tlmm_driver = {\n+\t.driver = {\n+\t\t.name = \"eliza-tlmm\",\n+\t\t.of_match_table = eliza_tlmm_of_match,\n+\t},\n+\t.probe = eliza_tlmm_probe,\n+};\n+\n+static int __init eliza_tlmm_init(void)\n+{\n+\treturn platform_driver_register(&eliza_tlmm_driver);\n+}\n+arch_initcall(eliza_tlmm_init);\n+\n+static void __exit eliza_tlmm_exit(void)\n+{\n+\tplatform_driver_unregister(&eliza_tlmm_driver);\n+}\n+module_exit(eliza_tlmm_exit);\n+\n+MODULE_DESCRIPTION(\"QTI Eliza TLMM driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match);\n", "prefixes": [ "v3", "2/2" ] }