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GET /api/patches/2196787/?format=api
{ "id": 2196787, "url": "http://patchwork.ozlabs.org/api/patches/2196787/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260216105547.13457-3-devendra.verma@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216105547.13457-3-devendra.verma@amd.com>", "list_archive_url": null, "date": "2026-02-16T10:55:46", "name": "[RESEND,v10,2/2] dmaengine: dw-edma: Add non-LL mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "eb300981c6882268880a6c22280a6e730418706b", "submitter": { "id": 91622, "url": "http://patchwork.ozlabs.org/api/people/91622/?format=api", "name": "Devendra K Verma", "email": "devendra.verma@amd.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260216105547.13457-3-devendra.verma@amd.com/mbox/", "series": [ { "id": 492293, "url": "http://patchwork.ozlabs.org/api/series/492293/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492293", "date": "2026-02-16T10:55:44", "name": "Add AMD MDB Endpoint and non-LL mode Support", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/492293/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196787/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196787/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47340-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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(p=quarantine sp=quarantine pct=100) action=none header.from=amd.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=TAHifbdgUf11x7ADrBrBtfxXXcDrXcJ2MCbbaRQNO/g=;\n b=1pzYMcIvyMQJixWAhqYzR22Tu/kJjAYj+FhHAV5wEFUAHbKMxj5VOo7o4TrPk057P/xJj0j7wMFwWC2Gn2VzhokppqlE37ngIIOIqNzyS1ysrz9LcPhWbv5P9++ctVrcPxqjItdSz6PcGZQWq4x5vwr02Rq7S5ZYB4oTxuTLmPo=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C", "From": "Devendra K Verma <devendra.verma@amd.com>", "To": "<bhelgaas@google.com>, <mani@kernel.org>, <vkoul@kernel.org>", "CC": "<dmaengine@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <michal.simek@amd.com>,\n\t<Devendra.Verma@amd.com>", "Subject": "[PATCH RESEND v10 2/2] dmaengine: dw-edma: Add non-LL mode", "Date": "Mon, 16 Feb 2026 16:25:46 +0530", "Message-ID": "<20260216105547.13457-3-devendra.verma@amd.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260216105547.13457-1-devendra.verma@amd.com>", "References": "<20260216105547.13457-1-devendra.verma@amd.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": 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"X-Forefront-Antispam-Report": "\n\tCIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tzYbINgRLr3nSQAnhGKcjkv3205EZDDhdn+mmKF1IDIXNaK4fopkPK3cW7vjCm3MOO3UWSovwhsLXPT0/8CX/uz75WezqxeNj8laSiOiV/HrArWQGQ23HJ9G4+S60Hf7IZyTF6nfIIerqRYTKVsidmpwk4RoQ11bRLmLaq1gornl6CnpLbSvbRPP+yhU5ob3M8S1RwFFRldv+UlHOOuVu39V2ryqP4HZW/x0Oo0UzZXGc7d+glGnHewSaiZJ+DAD+eZH+tr3xL2Aftb5LUfQIa5X0L1OeDDUr2w5pca4v/TWG3obV8cf2qtpxzu9aLyVhBCf85ipJvsGVXWEKUvZEZgYkZR5WZyHk4uGaHcXycaJKOsG1kUcimE1CVDShJLNKl4zlqYLSDvN9BULFEZS0F6CWxMiIE8okGNoyKLzdHfvYNFByCE6oAhjUHRVdfuOU", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Feb 2026 10:55:55.6979\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 74849087-365b-412c-edc4-08de6d49f5d1", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBN2PEPF00004FBC.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB7469" }, "content": "AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.\nThe current code does not have the mechanisms to enable the\nDMA transactions using the non-LL mode. The following two cases\nare added with this patch:\n- For the AMD (Xilinx) only, when a valid physical base address of\n the device side DDR is not configured, then the IP can still be\n used in non-LL mode. For all the channels DMA transactions will\n be using the non-LL mode only. This, the default non-LL mode,\n is not applicable for Synopsys IP with the current code addition.\n\n- If the default mode is LL-mode, for both AMD (Xilinx) and Synosys,\n and if user wants to use non-LL mode then user can do so via\n configuring the peripheral_config param of dma_slave_config.\n\nSigned-off-by: Devendra K Verma <devendra.verma@amd.com>\n---\nChanges in v10\n Added the peripheral_config check only for HDMA IP in\n dw_edma_device_config().\n Replaced the loop with single entry retrieval for non-LL\n mode.\n Addressed review comments and handled the burst allocation\n by defining 'bursts_max' as per suggestions.\n\nChanges in v9\n Fixed compilation errors related to macro name mismatch.\n\nChanges in v8\n Cosmetic change related to comment and code.\n\nChanges in v7\n No change\n\nChanges in v6\n Gave definition to bits used for channel configuration.\n Removed the comment related to doorbell.\n\nChanges in v5\n Variable name 'nollp' changed to 'non_ll'.\n In the dw_edma_device_config() WARN_ON replaced with dev_err().\n Comments follow the 80-column guideline.\n\nChanges in v4\n No change\n\nChanges in v3\n No change\n\nChanges in v2\n Reverted the function return type to u64 for\n dw_edma_get_phys_addr().\n\nChanges in v1\n Changed the function return type for dw_edma_get_phys_addr().\n Corrected the typo raised in review.\n---\n drivers/dma/dw-edma/dw-edma-core.c | 35 ++++++++++++++-\n drivers/dma/dw-edma/dw-edma-core.h | 1 +\n drivers/dma/dw-edma/dw-edma-pcie.c | 44 ++++++++++++------\n drivers/dma/dw-edma/dw-hdma-v0-core.c | 65 ++++++++++++++++++++++++++-\n drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 +\n include/linux/dma/edma.h | 1 +\n 6 files changed, 132 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c\nindex b43255f914f3..ef3d79a9f88d 100644\n--- a/drivers/dma/dw-edma/dw-edma-core.c\n+++ b/drivers/dma/dw-edma/dw-edma-core.c\n@@ -223,6 +223,31 @@ static int dw_edma_device_config(struct dma_chan *dchan,\n \t\t\t\t struct dma_slave_config *config)\n {\n \tstruct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);\n+\tint non_ll = 0;\n+\n+\tchan->non_ll = false;\n+\tif (chan->dw->chip->mf == EDMA_MF_HDMA_NATIVE) {\n+\t\tif (config->peripheral_config &&\n+\t\t config->peripheral_size != sizeof(int)) {\n+\t\t\tdev_err(dchan->device->dev,\n+\t\t\t\t\"config param peripheral size mismatch\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\t/*\n+\t\t * When there is no valid LLP base address available then the\n+\t\t * default DMA ops will use the non-LL mode.\n+\t\t *\n+\t\t * Cases where LL mode is enabled and client wants to use the\n+\t\t * non-LL mode then also client can do so via providing the\n+\t\t * peripheral_config param.\n+\t\t */\n+\t\tif (config->peripheral_config)\n+\t\t\tnon_ll = *(int *)config->peripheral_config;\n+\n+\t\tif (chan->dw->chip->non_ll || (!chan->dw->chip->non_ll && non_ll))\n+\t\t\tchan->non_ll = true;\n+\t}\n \n \tmemcpy(&chan->config, config, sizeof(*config));\n \tchan->configured = true;\n@@ -358,6 +383,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer)\n \tstruct dw_edma_desc *desc;\n \tu64 src_addr, dst_addr;\n \tsize_t fsz = 0;\n+\tu32 bursts_max;\n \tu32 cnt = 0;\n \tint i;\n \n@@ -415,6 +441,13 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer)\n \t\treturn NULL;\n \t}\n \n+\t/*\n+\t * For non-LL mode, only a single burst can be handled\n+\t * in a single chunk unlike LL mode where multiple bursts\n+\t * can be configured in a single chunk.\n+\t */\n+\tbursts_max = chan->non_ll ? 1 : chan->ll_max;\n+\n \tdesc = dw_edma_alloc_desc(chan);\n \tif (unlikely(!desc))\n \t\tgoto err_alloc;\n@@ -450,7 +483,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer)\n \t\tif (xfer->type == EDMA_XFER_SCATTER_GATHER && !sg)\n \t\t\tbreak;\n \n-\t\tif (chunk->bursts_alloc == chan->ll_max) {\n+\t\tif (chunk->bursts_alloc == bursts_max) {\n \t\t\tchunk = dw_edma_alloc_chunk(desc);\n \t\t\tif (unlikely(!chunk))\n \t\t\t\tgoto err_alloc;\ndiff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h\nindex 71894b9e0b15..c8e3d196a549 100644\n--- a/drivers/dma/dw-edma/dw-edma-core.h\n+++ b/drivers/dma/dw-edma/dw-edma-core.h\n@@ -86,6 +86,7 @@ struct dw_edma_chan {\n \tu8\t\t\t\tconfigured;\n \n \tstruct dma_slave_config\t\tconfig;\n+\tbool\t\t\t\tnon_ll;\n };\n \n struct dw_edma_irq {\ndiff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c\nindex 3aefc48f8e0a..94621b0f87df 100644\n--- a/drivers/dma/dw-edma/dw-edma-pcie.c\n+++ b/drivers/dma/dw-edma/dw-edma-pcie.c\n@@ -295,6 +295,15 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev,\n \tpdata->devmem_phys_off = off;\n }\n \n+static u64 dw_edma_get_phys_addr(struct pci_dev *pdev,\n+\t\t\t\t struct dw_edma_pcie_data *pdata,\n+\t\t\t\t enum pci_barno bar)\n+{\n+\tif (pdev->vendor == PCI_VENDOR_ID_XILINX)\n+\t\treturn pdata->devmem_phys_off;\n+\treturn pci_bus_address(pdev, bar);\n+}\n+\n static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \t\t\t const struct pci_device_id *pid)\n {\n@@ -304,6 +313,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \tstruct dw_edma_chip *chip;\n \tint err, nr_irqs;\n \tint i, mask;\n+\tbool non_ll = false;\n \n \tvsec_data = kmalloc(sizeof(*vsec_data), GFP_KERNEL);\n \tif (!vsec_data)\n@@ -329,21 +339,24 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \n \t\t/*\n \t\t * There is no valid address found for the LL memory\n-\t\t * space on the device side.\n+\t\t * space on the device side. In the absence of LL base\n+\t\t * address use the non-LL mode or simple mode supported by\n+\t\t * the HDMA IP.\n \t\t */\n \t\tif (vsec_data->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR)\n-\t\t\treturn -ENOMEM;\n+\t\t\tnon_ll = true;\n \n \t\t/*\n \t\t * Configure the channel LL and data blocks if number of\n \t\t * channels enabled in VSEC capability are more than the\n \t\t * channels configured in xilinx_mdb_data.\n \t\t */\n-\t\tdw_edma_set_chan_region_offset(vsec_data, BAR_2, 0,\n-\t\t\t\t\t DW_PCIE_XILINX_MDB_LL_OFF_GAP,\n-\t\t\t\t\t DW_PCIE_XILINX_MDB_LL_SIZE,\n-\t\t\t\t\t DW_PCIE_XILINX_MDB_DT_OFF_GAP,\n-\t\t\t\t\t DW_PCIE_XILINX_MDB_DT_SIZE);\n+\t\tif (!non_ll)\n+\t\t\tdw_edma_set_chan_region_offset(vsec_data, BAR_2, 0,\n+\t\t\t\t\t\t DW_PCIE_XILINX_MDB_LL_OFF_GAP,\n+\t\t\t\t\t\t DW_PCIE_XILINX_MDB_LL_SIZE,\n+\t\t\t\t\t\t DW_PCIE_XILINX_MDB_DT_OFF_GAP,\n+\t\t\t\t\t\t DW_PCIE_XILINX_MDB_DT_SIZE);\n \t}\n \n \t/* Mapping PCI BAR regions */\n@@ -391,6 +404,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \tchip->mf = vsec_data->mf;\n \tchip->nr_irqs = nr_irqs;\n \tchip->ops = &dw_edma_pcie_plat_ops;\n+\tchip->non_ll = non_ll;\n \n \tchip->ll_wr_cnt = vsec_data->wr_ch_cnt;\n \tchip->ll_rd_cnt = vsec_data->rd_ch_cnt;\n@@ -399,7 +413,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \tif (!chip->reg_base)\n \t\treturn -ENOMEM;\n \n-\tfor (i = 0; i < chip->ll_wr_cnt; i++) {\n+\tfor (i = 0; i < chip->ll_wr_cnt && !non_ll; i++) {\n \t\tstruct dw_edma_region *ll_region = &chip->ll_region_wr[i];\n \t\tstruct dw_edma_region *dt_region = &chip->dt_region_wr[i];\n \t\tstruct dw_edma_block *ll_block = &vsec_data->ll_wr[i];\n@@ -410,7 +424,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \t\t\treturn -ENOMEM;\n \n \t\tll_region->vaddr.io += ll_block->off;\n-\t\tll_region->paddr = pci_bus_address(pdev, ll_block->bar);\n+\t\tll_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data,\n+\t\t\t\t\t\t\t ll_block->bar);\n \t\tll_region->paddr += ll_block->off;\n \t\tll_region->sz = ll_block->sz;\n \n@@ -419,12 +434,13 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \t\t\treturn -ENOMEM;\n \n \t\tdt_region->vaddr.io += dt_block->off;\n-\t\tdt_region->paddr = pci_bus_address(pdev, dt_block->bar);\n+\t\tdt_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data,\n+\t\t\t\t\t\t\t dt_block->bar);\n \t\tdt_region->paddr += dt_block->off;\n \t\tdt_region->sz = dt_block->sz;\n \t}\n \n-\tfor (i = 0; i < chip->ll_rd_cnt; i++) {\n+\tfor (i = 0; i < chip->ll_rd_cnt && !non_ll; i++) {\n \t\tstruct dw_edma_region *ll_region = &chip->ll_region_rd[i];\n \t\tstruct dw_edma_region *dt_region = &chip->dt_region_rd[i];\n \t\tstruct dw_edma_block *ll_block = &vsec_data->ll_rd[i];\n@@ -435,7 +451,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \t\t\treturn -ENOMEM;\n \n \t\tll_region->vaddr.io += ll_block->off;\n-\t\tll_region->paddr = pci_bus_address(pdev, ll_block->bar);\n+\t\tll_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data,\n+\t\t\t\t\t\t\t ll_block->bar);\n \t\tll_region->paddr += ll_block->off;\n \t\tll_region->sz = ll_block->sz;\n \n@@ -444,7 +461,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \t\t\treturn -ENOMEM;\n \n \t\tdt_region->vaddr.io += dt_block->off;\n-\t\tdt_region->paddr = pci_bus_address(pdev, dt_block->bar);\n+\t\tdt_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data,\n+\t\t\t\t\t\t\t dt_block->bar);\n \t\tdt_region->paddr += dt_block->off;\n \t\tdt_region->sz = dt_block->sz;\n \t}\ndiff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c\nindex e3f8db4fe909..a1b04fec6310 100644\n--- a/drivers/dma/dw-edma/dw-hdma-v0-core.c\n+++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c\n@@ -225,7 +225,7 @@ static void dw_hdma_v0_sync_ll_data(struct dw_edma_chunk *chunk)\n \t\treadl(chunk->ll_region.vaddr.io);\n }\n \n-static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first)\n+static void dw_hdma_v0_core_ll_start(struct dw_edma_chunk *chunk, bool first)\n {\n \tstruct dw_edma_chan *chan = chunk->chan;\n \tstruct dw_edma *dw = chan->dw;\n@@ -263,6 +263,69 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first)\n \tSET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START);\n }\n \n+static void dw_hdma_v0_core_non_ll_start(struct dw_edma_chunk *chunk)\n+{\n+\tstruct dw_edma_chan *chan = chunk->chan;\n+\tstruct dw_edma *dw = chan->dw;\n+\tstruct dw_edma_burst *child;\n+\tu32 val;\n+\n+\tchild = list_first_entry_or_null(&chunk->burst->list,\n+\t\t\t\t\t struct dw_edma_burst, list);\n+\tif (!child)\n+\t\treturn;\n+\n+\tSET_CH_32(dw, chan->dir, chan->id, ch_en, HDMA_V0_CH_EN);\n+\n+\t/* Source address */\n+\tSET_CH_32(dw, chan->dir, chan->id, sar.lsb,\n+\t\t lower_32_bits(child->sar));\n+\tSET_CH_32(dw, chan->dir, chan->id, sar.msb,\n+\t\t upper_32_bits(child->sar));\n+\n+\t/* Destination address */\n+\tSET_CH_32(dw, chan->dir, chan->id, dar.lsb,\n+\t\t lower_32_bits(child->dar));\n+\tSET_CH_32(dw, chan->dir, chan->id, dar.msb,\n+\t\t upper_32_bits(child->dar));\n+\n+\t/* Transfer size */\n+\tSET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz);\n+\n+\t/* Interrupt setup */\n+\tval = GET_CH_32(dw, chan->dir, chan->id, int_setup) |\n+\t\t\tHDMA_V0_STOP_INT_MASK |\n+\t\t\tHDMA_V0_ABORT_INT_MASK |\n+\t\t\tHDMA_V0_LOCAL_STOP_INT_EN |\n+\t\t\tHDMA_V0_LOCAL_ABORT_INT_EN;\n+\n+\tif (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) {\n+\t\tval |= HDMA_V0_REMOTE_STOP_INT_EN |\n+\t\t HDMA_V0_REMOTE_ABORT_INT_EN;\n+\t}\n+\n+\tSET_CH_32(dw, chan->dir, chan->id, int_setup, val);\n+\n+\t/* Channel control setup */\n+\tval = GET_CH_32(dw, chan->dir, chan->id, control1);\n+\tval &= ~HDMA_V0_LINKLIST_EN;\n+\tSET_CH_32(dw, chan->dir, chan->id, control1, val);\n+\n+\tSET_CH_32(dw, chan->dir, chan->id, doorbell,\n+\t\t HDMA_V0_DOORBELL_START);\n+\t\n+}\n+\n+static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first)\n+{\n+\tstruct dw_edma_chan *chan = chunk->chan;\n+\n+\tif (chan->non_ll)\n+\t\tdw_hdma_v0_core_non_ll_start(chunk);\n+\telse\n+\t\tdw_hdma_v0_core_ll_start(chunk, first);\n+}\n+\n static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan)\n {\n \tstruct dw_edma *dw = chan->dw;\ndiff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h\nindex eab5fd7177e5..7759ba9b4850 100644\n--- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h\n+++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h\n@@ -12,6 +12,7 @@\n #include <linux/dmaengine.h>\n \n #define HDMA_V0_MAX_NR_CH\t\t\t8\n+#define HDMA_V0_CH_EN\t\t\t\tBIT(0)\n #define HDMA_V0_LOCAL_ABORT_INT_EN\t\tBIT(6)\n #define HDMA_V0_REMOTE_ABORT_INT_EN\t\tBIT(5)\n #define HDMA_V0_LOCAL_STOP_INT_EN\t\tBIT(4)\ndiff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h\nindex 3080747689f6..78ce31b049ae 100644\n--- a/include/linux/dma/edma.h\n+++ b/include/linux/dma/edma.h\n@@ -99,6 +99,7 @@ struct dw_edma_chip {\n \tenum dw_edma_map_format\tmf;\n \n \tstruct dw_edma\t\t*dw;\n+\tbool\t\t\tnon_ll;\n };\n \n /* Export to the platform drivers */\n", "prefixes": [ "RESEND", "v10", "2/2" ] }