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GET /api/patches/2196786/?format=api
{ "id": 2196786, "url": "http://patchwork.ozlabs.org/api/patches/2196786/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260216105547.13457-2-devendra.verma@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216105547.13457-2-devendra.verma@amd.com>", "list_archive_url": null, "date": "2026-02-16T10:55:45", "name": "[RESEND,v10,1/2] dmaengine: dw-edma: Add AMD MDB Endpoint Support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "65b1973734798a6d7443fe1d83850b6fe3d7373f", "submitter": { "id": 91622, "url": "http://patchwork.ozlabs.org/api/people/91622/?format=api", "name": "Devendra K Verma", "email": "devendra.verma@amd.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260216105547.13457-2-devendra.verma@amd.com/mbox/", "series": [ { "id": 492293, "url": "http://patchwork.ozlabs.org/api/series/492293/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492293", "date": "2026-02-16T10:55:44", "name": "Add AMD MDB Endpoint and non-LL mode Support", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/492293/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196786/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196786/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47339-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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permitted sender hosts)" ], "From": "Devendra K Verma <devendra.verma@amd.com>", "To": "<bhelgaas@google.com>, <mani@kernel.org>, <vkoul@kernel.org>", "CC": "<dmaengine@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <michal.simek@amd.com>,\n\t<Devendra.Verma@amd.com>", "Subject": "[PATCH RESEND v10 1/2] dmaengine: dw-edma: Add AMD MDB Endpoint\n Support", "Date": "Mon, 16 Feb 2026 16:25:45 +0530", "Message-ID": "<20260216105547.13457-2-devendra.verma@amd.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260216105547.13457-1-devendra.verma@amd.com>", "References": "<20260216105547.13457-1-devendra.verma@amd.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": 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"X-Forefront-Antispam-Report": "\n\tCIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tliw7jkvmU8ZnYSEfSqYxg+3eAQSj2VZ+4MviRWrhMzogO5JJKvcWuRJYhKGtFio+gS7eXvT2dWgdSHjoTYYyg+IWVhgqQS0thDfH1RHMigMPdxhteywjUb51rVQViAHg3YhJIOEaUmyyJuC3/mt3Jr0evr5W63epr1wcRBvrBiMVcwMe3U+3C0/hVDivPD9D/TvKBUO2ZUsc6RYzDeLRL8bKagXIIY5hCwss8PPmLCn5UpmmbMfcZAHRspyHjhxHhvhkudbw2AdgfFb0uiy+c8dQIn1oUxG4+s7rGDmf8qHNCARK07N4SPIrfhzJwfKlVaW4ede8momFhQLrM3jBu5bLiW572IDO6zTSdEiMCCduEr538U0wyr9MqYwy80wLYr+mngxH3ZaV8RcEolxPcJtP8Ya5ZogaJWPYG+PePLeDmw2i13zthJyHAhk7UHuT", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Feb 2026 10:55:53.9374\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cc96b723-17e4-457e-2678-08de6d49f4d3", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCO1PEPF000044F9.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6090" }, "content": "AMD MDB PCIe endpoint support. For AMD specific support\nadded the following\n - AMD supported PCIe Device IDs and Vendor ID (Xilinx).\n - AMD MDB specific driver data\n - AMD MDB specific VSEC capability to retrieve the device DDR\n base address.\n\nSigned-off-by: Devendra K Verma <devendra.verma@amd.com>\n---\nChanges in v10:\nFor Xilinx VSEC function kept only HDMA map format as\nXilinx only supports HDMA.\n\nChanges in v9:\nMoved Xilinx specific VSEC capability functions under\nthe vendor ID condition.\n\nChanges in v8:\nChanged the contant names to includer product vendor.\nMoved the vendor specific code to vendor specific functions.\n\nChanges in v7:\nIntroduced vendor specific functions to retrieve the\nvsec data.\n\nChanges in v6:\nIncluded \"sizes.h\" header and used the appropriate\ndefinitions instead of constants.\n\nChanges in v5:\nAdded the definitions for Xilinx specific VSEC header id,\nrevision, and register offsets.\nCorrected the error type when no physical offset found for\ndevice side memory.\nCorrected the order of variables.\n\nChanges in v4:\nConfigured 8 read and 8 write channels for Xilinx vendor\nAdded checks to validate vendor ID for vendor\nspecific vsec id.\nAdded Xilinx specific vendor id for vsec specific to Xilinx\nAdded the LL and data region offsets, size as input params to\nfunction dw_edma_set_chan_region_offset().\nMoved the LL and data region offsets assignment to function\nfor Xilinx specific case.\nCorrected comments.\n\nChanges in v3:\nCorrected a typo when assigning AMD (Xilinx) vsec id macro\nand condition check.\n\nChanges in v2:\nReverted the devmem_phys_off type to u64.\nRenamed the function appropriately to suit the\nfunctionality for setting the LL & data region offsets.\n\nChanges in v1:\nRemoved the pci device id from pci_ids.h file.\nAdded the vendor id macro as per the suggested method.\nChanged the type of the newly added devmem_phys_off variable.\nAdded to logic to assign offsets for LL and data region blocks\nin case more number of channels are enabled than given in\namd_mdb_data struct.\n---\n drivers/dma/dw-edma/dw-edma-pcie.c | 190 ++++++++++++++++++++++++++---\n 1 file changed, 176 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c\nindex 3371e0a76d3c..3aefc48f8e0a 100644\n--- a/drivers/dma/dw-edma/dw-edma-pcie.c\n+++ b/drivers/dma/dw-edma/dw-edma-pcie.c\n@@ -14,14 +14,35 @@\n #include <linux/pci-epf.h>\n #include <linux/msi.h>\n #include <linux/bitfield.h>\n+#include <linux/sizes.h>\n \n #include \"dw-edma-core.h\"\n \n-#define DW_PCIE_VSEC_DMA_ID\t\t\t0x6\n-#define DW_PCIE_VSEC_DMA_BAR\t\t\tGENMASK(10, 8)\n-#define DW_PCIE_VSEC_DMA_MAP\t\t\tGENMASK(2, 0)\n-#define DW_PCIE_VSEC_DMA_WR_CH\t\t\tGENMASK(9, 0)\n-#define DW_PCIE_VSEC_DMA_RD_CH\t\t\tGENMASK(25, 16)\n+/* Synopsys */\n+#define DW_PCIE_SYNOPSYS_VSEC_DMA_ID\t\t0x6\n+#define DW_PCIE_SYNOPSYS_VSEC_DMA_BAR\t\tGENMASK(10, 8)\n+#define DW_PCIE_SYNOPSYS_VSEC_DMA_MAP\t\tGENMASK(2, 0)\n+#define DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH\t\tGENMASK(9, 0)\n+#define DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH\t\tGENMASK(25, 16)\n+\n+/* AMD MDB (Xilinx) specific defines */\n+#define PCI_DEVICE_ID_XILINX_B054\t\t0xb054\n+\n+#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID\t\t0x6\n+#define DW_PCIE_XILINX_MDB_VSEC_ID\t\t0x20\n+#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR\t\tGENMASK(10, 8)\n+#define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP\t\tGENMASK(2, 0)\n+#define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH\tGENMASK(9, 0)\n+#define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH\tGENMASK(25, 16)\n+\n+#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH\t0xc\n+#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW\t0x8\n+#define DW_PCIE_XILINX_MDB_INVALID_ADDR\t\t(~0ULL)\n+\n+#define DW_PCIE_XILINX_MDB_LL_OFF_GAP\t\t0x200000\n+#define DW_PCIE_XILINX_MDB_LL_SIZE\t\t0x800\n+#define DW_PCIE_XILINX_MDB_DT_OFF_GAP\t\t0x100000\n+#define DW_PCIE_XILINX_MDB_DT_SIZE\t\t0x800\n \n #define DW_BLOCK(a, b, c) \\\n \t{ \\\n@@ -50,6 +71,7 @@ struct dw_edma_pcie_data {\n \tu8\t\t\t\tirqs;\n \tu16\t\t\t\twr_ch_cnt;\n \tu16\t\t\t\trd_ch_cnt;\n+\tu64\t\t\t\tdevmem_phys_off;\n };\n \n static const struct dw_edma_pcie_data snps_edda_data = {\n@@ -90,6 +112,64 @@ static const struct dw_edma_pcie_data snps_edda_data = {\n \t.rd_ch_cnt\t\t\t= 2,\n };\n \n+static const struct dw_edma_pcie_data xilinx_mdb_data = {\n+\t/* MDB registers location */\n+\t.rg.bar\t\t\t\t= BAR_0,\n+\t.rg.off\t\t\t\t= SZ_4K,\t/* 4 Kbytes */\n+\t.rg.sz\t\t\t\t= SZ_8K,\t/* 8 Kbytes */\n+\n+\t/* Other */\n+\t.mf\t\t\t\t= EDMA_MF_HDMA_NATIVE,\n+\t.irqs\t\t\t\t= 1,\n+\t.wr_ch_cnt\t\t\t= 8,\n+\t.rd_ch_cnt\t\t\t= 8,\n+};\n+\n+static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata,\n+\t\t\t\t\t enum pci_barno bar, off_t start_off,\n+\t\t\t\t\t off_t ll_off_gap, size_t ll_size,\n+\t\t\t\t\t off_t dt_off_gap, size_t dt_size)\n+{\n+\tu16 wr_ch = pdata->wr_ch_cnt;\n+\tu16 rd_ch = pdata->rd_ch_cnt;\n+\toff_t off;\n+\tu16 i;\n+\n+\toff = start_off;\n+\n+\t/* Write channel LL region */\n+\tfor (i = 0; i < wr_ch; i++) {\n+\t\tpdata->ll_wr[i].bar = bar;\n+\t\tpdata->ll_wr[i].off = off;\n+\t\tpdata->ll_wr[i].sz = ll_size;\n+\t\toff += ll_off_gap;\n+\t}\n+\n+\t/* Read channel LL region */\n+\tfor (i = 0; i < rd_ch; i++) {\n+\t\tpdata->ll_rd[i].bar = bar;\n+\t\tpdata->ll_rd[i].off = off;\n+\t\tpdata->ll_rd[i].sz = ll_size;\n+\t\toff += ll_off_gap;\n+\t}\n+\n+\t/* Write channel data region */\n+\tfor (i = 0; i < wr_ch; i++) {\n+\t\tpdata->dt_wr[i].bar = bar;\n+\t\tpdata->dt_wr[i].off = off;\n+\t\tpdata->dt_wr[i].sz = dt_size;\n+\t\toff += dt_off_gap;\n+\t}\n+\n+\t/* Read channel data region */\n+\tfor (i = 0; i < rd_ch; i++) {\n+\t\tpdata->dt_rd[i].bar = bar;\n+\t\tpdata->dt_rd[i].off = off;\n+\t\tpdata->dt_rd[i].sz = dt_size;\n+\t\toff += dt_off_gap;\n+\t}\n+}\n+\n static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr)\n {\n \treturn pci_irq_vector(to_pci_dev(dev), nr);\n@@ -114,15 +194,15 @@ static const struct dw_edma_plat_ops dw_edma_pcie_plat_ops = {\n \t.pci_address = dw_edma_pcie_address,\n };\n \n-static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev,\n-\t\t\t\t\t struct dw_edma_pcie_data *pdata)\n+static void dw_edma_pcie_get_synopsys_dma_data(struct pci_dev *pdev,\n+\t\t\t\t\t struct dw_edma_pcie_data *pdata)\n {\n \tu32 val, map;\n \tu16 vsec;\n \tu64 off;\n \n \tvsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS,\n-\t\t\t\t\tDW_PCIE_VSEC_DMA_ID);\n+\t\t\t\t\tDW_PCIE_SYNOPSYS_VSEC_DMA_ID);\n \tif (!vsec)\n \t\treturn;\n \n@@ -131,9 +211,9 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev,\n \t PCI_VNDR_HEADER_LEN(val) != 0x18)\n \t\treturn;\n \n-\tpci_dbg(pdev, \"Detected PCIe Vendor-Specific Extended Capability DMA\\n\");\n+\tpci_dbg(pdev, \"Detected Synopsys PCIe Vendor-Specific Extended Capability DMA\\n\");\n \tpci_read_config_dword(pdev, vsec + 0x8, &val);\n-\tmap = FIELD_GET(DW_PCIE_VSEC_DMA_MAP, val);\n+\tmap = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_MAP, val);\n \tif (map != EDMA_MF_EDMA_LEGACY &&\n \t map != EDMA_MF_EDMA_UNROLL &&\n \t map != EDMA_MF_HDMA_COMPAT &&\n@@ -141,13 +221,13 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev,\n \t\treturn;\n \n \tpdata->mf = map;\n-\tpdata->rg.bar = FIELD_GET(DW_PCIE_VSEC_DMA_BAR, val);\n+\tpdata->rg.bar = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_BAR, val);\n \n \tpci_read_config_dword(pdev, vsec + 0xc, &val);\n \tpdata->wr_ch_cnt = min_t(u16, pdata->wr_ch_cnt,\n-\t\t\t\t FIELD_GET(DW_PCIE_VSEC_DMA_WR_CH, val));\n+\t\t\t\t FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH, val));\n \tpdata->rd_ch_cnt = min_t(u16, pdata->rd_ch_cnt,\n-\t\t\t\t FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val));\n+\t\t\t\t FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH, val));\n \n \tpci_read_config_dword(pdev, vsec + 0x14, &val);\n \toff = val;\n@@ -157,6 +237,64 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev,\n \tpdata->rg.off = off;\n }\n \n+static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev,\n+\t\t\t\t\t struct dw_edma_pcie_data *pdata)\n+{\n+\tu32 val, map;\n+\tu16 vsec;\n+\tu64 off;\n+\n+\tpdata->devmem_phys_off = DW_PCIE_XILINX_MDB_INVALID_ADDR;\n+\n+\tvsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX,\n+\t\t\t\t\tDW_PCIE_XILINX_MDB_VSEC_DMA_ID);\n+\tif (!vsec)\n+\t\treturn;\n+\n+\tpci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val);\n+\tif (PCI_VNDR_HEADER_REV(val) != 0x00 ||\n+\t PCI_VNDR_HEADER_LEN(val) != 0x18)\n+\t\treturn;\n+\n+\tpci_dbg(pdev, \"Detected Xilinx PCIe Vendor-Specific Extended Capability DMA\\n\");\n+\tpci_read_config_dword(pdev, vsec + 0x8, &val);\n+\tmap = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_MAP, val);\n+\tif (map != EDMA_MF_HDMA_NATIVE)\n+\t\treturn;\n+\n+\tpdata->mf = map;\n+\tpdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val);\n+\n+\tpci_read_config_dword(pdev, vsec + 0xc, &val);\n+\tpdata->wr_ch_cnt = min_t(u16, pdata->wr_ch_cnt,\n+\t\t\t\t FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val));\n+\tpdata->rd_ch_cnt = min_t(u16, pdata->rd_ch_cnt,\n+\t\t\t\t FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH, val));\n+\n+\tpci_read_config_dword(pdev, vsec + 0x14, &val);\n+\toff = val;\n+\tpci_read_config_dword(pdev, vsec + 0x10, &val);\n+\toff <<= 32;\n+\toff |= val;\n+\tpdata->rg.off = off;\n+\n+\tvsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX,\n+\t\t\t\t\tDW_PCIE_XILINX_MDB_VSEC_ID);\n+\tif (!vsec)\n+\t\treturn;\n+\n+\tpci_read_config_dword(pdev,\n+\t\t\t vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH,\n+\t\t\t &val);\n+\toff = val;\n+\tpci_read_config_dword(pdev,\n+\t\t\t vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW,\n+\t\t\t &val);\n+\toff <<= 32;\n+\toff |= val;\n+\tpdata->devmem_phys_off = off;\n+}\n+\n static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \t\t\t const struct pci_device_id *pid)\n {\n@@ -184,7 +322,29 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,\n \t * Tries to find if exists a PCIe Vendor-Specific Extended Capability\n \t * for the DMA, if one exists, then reconfigures it.\n \t */\n-\tdw_edma_pcie_get_vsec_dma_data(pdev, vsec_data);\n+\tdw_edma_pcie_get_synopsys_dma_data(pdev, vsec_data);\n+\n+\tif (pdev->vendor == PCI_VENDOR_ID_XILINX) {\n+\t\tdw_edma_pcie_get_xilinx_dma_data(pdev, vsec_data);\n+\n+\t\t/*\n+\t\t * There is no valid address found for the LL memory\n+\t\t * space on the device side.\n+\t\t */\n+\t\tif (vsec_data->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR)\n+\t\t\treturn -ENOMEM;\n+\n+\t\t/*\n+\t\t * Configure the channel LL and data blocks if number of\n+\t\t * channels enabled in VSEC capability are more than the\n+\t\t * channels configured in xilinx_mdb_data.\n+\t\t */\n+\t\tdw_edma_set_chan_region_offset(vsec_data, BAR_2, 0,\n+\t\t\t\t\t DW_PCIE_XILINX_MDB_LL_OFF_GAP,\n+\t\t\t\t\t DW_PCIE_XILINX_MDB_LL_SIZE,\n+\t\t\t\t\t DW_PCIE_XILINX_MDB_DT_OFF_GAP,\n+\t\t\t\t\t DW_PCIE_XILINX_MDB_DT_SIZE);\n+\t}\n \n \t/* Mapping PCI BAR regions */\n \tmask = BIT(vsec_data->rg.bar);\n@@ -367,6 +527,8 @@ static void dw_edma_pcie_remove(struct pci_dev *pdev)\n \n static const struct pci_device_id dw_edma_pcie_id_table[] = {\n \t{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },\n+\t{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054),\n+\t (kernel_ulong_t)&xilinx_mdb_data },\n \t{ }\n };\n MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);\n", "prefixes": [ "RESEND", "v10", "1/2" ] }