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GET /api/patches/2196754/?format=api
{ "id": 2196754, "url": "http://patchwork.ozlabs.org/api/patches/2196754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260216102858.2745657-11-s-vadapalli@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216102858.2745657-11-s-vadapalli@ti.com>", "list_archive_url": null, "date": "2026-02-16T10:28:38", "name": "[v5,10/10] docs: board: ti: j784s4_evm: Add PCIe boot documentation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "76e6d2910a953014c8e453c464d9e6fdc35d8b50", "submitter": { "id": 84157, "url": "http://patchwork.ozlabs.org/api/people/84157/?format=api", "name": "Siddharth Vadapalli", "email": "s-vadapalli@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260216102858.2745657-11-s-vadapalli@ti.com/mbox/", "series": [ { "id": 492281, "url": "http://patchwork.ozlabs.org/api/series/492281/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=492281", "date": "2026-02-16T10:28:28", "name": "Add PCIe Boot support for TI J784S4 SoC", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/492281/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196754/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196754/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=selector1 header.b=puDHSz8N;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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helo=lewvzet201.ext.ti.com; pr=C", "From": "Siddharth Vadapalli <s-vadapalli@ti.com>", "To": "<trini@konsulko.com>, <m-chawdhry@ti.com>, <c-vankar@ti.com>,\n <neil.armstrong@linaro.org>, <marek.vasut+renesas@mailbox.org>,\n <u-kumar1@ti.com>, <j-keerthy@ti.com>, <semen.protsenko@linaro.org>,\n <afd@ti.com>, <anshuld@ti.com>, <peng.fan@nxp.com>, <ahalaney@redhat.com>,\n <mkorpershoek@kernel.org>, <n-francis@ti.com>", "CC": "<u-boot@lists.denx.de>, <srk@ti.com>, <s-vadapalli@ti.com>", "Subject": "[PATCH v5 10/10] docs: board: ti: j784s4_evm: Add PCIe boot\n documentation", "Date": "Mon, 16 Feb 2026 15:58:38 +0530", "Message-ID": "<20260216102858.2745657-11-s-vadapalli@ti.com>", "X-Mailer": "git-send-email 2.51.1", "In-Reply-To": "<20260216102858.2745657-1-s-vadapalli@ti.com>", "References": "<20260216102858.2745657-1-s-vadapalli@ti.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-C2ProcessedOrg": "333ef613-75bf-4e12-a4b1-8e3623f5dcea", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH2PEPF0000013E:EE_|SJ5PPFA8FAAE4F4:EE_", "X-MS-Office365-Filtering-Correlation-Id": "496dbed7-03f7-409b-7482-08de6d461d14", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|82310400026|36860700013|376014|921020;", "X-Microsoft-Antispam-Message-Info": "\n eGbWzMbZ+uyKrGV9BwBJpFSm3Ez8mqIggBOfBww50hoe7gqvbmqwzt+KknWOmEdo7lR/yK9ye/Y+dudfZFWqoWPW6ZBVlohJrcO0erdRtOwptu8W0ofnSbJ20ZBB2+Bp/L/zYThAslWqkIu3t/JI4zlzXmqfBofIK/96EV4shV3ShgPInrJ+wDus87/GMMPMrhj2vK0AfpYAWJGS3/n+pK4UJaFBp2LFTI2B4QeyqoeloLU3LAJbzjJqSOi3qnSrUVitklcE1+seEqmkrZObJfg1cV+Qybp2Njh02HKmJdOcW0H0oriEh9IwBDruWh+zCgos1rHU8SIGWHceJadaCLnY0Hizamc63m5a610Bv3L8Zt6ZGsvWBVjdFn5Zhgi+qNknnS1AvWC2EAbXLCwoSEnrcknqy5hRNyxpYmYz9ign40aVgLfHdeqqUwqlGmUFXnCCk3njn1bqZpgCxvE8uwCITLN2jeCy1ZZ8LUTIoQBbemkRUPMUNbtefVltSHExxfThOBwK6jNNH+SCF88fbgkaYaN5SMSsHOmDReF6cVwcLIK5sX1NRXOxcFn2rKsp2Nml02ZZKIDHhwWjkQEvhZJuKt4orFrVd2DT920nujEy+STy57lS9TnRmMRLZfv+Kg8kchZbMXmSAtRftFO94P5Su1NeVXeH+ebVTMKBJEpH9bCyrssrjYgUPLX3iVvlW8unqJSYqpe96tgcKcTzFF+8013ZWkXU8BQFx0wYQx05cK5PZmVoaI073+JUMluwvT0mSQN0Gp/3yWjgeijdHj57raz1CyIVmQgeW4yj+ZDpIPb/jzWn/ixP3AN1y39YiFGQPrzTqTf63GVlZQhwBX8hr8gCyikInntrtkMputWwLOneHlAOz8vVPZFZpLqtADSih9/rDn8v9AT/BRSt1betGvNobhjq9w/vHLnPO8jhkpoQCEMPaYCCaWf7Q+j+UF0KBUmn9+1JMXXlCaMKd9cyxnJzhGu/Q2Gfd1HFuAHIfePF8D8kyHmSXGAhaDZNq+L6sDJPnn8Riq0xiRUEup/+Y5MjsAunEo1SSaA1q5RabBLGREqhOtGXkoBxmPnVsFzdD/dtL3JB5zmZNcH2RFLji2w+rzDqBbNeUJmuZ6OyztMmWZqX5KcWfV2V0um9lIo5H7oJVmhn/rZTZtgyAug3ANzYT+iRiHJN6+cFnKpglUdJhkjHYEpfcz2ftvPlPZ6zfupxZLDl+fMF4MraQF47gjvIPH7xHMk/+9CkGnQOBNkrju0oMJvXwzfomyJWG2ywO+aNWN7BsL3q+UO5oMYsDFm9NQjtIxfzV8f7w2TCuqPsCVZbk4Ygj+Z3/eEHGu/bYADPOlHX9ZwDBdK/zbtIeol1hoSgaik2BVuqRTvQEuHzMMYhMGMLpjWW7etZDAeEQbG8gXG62qg7v907c3eHxgsuefvFNBzhTLAsk9dATIGd6IK6BGYlVtVQMRH+oHSu0vKvoUameiVp3KbhBV9sJHh3OjfkYQOeLcXFxW1MYq8MO9vDjFJLpplWDh0sh6Ug0xLuPwbUJOH0NedFCABDVjSBYOFaZ1sHHG2B9qt0moTfiyHP5WMncbCP5MoKiJLZAze//E6P78l147Ozi578tWYjVNhhodoLJ5MP0CL9fbK4nbLbspxxu3jBtazEVg43srqaRCMoWzsyrBybHl9Iu9FtxFAsl9HwompkDYY=", "X-Forefront-Antispam-Report": "CIP:198.47.23.195; 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Ip=[198.47.23.195];\n Helo=[lewvzet201.ext.ti.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH2PEPF0000013E.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ5PPFA8FAAE4F4", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Hrushikesh Salunke <h-salunke@ti.com>\n\nAdd PCIe boot documentation for J784S4-EVM including boot mode switch\nsettings, hardware setup requirements, endpoint configuration details\nand step-by-step boot procedure.\n\nSigned-off-by: Hrushikesh Salunke <h-salunke@ti.com>\n[s-vadapalli@ti.com: simplified and documented the pcie_boot_util program]\nCo-developed-by: Siddharth Vadapalli <s-vadapalli@ti.com>\nSigned-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>\n---\n doc/board/ti/j784s4_evm.rst | 305 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 305 insertions(+)", "diff": "diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst\nindex d858dc7cdbb..fb767bedbf6 100644\n--- a/doc/board/ti/j784s4_evm.rst\n+++ b/doc/board/ti/j784s4_evm.rst\n@@ -299,6 +299,10 @@ http://www.ti.com/lit/zip/spruj52 under the `Boot Mode Pins` section.\n - 00000000\n - 01110000\n \n+ * - PCIe\n+ - 10001000\n+ - 01010000\n+\n For SW7 and SW11, the switch state in the \"ON\" position = 1.\n \n Boot Mode Pins for AM69-SK\n@@ -330,6 +334,307 @@ section.\n \n For SW2, the switch state in the \"ON\" position = 1.\n \n+PCIe Boot\n+---------\n+\n+The J784S4 SoC supports booting over PCIe, allowing the device to function\n+as a PCIe endpoint and receive boot loader images from a PCIe Root Complex.\n+The PCIe1 instance of PCIe is configured by Boot ROM for Endpoint Mode of\n+operation. Hence, the PCIe Connector on the EVM corresponding to PCIe1\n+should be utilized for PCIe Boot.\n+\n+Hardware Setup\n+^^^^^^^^^^^^^^\n+\n+To boot the J784S4 EVM via PCIe, the following hardware setup is required:\n+\n+1. Configure the boot mode switches on J784S4-EVM for PCIe boot:\n+\n+ .. code-block:: text\n+\n+ SW7: 01010000\n+ SW11: 10001000\n+\n+2. Connect the J784S4-EVM (endpoint) to a PCIe Root Complex (e.g., x86 host)\n+ using a PCIe cable. Both boards should be powered off before making the\n+ connection.\n+\n+Endpoint Configuration\n+^^^^^^^^^^^^^^^^^^^^^^\n+\n+The following configuration options are enabled by default in\n+``j784s4_evm_r5_defconfig`` and ``j784s4_evm_a72_defconfig``:\n+\n+- ``CONFIG_SPL_PCI_DFU_BAR_SIZE``: Size of the PCIe BAR for DFU/boot image download\n+- ``CONFIG_SPL_PCI_DFU_VENDOR_ID``: PCIe vendor ID advertised by the endpoint\n+- ``CONFIG_SPL_PCI_DFU_DEVICE_ID``: PCIe device ID advertised by the endpoint\n+- ``CONFIG_SPL_PCI_DFU_MAGIC_WORD``: Magic word written by Root Complex to signal image transfer completion\n+- ``CONFIG_SPL_PCI_DFU_BOOT_PHASE``: Current boot phase indicator for Root Complex\n+\n+By default, PCIe Root Complex mode is enabled in the device tree. For PCIe Boot,\n+build the Bootloaders with the following content added to k3-j784s4-evm-u-boot.dtsi:\n+\n+.. code-block:: devicetree\n+\n+ &serdes0 {\n+ /delete-property/ serdes0_usb_link;\n+ };\n+\n+ &serdes_refclk {\n+ bootph-all;\n+ };\n+\n+ &serdes0_pcie1_link {\n+ bootph-all;\n+ };\n+\n+ &serdes_ln_ctrl {\n+ bootph-all;\n+ };\n+\n+ &pcie1_ctrl {\n+ bootph-all;\n+ };\n+\n+ &pcie1_rc {\n+ status = \"disabled\";\n+ };\n+\n+ &cbass_main {\n+ pcie1_ep: pcie-ep@2910000 {\n+ compatible = \"ti,j784s4-pcie-ep\";\n+ reg = <0x00 0x02910000 0x00 0x1000>,\n+ <0x00 0x02917000 0x00 0x400>,\n+ <0x00 0x0d800000 0x00 0x00800000>,\n+ <0x00 0x18000000 0x00 0x08000000>;\n+ reg-names = \"intd_cfg\", \"user_cfg\", \"reg\", \"mem\";\n+ interrupt-names = \"link_state\";\n+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;\n+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;\n+ max-link-speed = <3>;\n+ num-lanes = <2>;\n+ power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;\n+ clocks = <&k3_clks 333 0>;\n+ clock-names = \"fck\";\n+ max-functions = /bits/ 8 <6>;\n+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;\n+ dma-coherent;\n+ phys = <&serdes0_pcie1_link>;\n+ phy-names = \"pcie-phy\";\n+ bootph-all;\n+ };\n+ };\n+\n+PCIe Boot Procedure\n+^^^^^^^^^^^^^^^^^^^\n+\n+The following steps describe the process of booting J784S4-EVM over PCIe:\n+\n+1. Compile the sample host program (provided after this section):\n+\n+ .. prompt:: bash\n+\n+ gcc -o pcie_boot_util pcie_boot_util.c\n+\n+2. Power on the J784S4-EVM (endpoint) after configuring boot mode switches\n+ for PCIe Boot.\n+\n+3. Copy the compiled sample host program (pcie_boot_util) and the bootloader\n+ images to the Root Complex. Check PCIe enumeration on Root Complex to ensure\n+ that the J784S4 EVM shows up as the PCIe Endpoint:\n+\n+ .. prompt:: bash\n+\n+ lspci\n+\n+ The endpoint will appear as a RAM device or with multiple functions:\n+\n+ .. code-block:: text\n+\n+ 0000:00:00.0 PCI bridge: Texas Instruments Device b012\n+ 0000:01:00.0 RAM memory: Texas Instruments Device b012\n+ 0000:01:00.1 Non-VGA unclassified device: Texas Instruments Device 0100\n+ 0000:01:00.2 Non-VGA unclassified device: Texas Instruments Device 0100\n+\n+4. Copy ``tiboot3.bin`` to the endpoint. Use ``lspci -vv`` to identify the BAR\n+ address:\n+\n+ .. prompt:: bash\n+\n+ sudo ./pcie_boot_util 0x4007100000 tiboot3.bin\n+\n+ The sample program automatically writes the image start address to\n+ ``0x41CF3FE0`` and the magic word ``0xB17CEAD9`` to ``0x41CF3FE4``.\n+\n+5. After ``tiboot3.bin`` is processed, the PCIe link will go down briefly.\n+ Remove the PCIe device and rescan the bus:\n+\n+ .. prompt:: bash\n+\n+ echo 1 > /sys/bus/pci/devices/0000\\:01\\:00.0/remove\n+ echo 1 > /sys/bus/pci/devices/0000\\:00\\:00.0/rescan\n+ lspci\n+\n+ The enumeration will change to something similar:\n+\n+ .. code-block:: text\n+\n+ 0000:00:00.0 PCI bridge: Texas Instruments Device b012\n+ 0000:01:00.0 RAM memory: Texas Instruments Device b010 (rev dc)\n+\n+ .. note::\n+\n+ When the Root-Complex enumerates the PCIe Endpoint after a 'remove-rescan' sequence,\n+ it is possible that the 'BAR' appears 'disabled'. If so, writing to the BAR via the\n+ 'pcie_boot_util' to transfer the bootloader image will have no effect. In such cases,\n+ run 'setpci -s 0000:01:00.0 COMMAND=0x02' on the Root-Complex after enumeration\n+ (with appropriate DOMAIN:BUS:DEVICE.FUNCTION corresponding to the Endpoint) to enable\n+ the BAR.\n+\n+6. Copy ``tispl.bin`` to the new BAR address (use ``lspci -vv`` to find):\n+\n+ .. prompt:: bash\n+\n+ sudo ./pcie_boot_util 0x4000400000 tispl.bin\n+\n+7. After ``tispl.bin`` is processed, the PCIe link will go down again. Remove\n+ and rescan the PCIe device:\n+\n+ .. prompt:: bash\n+\n+ echo 1 > /sys/bus/pci/devices/0000\\:01\\:00.0/remove\n+ echo 1 > /sys/bus/pci/devices/0000\\:00\\:00.0/rescan\n+\n+8. Copy ``u-boot.img``:\n+\n+ .. prompt:: bash\n+\n+ sudo ./pcie_boot_util 0x4000400000 u-boot.img\n+\n+9. After ``u-boot.img`` is successfully loaded, the boot process is complete\n+ and endpoint should boot till U-Boot prompt.\n+\n+.. note::\n+\n+ During the boot process, \"PCIe LINK DOWN\" messages might appear in kernel\n+ logs. This is expected as the endpoint resets and re-initializes the PCIe\n+ link after processing each boot stage.\n+\n+Sample Host Program\n+^^^^^^^^^^^^^^^^^^^\n+\n+The following C program can be used on the Root Complex to copy bootloader images\n+to the J784S4 endpoint:\n+\n+.. code-block:: c\n+\n+ #include <stdio.h>\n+ #include <stdlib.h>\n+ #include <fcntl.h>\n+ #include <sys/mman.h>\n+ #include <unistd.h>\n+ #include <string.h>\n+\n+ #define MAP_SIZE 0x400000\n+\n+ /*\n+ * bootloader_file: Path to the bootloader image (tiboot3.bin, tispl.bin and u-boot.img)\n+ * bootloader_mem: Memory allocated in RAM for reading the bootloader image file\n+ * bar_address: Address of BAR to which bootloader image will be written\n+ * bar_map_base: Mapping of the BAR Base Address for the program\n+ * load_address: Address in BAR region where bootloader is being transferred\n+ * transfer_completion_offset: Offset in BAR region to write to notify completion of transfer\n+ * fd_mem: File descriptor for opening /dev/mem\n+ * fptr: File pointer for bootloader image in filesystem\n+ * magic_word: Magic word to notify completion of tiboot3.bin transfer to Boot ROM\n+ * use_magic_word: Flag to indicate if Magic Word has to be written\n+ * file_size: Size of bootloader image\n+ * i: Iterator used during bootloader image transfer\n+ */\n+ int main(int argc, char *argv[])\n+ {\n+ off_t bar_address, load_address, transfer_completion_offset;\n+ unsigned char *bootloader_mem;\n+ const char *bootloader_file;\n+ int fd_mem, i, use_magic_word;\n+ unsigned int magic_word;\n+ void *bar_map_base;\n+ long file_size;\n+ FILE * fptr;\n+\n+ if (argc != 3) {\n+ printf(\"Usage: %s <bar_address> <bootloader_file>\\n\", argv[0]);\n+ return 0;\n+ }\n+\n+ bar_address = strtoul(argv[1], NULL, 16);\n+ bootloader_file = argv[2];\n+\n+ printf(\"Bootloader File: %s\\n\", bootloader_file);\n+ printf(\"BAR Address: 0x%lx\\n\", bar_address);\n+\n+ if(!strcmp(bootloader_file,\"tiboot3.bin\")) {\n+ transfer_completion_offset = 0xF3FE0;\n+ load_address = 0x41C00000;\n+ magic_word = 0xB17CEAD9;\n+ use_magic_word = 1;\n+ } else {\n+ transfer_completion_offset = MAP_SIZE - 0x4;\n+ load_address = 0xDEADBEEF;\n+ use_magic_word = 0;\n+ }\n+\n+ fd_mem = open(\"/dev/mem\", O_RDWR | O_SYNC);\n+ if(fd_mem == -1) {\n+ printf(\"failed to open /dev/mem\\n\");\n+ return -1;\n+ }\n+\n+ bar_map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, bar_address);\n+ if(bar_map_base == (void *)-1) {\n+ printf(\"failed to map BAR\\n\");\n+ return -1;\n+ }\n+\n+ fptr = fopen(bootloader_file, \"rb\");\n+ if (!fptr) {\n+ printf(\"failed to read bootloader file\\n\");\n+ return -1;\n+ }\n+\n+ fseek(fptr, 0, SEEK_END);\n+ file_size = ftell(fptr);\n+ rewind(fptr);\n+\n+ bootloader_mem = (unsigned char *)malloc(sizeof(char) * file_size);\n+ if(!bootloader_mem) {\n+ printf(\"failed to allocate local memory for bootloader file\\n\");\n+ return -1;\n+ }\n+\n+ if (fread(bootloader_mem, 1, file_size, fptr) != file_size) {\n+ printf(\"failed to read bootloader file into local memory\\n\");\n+ return -1;\n+ }\n+\n+ for(i = 0; i < file_size; i++) {\n+ *((char *)(bar_map_base) + i) = bootloader_mem[i];\n+ }\n+\n+ *(unsigned int *)(bar_map_base + transfer_completion_offset) = (unsigned int)(load_address);\n+\n+ if(use_magic_word) {\n+ *(unsigned int *)(bar_map_base + transfer_completion_offset + 4) = magic_word;\n+ printf(\"Magic word written for Boot ROM\\n\");\n+ }\n+\n+ printf(\"Transferred %s to Endpoint\\n\", bootloader_file);\n+ return 0;\n+ }\n+\n+This program copies the boot image to the PCIe endpoint's memory region and\n+writes the necessary control words to signal image transfer completion.\n+\n Debugging U-Boot\n ----------------\n \n", "prefixes": [ "v5", "10/10" ] }