Patch Detail
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Show a patch.
patch:
Update a patch.
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Update a patch.
GET /api/patches/2196745/?format=api
{ "id": 2196745, "url": "http://patchwork.ozlabs.org/api/patches/2196745/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260216102858.2745657-2-s-vadapalli@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216102858.2745657-2-s-vadapalli@ti.com>", "list_archive_url": null, "date": "2026-02-16T10:28:29", "name": "[v5,01/10] arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe boot", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "50600d1320be82e5a03a7d6a3199729d534c1ccc", "submitter": { "id": 84157, "url": "http://patchwork.ozlabs.org/api/people/84157/?format=api", "name": "Siddharth Vadapalli", "email": "s-vadapalli@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260216102858.2745657-2-s-vadapalli@ti.com/mbox/", "series": [ { "id": 492281, "url": "http://patchwork.ozlabs.org/api/series/492281/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=492281", "date": "2026-02-16T10:28:28", "name": "Add PCIe Boot support for TI J784S4 SoC", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/492281/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196745/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196745/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=selector1 header.b=xK9gjXC1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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helo=flwvzet200.ext.ti.com; pr=C", "From": "Siddharth Vadapalli <s-vadapalli@ti.com>", "To": "<trini@konsulko.com>, <m-chawdhry@ti.com>, <c-vankar@ti.com>,\n <neil.armstrong@linaro.org>, <marek.vasut+renesas@mailbox.org>,\n <u-kumar1@ti.com>, <j-keerthy@ti.com>, <semen.protsenko@linaro.org>,\n <afd@ti.com>, <anshuld@ti.com>, <peng.fan@nxp.com>, <ahalaney@redhat.com>,\n <mkorpershoek@kernel.org>, <n-francis@ti.com>", "CC": "<u-boot@lists.denx.de>, <srk@ti.com>, <s-vadapalli@ti.com>", "Subject": "[PATCH v5 01/10] arm: mach-k3: j784s4: Update SoC autogen data to\n enable PCIe boot", "Date": "Mon, 16 Feb 2026 15:58:29 +0530", "Message-ID": "<20260216102858.2745657-2-s-vadapalli@ti.com>", "X-Mailer": "git-send-email 2.51.1", "In-Reply-To": "<20260216102858.2745657-1-s-vadapalli@ti.com>", "References": "<20260216102858.2745657-1-s-vadapalli@ti.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-C2ProcessedOrg": "333ef613-75bf-4e12-a4b1-8e3623f5dcea", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SA2PEPF00003F62:EE_|SA2PR10MB4570:EE_", "X-MS-Office365-Filtering-Correlation-Id": "779094db-c0b6-4496-d2ef-08de6d4603a4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|82310400026|36860700013|376014|13003099007|921020;", "X-Microsoft-Antispam-Message-Info": "\n 0ADUvfXLO0k5h1kiHACNiNZB92MhiHwMw6wJVwJJ9wASAD6df2o8r9LBj3C2k0wuQiqz7n3BG4sIL3pMXRc6nw1hjCEmN72neIMomTn+oQrBnAH2R2KMHiLdiCo0razl9V7ejtqGwjnMNkq+NbyaLT4XB5i5QI0uMTocIl1lw8RcEfpi8yhdFVVjcJM3yfBtJsFZqnyvIt28h0JXHTfjFOX4IG/1J/bKFdOufKBMMKhnGhOPO2BcwdFb3JWxJjclIzOWDw51AlJGm33YwrvMqFj/3L1dkm0v4LMflaO3ADY9bP5kpV4TESN2IeE/AToHMWbgHZ+InDWtoDtOWw8qWK4XxbCLauM0yqGvrZ2UTz6iye/W0vvzytDQhrJBjdGcM2oK6442iTcJyOe3XEp7RRy+QN9UiRMJPdivCjODzBuslLaHGJbmGMUKcZVSitOv5e9Dtcftv45I8bk8ys4Z+3p4oVAGd/kU5c5TSHlwdFbmIE6S+M/De9Pd8Kf4wKsk2YTAq5a9Zv96opSNxfryF2c4GvG+VSps1XAdLQ6JC+2H3um1eadHzrEWQERDMOi7COaQMGDvZdyRPb0QfMnbbMgqqL7it6UH4XNuUAmCxGo86m+b+9f0vSME+KiuCLVIkkfMblmAoYTrLCqhUo3lTzbq85I+47NVMNPNh0Vd9FtXm3HQilVsXuGpmmp6Qzr8F82KJ5asQxBTnaV4lE7IJv/cJs2Dx2NupMo9cERdDz5U+kE22rrxSgKNIGqsrmJuN9LrsWjpldBGxthXPXaUIfOnQfo0toWVT2lNae2Fnr0jXnFYj82H8OvELrWbnQ6wl7nEUxS96PBzPNdkiLT8C0ZyfFrxmjuS0OToqwXf5hmK1YWz+YsgB1+M6OmoQdgqD6EDSU33feLi/R4gahOqyRyfzprn3cb5zdLf5g44x5cCI7tZPU2cLQvzYrrwV1vHd/u0G7RToUOkZPcGMKNw3ODi34JER2tSQQduIpYFqxrYeOBQMwQH90Rm8gzjKaq3UWx8kaWuN7U38R9pzFaJ5mUgi3whtU6qlaOeR4mRWImSMwA603Y3P8m6XjF0Ft8A6RHKX33Owf7RxyZRM5MoDh0iLnClTXpF87ElG4WN6wDnYnWeoMC7U/rjdEBfhWspl2h7BDszQM4QF0p0shnAuwFTu03UCz1FPIvcdjbhJmCaV27cKiXD8fp4Lrq0kQqcZY8elfMj/rdbGjWU11h26Sxl0nEeawYHrwZtgHW+ycuam2N7ZEDFOJQlCSZbm6dSHzh95B2/RCEdZsNVFBjklAh5iu5vLkS95+N+6umE+pkm3sAZ+e4Wz1FIc9hzFbr2OhNfhe91mm0b9Ha87L0vg7f17psadCbwL6Y63OVHQDfqDc+4BmgOAYJ5WaR/Z2AEogFC8A2MooRp70ZFN3yAOuWJyhlx8wn3c7CxiDVKFXg5NEhDqUcm2JXmfGeYFo5QEciLK86pgCG1bBvzbqiWSps0eWZrZxVQ8wvWJSSmKWwiAPSgd5rbrdtmx4+uW4KpWh0yLMnrGZHxKQTJ+wYMjvDnyB+xAKd2mwsWYLcbsQ28NpFgYPVL1JW2nURbh4D37mW6llwb1aOo77piibMSJqV6VECcvSpFO9aC+x77HEg=", "X-Forefront-Antispam-Report": "CIP:198.47.21.194; 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Ip=[198.47.21.194];\n Helo=[flwvzet200.ext.ti.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF00003F62.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA2PR10MB4570", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Hrushikesh Salunke <h-salunke@ti.com>\n\nTo enable PCIe boot on J784S4 SoC SERDES0 and PCIE1 should be enabled\nand configured at the R5 stage. Add the required clk-data and dev-data\nfor SERDES0 and PCIE1.\n\nSigned-off-by: Hrushikesh Salunke <h-salunke@ti.com>\nSigned-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>\n---\n arch/arm/mach-k3/r5/j784s4/clk-data.c | 184 ++++++++++++++++++++++++--\n arch/arm/mach-k3/r5/j784s4/dev-data.c | 45 ++++---\n 2 files changed, 201 insertions(+), 28 deletions(-)", "diff": "diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c\nindex 24780eb6562..228b424d3f2 100644\n--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c\n+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c\n@@ -5,7 +5,7 @@\n * This file is auto generated. Please do not hand edit and report any issues\n * to Bryan Brattlof <bb@ti.com>.\n *\n- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/\n+ * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/\n */\n \n #include <linux/clk-provider.h>\n@@ -64,13 +64,13 @@ static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {\n \t\"board_0_cpts0_rft_clk_out\",\n \t\"board_0_mcu_ext_refclk0_out\",\n \t\"board_0_ext_refclk1_out\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln0_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln1_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln2_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln3_txmclk\",\n \tNULL,\n \tNULL,\n-\tNULL,\n-\tNULL,\n-\tNULL,\n-\tNULL,\n-\tNULL,\n+\t\"wiz16b8m4ct3_main_0_ip1_ln2_txmclk\",\n \tNULL,\n \t\"hsdiv4_16fft_mcu_2_hsdivout1_clk\",\n \t\"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk\",\n@@ -166,6 +166,31 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = {\n \t\"board_0_mmc1_clk_out\",\n };\n \n+static const char * const usb0_serdes_refclk_mux_out0_parents[] = {\n+\t\"wiz16b8m4ct3_main_0_ip3_ln3_refclk\",\n+\tNULL,\n+};\n+\n+static const char * const usb0_serdes_rxclk_mux_out0_parents[] = {\n+\t\"wiz16b8m4ct3_main_0_ip3_ln3_rxclk\",\n+\tNULL,\n+};\n+\n+static const char * const usb0_serdes_rxfclk_mux_out0_parents[] = {\n+\t\"wiz16b8m4ct3_main_0_ip3_ln3_rxfclk\",\n+\tNULL,\n+};\n+\n+static const char * const usb0_serdes_txfclk_mux_out0_parents[] = {\n+\t\"wiz16b8m4ct3_main_0_ip3_ln3_txfclk\",\n+\tNULL,\n+};\n+\n+static const char * const usb0_serdes_txmclk_mux_out0_parents[] = {\n+\t\"wiz16b8m4ct3_main_0_ip3_ln3_txmclk\",\n+\tNULL,\n+};\n+\n static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {\n \t\"main_pll_hfosc_sel_out0\",\n \t\"hsdiv4_16fft_main_0_hsdivout0_clk\",\n@@ -197,18 +222,44 @@ static const char * const gtc_clk_mux_out0_parents[] = {\n \t\"board_0_cpts0_rft_clk_out\",\n \t\"board_0_mcu_ext_refclk0_out\",\n \t\"board_0_ext_refclk1_out\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln0_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln1_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln2_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln3_txmclk\",\n \tNULL,\n \tNULL,\n+\t\"wiz16b8m4ct3_main_0_ip1_ln2_txmclk\",\n \tNULL,\n+\t\"hsdiv4_16fft_mcu_2_hsdivout1_clk\",\n+\t\"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\",\n+};\n+\n+static const char * const pcien_cpts_rclk_mux_out1_parents[] = {\n+\t\"hsdiv4_16fft_main_3_hsdivout1_clk\",\n+\t\"postdiv3_16fft_main_0_hsdivout6_clk\",\n+\t\"board_0_mcu_cpts0_rft_clk_out\",\n+\t\"board_0_cpts0_rft_clk_out\",\n+\t\"board_0_mcu_ext_refclk0_out\",\n+\t\"board_0_ext_refclk1_out\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln0_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln1_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln2_txmclk\",\n+\t\"wiz16b8m4ct3_main_0_ip2_ln3_txmclk\",\n \tNULL,\n \tNULL,\n-\tNULL,\n-\tNULL,\n+\t\"wiz16b8m4ct3_main_0_ip1_ln2_txmclk\",\n \tNULL,\n \t\"hsdiv4_16fft_mcu_2_hsdivout1_clk\",\n \t\"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\",\n };\n \n+static const char * const serdes0_core_refclk_out0_parents[] = {\n+\t\"gluelogic_hfosc0_clkout\",\n+\t\"board_0_hfosc1_clk_out\",\n+\t\"hsdiv4_16fft_main_3_hsdivout4_clk\",\n+\t\"hsdiv4_16fft_main_2_hsdivout4_clk\",\n+};\n+\n static const struct clk_data clk_list[] = {\n \tCLK_FIXED_RATE(\"osc_27_mhz\", 27000000, 0),\n \tCLK_FIXED_RATE(\"osc_26_mhz\", 26000000, 0),\n@@ -270,11 +321,17 @@ static const struct clk_data clk_list[] = {\n \tCLK_FIXED_RATE(\"board_0_mcu_ext_refclk0_out\", 0, 0),\n \tCLK_FIXED_RATE(\"board_0_mmc1_clklb_out\", 0, 0),\n \tCLK_FIXED_RATE(\"board_0_mmc1_clk_out\", 0, 0),\n+\tCLK_FIXED_RATE(\"board_0_serdes0_refclk_n_out\", 0, 0),\n+\tCLK_FIXED_RATE(\"board_0_serdes0_refclk_p_out\", 0, 0),\n \tCLK_FIXED_RATE(\"board_0_tck_out\", 0, 0),\n \tCLK_FIXED_RATE(\"board_0_vout0_extpclkin_out\", 0, 0),\n \tCLK_FIXED_RATE(\"emmcsd4ss_main_0_emmcsdss_io_clk_o\", 0, 0),\n \tCLK_DIV(\"hsdiv4_16fft_mcu_2_hsdivout0_clk\", \"pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk\", 0x40d02080, 0, 7, 0, 0),\n \tCLK_DIV(\"hsdiv4_16fft_mcu_2_hsdivout1_clk\", \"pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk\", 0x40d02084, 0, 7, 0, 0),\n+\tCLK_FIXED_RATE(\"pcie_g3x4_128_main_1_pcie_lane0_txclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"pcie_g3x4_128_main_1_pcie_lane1_txclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"pcie_g3x4_128_main_1_pcie_lane2_txclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"pcie_g3x4_128_main_1_pcie_lane3_txclk\", 0, 0),\n \tCLK_PLL_DEFFREQ(\"pllfracf2_ssmod_16fft_main_0_foutvcop_clk\", \"main_pll_hfosc_sel_out0\", 0x680000, 0, 2000000000),\n \tCLK_DIV(\"pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv\", \"pllfracf2_ssmod_16fft_main_0_foutvcop_clk\", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),\n \tCLK_DIV(\"pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk\", \"pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv\", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),\n@@ -294,8 +351,42 @@ static const struct clk_data clk_list[] = {\n \tCLK_DIV(\"postdiv3_16fft_main_0_hsdivout8_clk\", \"pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk\", 0x6800a0, 0, 7, 0, 0),\n \tCLK_DIV(\"postdiv3_16fft_main_1_hsdivout5_clk\", \"pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk\", 0x681094, 0, 7, 0, 0),\n \tCLK_DIV(\"postdiv3_16fft_main_1_hsdivout7_clk\", \"pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk\", 0x68109c, 0, 7, 0, 0),\n+\tCLK_FIXED_RATE(\"usb3p0ss_16ffc_main_0_pipe_txclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_cmn_refclk_m\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_cmn_refclk_p\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip1_ln2_txmclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln0_refclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln0_rxclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln0_rxfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln0_txfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln0_txmclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln1_refclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln1_rxclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln1_rxfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln1_txfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln1_txmclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln2_refclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln2_rxclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln2_rxfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln2_txfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln2_txmclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln3_refclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln3_rxclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln3_rxfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln3_txfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip2_ln3_txmclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip3_ln3_refclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip3_ln3_rxclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip3_ln3_rxfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip3_ln3_txfclk\", 0, 0),\n+\tCLK_FIXED_RATE(\"wiz16b8m4ct3_main_0_ip3_ln3_txmclk\", 0, 0),\n \tCLK_MUX(\"emmcsd1_lb_clksel_out0\", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),\n \tCLK_MUX(\"mcu_clkout_mux_out0\", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),\n+\tCLK_MUX(\"usb0_serdes_refclk_mux_out0\", usb0_serdes_refclk_mux_out0_parents, 2, 0x104000, 27, 1, 0),\n+\tCLK_MUX(\"usb0_serdes_rxclk_mux_out0\", usb0_serdes_rxclk_mux_out0_parents, 2, 0x104000, 27, 1, 0),\n+\tCLK_MUX(\"usb0_serdes_rxfclk_mux_out0\", usb0_serdes_rxfclk_mux_out0_parents, 2, 0x104000, 27, 1, 0),\n+\tCLK_MUX(\"usb0_serdes_txfclk_mux_out0\", usb0_serdes_txfclk_mux_out0_parents, 2, 0x104000, 27, 1, 0),\n+\tCLK_MUX(\"usb0_serdes_txmclk_mux_out0\", usb0_serdes_txmclk_mux_out0_parents, 2, 0x104000, 27, 1, 0),\n \tCLK_DIV(\"hsdiv0_16fft_main_12_hsdivout0_clk\", \"pllfracf2_ssmod_16fft_main_12_foutvcop_clk\", 0x68c080, 0, 7, 0, 0),\n \tCLK_DIV(\"hsdiv0_16fft_main_26_hsdivout0_clk\", \"pllfracf2_ssmod_16fft_main_26_foutvcop_clk\", 0x69a080, 0, 7, 0, 0),\n \tCLK_DIV(\"hsdiv0_16fft_main_27_hsdivout0_clk\", \"pllfracf2_ssmod_16fft_main_27_foutvcop_clk\", 0x69b080, 0, 7, 0, 0),\n@@ -310,14 +401,18 @@ static const struct clk_data clk_list[] = {\n \tCLK_DIV_DEFFREQ(\"hsdiv4_16fft_main_1_hsdivout0_clk\", \"pllfracf2_ssmod_16fft_main_1_foutvcop_clk\", 0x681080, 0, 7, 0, 0, 192000000),\n \tCLK_DIV(\"hsdiv4_16fft_main_1_hsdivout2_clk\", \"pllfracf2_ssmod_16fft_main_1_foutvcop_clk\", 0x681088, 0, 7, 0, 0),\n \tCLK_DIV(\"hsdiv4_16fft_main_2_hsdivout2_clk\", \"pllfracf2_ssmod_16fft_main_2_foutvcop_clk\", 0x682088, 0, 7, 0, 0),\n+\tCLK_DIV(\"hsdiv4_16fft_main_2_hsdivout4_clk\", \"pllfracf2_ssmod_16fft_main_2_foutvcop_clk\", 0x682090, 0, 7, 0, 0),\n \tCLK_DIV(\"hsdiv4_16fft_main_3_hsdivout1_clk\", \"pllfracf2_ssmod_16fft_main_3_foutvcop_clk\", 0x683084, 0, 7, 0, 0),\n \tCLK_DIV(\"hsdiv4_16fft_main_3_hsdivout2_clk\", \"pllfracf2_ssmod_16fft_main_3_foutvcop_clk\", 0x683088, 0, 7, 0, 0),\n+\tCLK_DIV(\"hsdiv4_16fft_main_3_hsdivout4_clk\", \"pllfracf2_ssmod_16fft_main_3_foutvcop_clk\", 0x683090, 0, 7, 0, 0),\n \tCLK_MUX_PLLCTRL(\"k3_pll_ctrl_wrap_main_0_sysclkout_clk\", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),\n \tCLK_DIV(\"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\", \"k3_pll_ctrl_wrap_main_0_sysclkout_clk\", 0x410118, 0, 5, 0, 0),\n \tCLK_MUX(\"dpi0_ext_clksel_out0\", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),\n \tCLK_MUX(\"emmcsd_refclk_sel_out0\", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),\n \tCLK_MUX(\"emmcsd_refclk_sel_out1\", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),\n \tCLK_MUX(\"gtc_clk_mux_out0\", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),\n+\tCLK_MUX(\"pcien_cpts_rclk_mux_out1\", pcien_cpts_rclk_mux_out1_parents, 16, 0x108084, 0, 4, 0),\n+\tCLK_MUX(\"serdes0_core_refclk_out0\", serdes0_core_refclk_out0_parents, 4, 0x108400, 0, 2, 0),\n \tCLK_DIV_DEFFREQ(\"usart_programmable_clock_divider_out0\", \"hsdiv4_16fft_main_1_hsdivout0_clk\", 0x1081c0, 0, 2, 0, 0, 48000000),\n \tCLK_DIV(\"usart_programmable_clock_divider_out5\", \"hsdiv4_16fft_main_1_hsdivout0_clk\", 0x1081d4, 0, 2, 0, 0),\n \tCLK_DIV(\"usart_programmable_clock_divider_out8\", \"hsdiv4_16fft_main_1_hsdivout0_clk\", 0x1081e0, 0, 2, 0, 0),\n@@ -338,6 +433,11 @@ static const struct dev_clk soc_dev_clk_data[] = {\n \tDEV_CLK(61, 4, \"board_0_cpts0_rft_clk_out\"),\n \tDEV_CLK(61, 5, \"board_0_mcu_ext_refclk0_out\"),\n \tDEV_CLK(61, 6, \"board_0_ext_refclk1_out\"),\n+\tDEV_CLK(61, 7, \"wiz16b8m4ct3_main_0_ip2_ln0_txmclk\"),\n+\tDEV_CLK(61, 8, \"wiz16b8m4ct3_main_0_ip2_ln1_txmclk\"),\n+\tDEV_CLK(61, 9, \"wiz16b8m4ct3_main_0_ip2_ln2_txmclk\"),\n+\tDEV_CLK(61, 10, \"wiz16b8m4ct3_main_0_ip2_ln3_txmclk\"),\n+\tDEV_CLK(61, 13, \"wiz16b8m4ct3_main_0_ip1_ln2_txmclk\"),\n \tDEV_CLK(61, 15, \"hsdiv4_16fft_mcu_2_hsdivout1_clk\"),\n \tDEV_CLK(61, 16, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n \tDEV_CLK(61, 17, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n@@ -349,6 +449,11 @@ static const struct dev_clk soc_dev_clk_data[] = {\n \tDEV_CLK(63, 7, \"board_0_cpts0_rft_clk_out\"),\n \tDEV_CLK(63, 8, \"board_0_mcu_ext_refclk0_out\"),\n \tDEV_CLK(63, 9, \"board_0_ext_refclk1_out\"),\n+\tDEV_CLK(63, 10, \"wiz16b8m4ct3_main_0_ip2_ln0_txmclk\"),\n+\tDEV_CLK(63, 11, \"wiz16b8m4ct3_main_0_ip2_ln1_txmclk\"),\n+\tDEV_CLK(63, 12, \"wiz16b8m4ct3_main_0_ip2_ln2_txmclk\"),\n+\tDEV_CLK(63, 13, \"wiz16b8m4ct3_main_0_ip2_ln3_txmclk\"),\n+\tDEV_CLK(63, 16, \"wiz16b8m4ct3_main_0_ip1_ln2_txmclk\"),\n \tDEV_CLK(63, 18, \"hsdiv4_16fft_mcu_2_hsdivout1_clk\"),\n \tDEV_CLK(63, 19, \"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk\"),\n \tDEV_CLK(63, 20, \"hsdiv4_16fft_mcu_2_hsdivout0_clk\"),\n@@ -404,6 +509,8 @@ static const struct dev_clk soc_dev_clk_data[] = {\n \tDEV_CLK(157, 239, \"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk\"),\n \tDEV_CLK(157, 243, \"emmcsd4ss_main_0_emmcsdss_io_clk_o\"),\n \tDEV_CLK(157, 245, \"emmcsd4ss_main_0_emmcsdss_io_clk_o\"),\n+\tDEV_CLK(157, 324, \"wiz16b8m4ct3_main_0_cmn_refclk_m\"),\n+\tDEV_CLK(157, 326, \"wiz16b8m4ct3_main_0_cmn_refclk_p\"),\n \tDEV_CLK(157, 354, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n \tDEV_CLK(157, 359, \"dpi0_ext_clksel_out0\"),\n \tDEV_CLK(157, 360, \"mshsi2c_wkup_0_porscl\"),\n@@ -461,6 +568,42 @@ static const struct dev_clk soc_dev_clk_data[] = {\n \tDEV_CLK(279, 2, \"wkup_i2c_mcupll_bypass_out0\"),\n \tDEV_CLK(279, 3, \"hsdiv4_16fft_mcu_1_hsdivout3_clk\"),\n \tDEV_CLK(279, 4, \"gluelogic_hfosc0_clkout\"),\n+\tDEV_CLK(333, 0, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n+\tDEV_CLK(333, 2, \"pcien_cpts_rclk_mux_out1\"),\n+\tDEV_CLK(333, 3, \"hsdiv4_16fft_main_3_hsdivout1_clk\"),\n+\tDEV_CLK(333, 4, \"postdiv3_16fft_main_0_hsdivout6_clk\"),\n+\tDEV_CLK(333, 5, \"board_0_mcu_cpts0_rft_clk_out\"),\n+\tDEV_CLK(333, 6, \"board_0_cpts0_rft_clk_out\"),\n+\tDEV_CLK(333, 7, \"board_0_mcu_ext_refclk0_out\"),\n+\tDEV_CLK(333, 8, \"board_0_ext_refclk1_out\"),\n+\tDEV_CLK(333, 9, \"wiz16b8m4ct3_main_0_ip2_ln0_txmclk\"),\n+\tDEV_CLK(333, 10, \"wiz16b8m4ct3_main_0_ip2_ln1_txmclk\"),\n+\tDEV_CLK(333, 11, \"wiz16b8m4ct3_main_0_ip2_ln2_txmclk\"),\n+\tDEV_CLK(333, 12, \"wiz16b8m4ct3_main_0_ip2_ln3_txmclk\"),\n+\tDEV_CLK(333, 15, \"wiz16b8m4ct3_main_0_ip1_ln2_txmclk\"),\n+\tDEV_CLK(333, 17, \"hsdiv4_16fft_mcu_2_hsdivout1_clk\"),\n+\tDEV_CLK(333, 18, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n+\tDEV_CLK(333, 19, \"wiz16b8m4ct3_main_0_ip2_ln0_refclk\"),\n+\tDEV_CLK(333, 20, \"wiz16b8m4ct3_main_0_ip2_ln0_rxclk\"),\n+\tDEV_CLK(333, 21, \"wiz16b8m4ct3_main_0_ip2_ln0_rxfclk\"),\n+\tDEV_CLK(333, 23, \"wiz16b8m4ct3_main_0_ip2_ln0_txfclk\"),\n+\tDEV_CLK(333, 24, \"wiz16b8m4ct3_main_0_ip2_ln0_txmclk\"),\n+\tDEV_CLK(333, 25, \"wiz16b8m4ct3_main_0_ip2_ln1_refclk\"),\n+\tDEV_CLK(333, 26, \"wiz16b8m4ct3_main_0_ip2_ln1_rxclk\"),\n+\tDEV_CLK(333, 27, \"wiz16b8m4ct3_main_0_ip2_ln1_rxfclk\"),\n+\tDEV_CLK(333, 29, \"wiz16b8m4ct3_main_0_ip2_ln1_txfclk\"),\n+\tDEV_CLK(333, 30, \"wiz16b8m4ct3_main_0_ip2_ln1_txmclk\"),\n+\tDEV_CLK(333, 31, \"wiz16b8m4ct3_main_0_ip2_ln2_refclk\"),\n+\tDEV_CLK(333, 32, \"wiz16b8m4ct3_main_0_ip2_ln2_rxclk\"),\n+\tDEV_CLK(333, 33, \"wiz16b8m4ct3_main_0_ip2_ln2_rxfclk\"),\n+\tDEV_CLK(333, 35, \"wiz16b8m4ct3_main_0_ip2_ln2_txfclk\"),\n+\tDEV_CLK(333, 36, \"wiz16b8m4ct3_main_0_ip2_ln2_txmclk\"),\n+\tDEV_CLK(333, 37, \"wiz16b8m4ct3_main_0_ip2_ln3_refclk\"),\n+\tDEV_CLK(333, 38, \"wiz16b8m4ct3_main_0_ip2_ln3_rxclk\"),\n+\tDEV_CLK(333, 39, \"wiz16b8m4ct3_main_0_ip2_ln3_rxfclk\"),\n+\tDEV_CLK(333, 41, \"wiz16b8m4ct3_main_0_ip2_ln3_txfclk\"),\n+\tDEV_CLK(333, 42, \"wiz16b8m4ct3_main_0_ip2_ln3_txmclk\"),\n+\tDEV_CLK(333, 43, \"j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk\"),\n \tDEV_CLK(392, 0, \"usart_programmable_clock_divider_out5\"),\n \tDEV_CLK(392, 3, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n \tDEV_CLK(395, 0, \"usart_programmable_clock_divider_out8\"),\n@@ -473,11 +616,36 @@ static const struct dev_clk soc_dev_clk_data[] = {\n \tDEV_CLK(398, 1, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n \tDEV_CLK(398, 2, \"postdiv3_16fft_main_1_hsdivout7_clk\"),\n \tDEV_CLK(398, 3, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n+\tDEV_CLK(398, 4, \"usb0_serdes_refclk_mux_out0\"),\n+\tDEV_CLK(398, 5, \"wiz16b8m4ct3_main_0_ip3_ln3_refclk\"),\n+\tDEV_CLK(398, 7, \"usb0_serdes_rxclk_mux_out0\"),\n+\tDEV_CLK(398, 8, \"wiz16b8m4ct3_main_0_ip3_ln3_rxclk\"),\n+\tDEV_CLK(398, 10, \"usb0_serdes_rxfclk_mux_out0\"),\n+\tDEV_CLK(398, 11, \"wiz16b8m4ct3_main_0_ip3_ln3_rxfclk\"),\n+\tDEV_CLK(398, 14, \"usb0_serdes_txfclk_mux_out0\"),\n+\tDEV_CLK(398, 15, \"wiz16b8m4ct3_main_0_ip3_ln3_txfclk\"),\n+\tDEV_CLK(398, 17, \"usb0_serdes_txmclk_mux_out0\"),\n+\tDEV_CLK(398, 18, \"wiz16b8m4ct3_main_0_ip3_ln3_txmclk\"),\n \tDEV_CLK(398, 20, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n \tDEV_CLK(398, 21, \"usb0_refclk_sel_out0\"),\n \tDEV_CLK(398, 22, \"gluelogic_hfosc0_clkout\"),\n \tDEV_CLK(398, 23, \"board_0_hfosc1_clk_out\"),\n \tDEV_CLK(398, 28, \"board_0_tck_out\"),\n+\tDEV_CLK(404, 2, \"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk\"),\n+\tDEV_CLK(404, 3, \"board_0_serdes0_refclk_n_out\"),\n+\tDEV_CLK(404, 4, \"board_0_serdes0_refclk_p_out\"),\n+\tDEV_CLK(404, 5, \"hsdiv4_16fft_main_3_hsdivout4_clk\"),\n+\tDEV_CLK(404, 6, \"serdes0_core_refclk_out0\"),\n+\tDEV_CLK(404, 7, \"gluelogic_hfosc0_clkout\"),\n+\tDEV_CLK(404, 8, \"board_0_hfosc1_clk_out\"),\n+\tDEV_CLK(404, 9, \"hsdiv4_16fft_main_3_hsdivout4_clk\"),\n+\tDEV_CLK(404, 10, \"hsdiv4_16fft_main_2_hsdivout4_clk\"),\n+\tDEV_CLK(404, 39, \"pcie_g3x4_128_main_1_pcie_lane0_txclk\"),\n+\tDEV_CLK(404, 45, \"pcie_g3x4_128_main_1_pcie_lane1_txclk\"),\n+\tDEV_CLK(404, 51, \"pcie_g3x4_128_main_1_pcie_lane2_txclk\"),\n+\tDEV_CLK(404, 57, \"pcie_g3x4_128_main_1_pcie_lane3_txclk\"),\n+\tDEV_CLK(404, 81, \"usb3p0ss_16ffc_main_0_pipe_txclk\"),\n+\tDEV_CLK(404, 129, \"board_0_tck_out\"),\n };\n \n const struct ti_k3_clk_platdata j784s4_clk_platdata = {\ndiff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c\nindex 19901821225..2bb1a88ab3b 100644\n--- a/arch/arm/mach-k3/r5/j784s4/dev-data.c\n+++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c\n@@ -5,7 +5,7 @@\n * This file is auto generated. Please do not hand edit and report any issues\n * to Bryan Brattlof <bb@ti.com>.\n *\n- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/\n+ * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/\n */\n \n #include \"k3-dev.h\"\n@@ -21,10 +21,11 @@ static struct ti_pd soc_pd_list[] = {\n \t[1] = PSC_PD(3, &soc_psc_list[1], NULL),\n \t[2] = PSC_PD(0, &soc_psc_list[2], NULL),\n \t[3] = PSC_PD(1, &soc_psc_list[2], &soc_pd_list[2]),\n-\t[4] = PSC_PD(14, &soc_psc_list[2], NULL),\n-\t[5] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[4]),\n-\t[6] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[4]),\n-\t[7] = PSC_PD(38, &soc_psc_list[2], NULL),\n+\t[4] = PSC_PD(5, &soc_psc_list[2], NULL),\n+\t[5] = PSC_PD(14, &soc_psc_list[2], NULL),\n+\t[6] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[5]),\n+\t[7] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[5]),\n+\t[8] = PSC_PD(38, &soc_psc_list[2], NULL),\n };\n \n static struct ti_lpsc soc_lpsc_list[] = {\n@@ -44,13 +45,15 @@ static struct ti_lpsc soc_lpsc_list[] = {\n \t[13] = PSC_LPSC(20, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]),\n \t[14] = PSC_LPSC(23, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]),\n \t[15] = PSC_LPSC(25, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]),\n-\t[16] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL),\n-\t[17] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL),\n-\t[18] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[4], NULL),\n-\t[19] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[5], &soc_lpsc_list[18]),\n-\t[20] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[18]),\n-\t[21] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[22]),\n-\t[22] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[7], NULL),\n+\t[16] = PSC_LPSC(29, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]),\n+\t[17] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL),\n+\t[18] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL),\n+\t[19] = PSC_LPSC(64, &soc_psc_list[2], &soc_pd_list[4], NULL),\n+\t[20] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[5], NULL),\n+\t[21] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[20]),\n+\t[22] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[20]),\n+\t[23] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[8], &soc_lpsc_list[24]),\n+\t[24] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[8], NULL),\n };\n \n static struct ti_dev soc_dev_list[] = {\n@@ -78,14 +81,16 @@ static struct ti_dev soc_dev_list[] = {\n \tPSC_DEV(398, &soc_lpsc_list[13]),\n \tPSC_DEV(141, &soc_lpsc_list[14]),\n \tPSC_DEV(140, &soc_lpsc_list[15]),\n-\tPSC_DEV(146, &soc_lpsc_list[16]),\n-\tPSC_DEV(392, &soc_lpsc_list[17]),\n-\tPSC_DEV(395, &soc_lpsc_list[17]),\n-\tPSC_DEV(198, &soc_lpsc_list[18]),\n-\tPSC_DEV(202, &soc_lpsc_list[19]),\n-\tPSC_DEV(203, &soc_lpsc_list[20]),\n-\tPSC_DEV(133, &soc_lpsc_list[21]),\n-\tPSC_DEV(193, &soc_lpsc_list[22]),\n+\tPSC_DEV(333, &soc_lpsc_list[16]),\n+\tPSC_DEV(146, &soc_lpsc_list[17]),\n+\tPSC_DEV(392, &soc_lpsc_list[18]),\n+\tPSC_DEV(395, &soc_lpsc_list[18]),\n+\tPSC_DEV(404, &soc_lpsc_list[19]),\n+\tPSC_DEV(198, &soc_lpsc_list[20]),\n+\tPSC_DEV(202, &soc_lpsc_list[21]),\n+\tPSC_DEV(203, &soc_lpsc_list[22]),\n+\tPSC_DEV(133, &soc_lpsc_list[23]),\n+\tPSC_DEV(193, &soc_lpsc_list[24]),\n };\n \n const struct ti_k3_pd_platdata j784s4_pd_platdata = {\n", "prefixes": [ "v5", "01/10" ] }