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GET /api/patches/2196634/?format=api
{ "id": 2196634, "url": "http://patchwork.ozlabs.org/api/patches/2196634/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260215163847.3522572-6-den@valinux.co.jp/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260215163847.3522572-6-den@valinux.co.jp>", "list_archive_url": null, "date": "2026-02-15T16:38:43", "name": "[v7,5/9] PCI: dwc: ep: Expose integrated eDMA resources via EPC aux-resource API", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "32930132c32da30c59a6d80ff436449ad968cc3a", "submitter": { "id": 91573, "url": "http://patchwork.ozlabs.org/api/people/91573/?format=api", "name": "Koichiro Den", "email": "den@valinux.co.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260215163847.3522572-6-den@valinux.co.jp/mbox/", "series": [ { "id": 492228, "url": "http://patchwork.ozlabs.org/api/series/492228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492228", "date": "2026-02-15T16:38:38", "name": "PCI: endpoint: pci-ep-msi: Add embedded doorbell fallback", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/492228/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196634/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196634/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47316-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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dkim=pass header.d=valinux.co.jp; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=valinux.co.jp;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=5WxmsAc17oVlQJKPf6xRLziiFoTNMAWHD1uw1KDj7SQ=;\n b=T/ovfZFLKInya35oQ1EHhuQ0C36oz+zO59d4hS5yY0Pal/wW7WNxa0M4xPuzS+Jso0Lx6smtrqJYoy8EG62xHvoUeVZcvKZSXh/iIfLI10qcuA1DtfEBQ7bukOFIzv/FPr4ICUWI2k1X+pZznYvlKNdHEZJ4PJshMqO3cHstrWc=", "From": "Koichiro Den <den@valinux.co.jp>", "To": "jingoohan1@gmail.com,\n\tmani@kernel.org,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\theiko@sntech.de,\n\tkishon@kernel.org,\n\tjdmason@kudzu.us,\n\tdave.jiang@intel.com,\n\tallenbh@gmail.com,\n\tcassel@kernel.org,\n\tshawn.lin@rock-chips.com,\n\tFrank.Li@nxp.com", "Cc": "linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-rockchip@lists.infradead.org,\n\tntb@lists.linux.dev", "Subject": "[PATCH v7 5/9] PCI: dwc: ep: Expose integrated eDMA resources via EPC\n aux-resource API", "Date": "Mon, 16 Feb 2026 01:38:43 +0900", "Message-ID": "<20260215163847.3522572-6-den@valinux.co.jp>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20260215163847.3522572-1-den@valinux.co.jp>", "References": "<20260215163847.3522572-1-den@valinux.co.jp>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "TYWP286CA0024.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:400:262::9) To TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:405:38f::10)", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "TY7P286MB7722:EE_|OSCP286MB5196:EE_", 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"X-OriginatorOrg": "valinux.co.jp", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 44f625b9-310a-4e39-a19e-08de6cb0bc1c", "X-MS-Exchange-CrossTenant-AuthSource": "TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Feb 2026 16:39:05.9626\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "7a57bee8-f73d-4c5f-a4f7-d72c91c8c111", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n Oaffq4UOMtUJLjhU/e3RSJYQGWHZoehZ1SwdpYhBmXprFTEK4yDcPT7ZN0eYuxOehx4771NXBRH5WkQKFVgWbg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "OSCP286MB5196" }, "content": "Implement the EPC aux-resource API for DesignWare endpoint controllers\nwith integrated eDMA.\n\nReport:\n - DMA controller MMIO window (PCI_EPC_AUX_DMA_CTRL_MMIO)\n - interrupt-emulation doorbell register (PCI_EPC_AUX_DOORBELL_MMIO),\n including its Linux IRQ\n - per-channel LL descriptor regions (PCI_EPC_AUX_DMA_CHAN_DESC)\n\nIf the DMA controller MMIO window is already exposed via a\nplatform-owned fixed BAR subregion, also provide the BAR number and\noffset so EPF drivers can reuse it without reprogramming the BAR.\n\nSigned-off-by: Koichiro Den <den@valinux.co.jp>\n---\n .../pci/controller/dwc/pcie-designware-ep.c | 149 ++++++++++++++++++\n 1 file changed, 149 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c\nindex 7e7844ff0f7e..ffd2797b7b81 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c\n@@ -808,6 +808,154 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)\n \treturn ep->ops->get_features(ep);\n }\n \n+static const struct pci_epc_bar_rsvd_region *\n+dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep,\n+\t\t\t\tenum pci_epc_bar_rsvd_region_type type,\n+\t\t\t\tenum pci_barno *bar,\n+\t\t\t\tresource_size_t *bar_offset)\n+{\n+\tconst struct pci_epc_features *features;\n+\tconst struct pci_epc_bar_desc *bar_desc;\n+\tconst struct pci_epc_bar_rsvd_region *r;\n+\tint i, j;\n+\n+\tif (!ep->ops->get_features)\n+\t\treturn NULL;\n+\n+\tfeatures = ep->ops->get_features(ep);\n+\tif (!features)\n+\t\treturn NULL;\n+\n+\tfor (i = BAR_0; i <= BAR_5; i++) {\n+\t\tbar_desc = &features->bar[i];\n+\n+\t\tif (!bar_desc->nr_rsvd_regions || !bar_desc->rsvd_regions)\n+\t\t\tcontinue;\n+\n+\t\tfor (j = 0; j < bar_desc->nr_rsvd_regions; j++) {\n+\t\t\tr = &bar_desc->rsvd_regions[j];\n+\n+\t\t\tif (r->type != type)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (bar)\n+\t\t\t\t*bar = i;\n+\t\t\tif (bar_offset)\n+\t\t\t\t*bar_offset = r->offset;\n+\t\t\treturn r;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int\n+dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n+\t\t\t struct pci_epc_aux_resource *resources,\n+\t\t\t int num_resources)\n+{\n+\tstruct dw_pcie_ep *ep = epc_get_drvdata(epc);\n+\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n+\tconst struct pci_epc_bar_rsvd_region *rsvd;\n+\tstruct dw_edma_chip *edma = &pci->edma;\n+\tenum pci_barno dma_ctrl_bar = NO_BAR;\n+\tint ll_cnt = 0, needed, idx = 0;\n+\tresource_size_t db_offset = edma->db_offset;\n+\tresource_size_t dma_ctrl_bar_offset = 0;\n+\tresource_size_t dma_reg_size;\n+\tunsigned int i;\n+\n+\tif (!pci->edma_reg_size)\n+\t\treturn 0;\n+\n+\tdma_reg_size = pci->edma_reg_size;\n+\n+\tfor (i = 0; i < edma->ll_wr_cnt; i++)\n+\t\tif (edma->ll_region_wr[i].sz)\n+\t\t\tll_cnt++;\n+\n+\tfor (i = 0; i < edma->ll_rd_cnt; i++)\n+\t\tif (edma->ll_region_rd[i].sz)\n+\t\t\tll_cnt++;\n+\n+\tneeded = 1 + ll_cnt + (db_offset != ~0 ? 1 : 0);\n+\n+\t/* Count query mode */\n+\tif (!resources || !num_resources)\n+\t\treturn needed;\n+\n+\tif (num_resources < needed)\n+\t\treturn -ENOSPC;\n+\n+\trsvd = dw_pcie_ep_find_bar_rsvd_region(ep,\n+\t\t\t\t\t PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,\n+\t\t\t\t\t &dma_ctrl_bar,\n+\t\t\t\t\t &dma_ctrl_bar_offset);\n+\tif (rsvd && rsvd->size < dma_reg_size)\n+\t\tdma_reg_size = rsvd->size;\n+\n+\t/* DMA register block */\n+\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t.type = PCI_EPC_AUX_DMA_CTRL_MMIO,\n+\t\t.phys_addr = pci->edma_reg_phys,\n+\t\t.size = dma_reg_size,\n+\t\t.bar = dma_ctrl_bar,\n+\t\t.bar_offset = dma_ctrl_bar_offset,\n+\t};\n+\n+\t/*\n+\t * For interrupt-emulation doorbells, report a standalone resource\n+\t * instead of bundling it into the DMA controller MMIO resource.\n+\t */\n+\tif (db_offset != ~0) {\n+\t\tif (dma_reg_size < sizeof(u32) ||\n+\t\t db_offset > dma_reg_size - sizeof(u32))\n+\t\t\treturn -EINVAL;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DOORBELL_MMIO,\n+\t\t\t.phys_addr = pci->edma_reg_phys + db_offset,\n+\t\t\t.size = sizeof(u32),\n+\t\t\t.bar = dma_ctrl_bar,\n+\t\t\t.bar_offset = dma_ctrl_bar != NO_BAR ?\n+\t\t\t\t\tdma_ctrl_bar_offset + db_offset : 0,\n+\t\t\t.u.db_mmio = {\n+\t\t\t\t.irq = edma->db_irq,\n+\t\t\t},\n+\t\t};\n+\t}\n+\n+\t/* One LL region per write channel */\n+\tfor (i = 0; i < edma->ll_wr_cnt; i++) {\n+\t\tif (!edma->ll_region_wr[i].sz)\n+\t\t\tcontinue;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DMA_CHAN_DESC,\n+\t\t\t.phys_addr = edma->ll_region_wr[i].paddr,\n+\t\t\t.size = edma->ll_region_wr[i].sz,\n+\t\t\t.bar = NO_BAR,\n+\t\t\t.bar_offset = 0,\n+\t\t};\n+\t}\n+\n+\t/* One LL region per read channel */\n+\tfor (i = 0; i < edma->ll_rd_cnt; i++) {\n+\t\tif (!edma->ll_region_rd[i].sz)\n+\t\t\tcontinue;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DMA_CHAN_DESC,\n+\t\t\t.phys_addr = edma->ll_region_rd[i].paddr,\n+\t\t\t.size = edma->ll_region_rd[i].sz,\n+\t\t\t.bar = NO_BAR,\n+\t\t\t.bar_offset = 0,\n+\t\t};\n+\t}\n+\n+\treturn idx;\n+}\n+\n static const struct pci_epc_ops epc_ops = {\n \t.write_header\t\t= dw_pcie_ep_write_header,\n \t.set_bar\t\t= dw_pcie_ep_set_bar,\n@@ -823,6 +971,7 @@ static const struct pci_epc_ops epc_ops = {\n \t.start\t\t\t= dw_pcie_ep_start,\n \t.stop\t\t\t= dw_pcie_ep_stop,\n \t.get_features\t\t= dw_pcie_ep_get_features,\n+\t.get_aux_resources\t= dw_pcie_ep_get_aux_resources,\n };\n \n /**\n", "prefixes": [ "v7", "5/9" ] }