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GET /api/patches/2196595/?format=api
{ "id": 2196595, "url": "http://patchwork.ozlabs.org/api/patches/2196595/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260215112543.4817-12-mohamed@unpredictable.fr/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260215112543.4817-12-mohamed@unpredictable.fr>", "list_archive_url": null, "date": "2026-02-15T11:25:40", "name": "[v10,11/14] hvf: sync registers used at EL2", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5736e04478dfb0e3428fdd551186e75d7d8b9ad6", "submitter": { "id": 91318, "url": "http://patchwork.ozlabs.org/api/people/91318/?format=api", "name": "Mohamed Mediouni", "email": "mohamed@unpredictable.fr" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260215112543.4817-12-mohamed@unpredictable.fr/mbox/", "series": [ { "id": 492211, "url": "http://patchwork.ozlabs.org/api/series/492211/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492211", "date": "2026-02-15T11:25:32", "name": "HVF: Add support for platform vGIC and nested virtualisation", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/492211/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196595/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196595/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=XRB1YaQb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Sun, 15 Feb 2026 06:26:17 -0500", "from outbound.mr.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-west-2a-100-percent-0 (Postfix) with ESMTPS id\n 6623E18002AD; Sun, 15 Feb 2026 11:26:13 +0000 (UTC)", "from localhost.localdomain (unknown [17.57.152.38])\n by p00-icloudmta-asmtp-us-west-2a-100-percent-0 (Postfix) with ESMTPSA id\n 4807D18004DC; Sun, 15 Feb 2026 11:26:11 +0000 (UTC)" ], "Dkim-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1771154774; x=1773746774;\n bh=FVokaBFGw8s/kbfJt1bNlUw/IqCgXWLByKpYAjS307s=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=XRB1YaQb5GTC3NKz8mN4emqY05UcA2tL1yG7WKg/pbAedyvhOy6SiVxrPn/hF8gXK7wYtduV4t+NbsTAG6LFw7ly5LQ7nNw/gi5D8UvCyC9iZ6HuTDcr0yGJrpY/ocHNUrplfdXauS37C1RzXuwvcouC1NxZP8uBVdAJZtfKzpit+3loRBOPLgYZqhIan/gyDTWasFkSJT2NCq2U+4YExP4r2otzPFHqtVVZN/caq0+FKQLCiaIM+ZDHCrrPlbRstFc8cyt9hpy5pSHbZwAKPs5Y7hbpJQDfapSQ54oW+Bml9efh7khPYU8DwZYxr7rlVTjdlFinyc3r4fJhEv92aw==", "mail-alias-created-date": "1752046281608", "From": "Mohamed Mediouni <mohamed@unpredictable.fr>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,\n Mads Ynddal <mads@ynddal.dk>, Roman Bolshakov <rbolshakov@ddn.com>,\n Phil Dennis-Jordan <phil@philjordan.eu>, Alexander Graf <agraf@csgraf.de>,\n Paolo Bonzini <pbonzini@redhat.com>, Cameron Esfahani <dirty@apple.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>", "Subject": "[PATCH v10 11/14] hvf: sync registers used at EL2", "Date": "Sun, 15 Feb 2026 12:25:40 +0100", "Message-ID": "<20260215112543.4817-12-mohamed@unpredictable.fr>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260215112543.4817-1-mohamed@unpredictable.fr>", "References": "<20260215112543.4817-1-mohamed@unpredictable.fr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "qvIa5CV_HgLdo8lsWgOuZ6YqSDdLwoTZ", "X-Proofpoint-GUID": "qvIa5CV_HgLdo8lsWgOuZ6YqSDdLwoTZ", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjE1MDA5MiBTYWx0ZWRfX3xOnesgMLujd\n QBHCGaxGdwuyz9NNARvyUJS9bsf3IEZWmAYja1fz2JaW3OMzX0zl8aBQeEL1MLg6cJZ5/+JMaqH\n osF4z+FH/VnjvopP9ptIZTCuyvAJmBfbeRx7bM7tUaMNk7VUZqYzH43IqKCCV+bgvFCwiALps8A\n FUSbqtUNzNIHxqp+eefrtkj/BB1M2x/3CQWF5ZIvVnMIVm7f2It3ld9EdKVe0Gii5cMHIdQMeqG\n ZMqVYM54YZVBOjy6z6iGvC3tjLcd6anpIRQ4uh3TIz4iJz3eJBRcKNsqpii24ty9CAUNrzdWXcP\n jaI8N/mJlHw8rZzM5sVMcp7dKgiiIUgG8EOV28lA8xS70oghjmjwluGeQ9ziJE=", "X-Authority-Info-Out": "v=2.4 cv=Vcf6/Vp9 c=1 sm=1 tr=0 ts=6991ad55\n cx=c_apl:c_apl_out:c_pps a=9OgfyREA4BUYbbCgc0Y0oA==:117\n a=9OgfyREA4BUYbbCgc0Y0oA==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22\n a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=7gx8ALrZTGDtSAp3wEYA:9", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-15_04,2026-02-13_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0 mlxlogscore=848\n bulkscore=0 mlxscore=0 lowpriorityscore=0\n suspectscore=0 adultscore=0\n malwarescore=0 phishscore=0 clxscore=1030 spamscore=0 classifier=spam\n authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2602150092", "X-JNJ": "\n AAAAAAABDHov+zv7mqR4JMY3pc/W5wrEH1Y1l9ErIi1/WakYCkO8tvz7btCqL7K/TaOppj263npxRL/KM3zVo+d0BNb4qD5R4GSdsi+wLHCb9LstxEj9G+GSylx2ByZB7xAKztXSLnyeXDY39IUgV9/LKZvv7WB3YzkfMZR/RwwMRlTpGqkbSDriU3HMv8LAcaDitX8NgvEHRSOKIWq46NroUZpd9F2WjBIW5Srwt7TZCWZ/SgVZJ3WGQLEnOkdzO1xQy46v6u+Tvo5CZgI2XbDrcwMuRsTHH61RPJNScNSABvaCW+xDFyrjv+7dnL3kaa9VmeA5HmQO4/fW0DvnPV+X4UgnGfJnyfq5HbWNE/8i+9EbtGfwGM/T8PHPmQy96n17toCHLgeXeOXSWV/pBsC5cS8d88Xu80A4ueYIWMS2fv3Ho7MiMsBrHc5FWqLVXDu7CQWwa0f52dA7HQcaYLj5pIy/fNhzRziZOVxqQCe7fZ/uDNPc/JokISPxmPePx8yTT3KbvDRVRG8TuT9gFw0WvFfA4BLP7xPTuRLdj7Pae0VvcceAMg/UATQvJ+24nmHQdkenTf08tzzQBHk1zqdCmOeybBL4TI+bo7IRWjjPHHjoJU/DTl6sfLr4zXk5QKtA6YljVJ+lmFQttlShf0Erx/4BTi5sdgEjgGFu0RChJ8iz3hmSGzq2Vi+Eeek=", "Received-SPF": "pass client-ip=57.103.68.48;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.mr.icloud.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "When starting up the VM at EL2, more sysregs are available. Sync the state of those.\n\nIn addition, sync the state of the EL1 physical timer when the vGIC is used, even\nif running at EL1. However, no OS running at EL1 is expected to use those registers.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n target/arm/hvf/hvf.c | 37 +++++++++++++++++++++++++++++++++----\n target/arm/hvf/sysreg.c.inc | 35 +++++++++++++++++++++++++++++++++++\n 2 files changed, 68 insertions(+), 4 deletions(-)", "diff": "diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex 0aae421ba6..f286e6a014 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -412,13 +412,34 @@ static const struct hvf_reg_match hvf_fpreg_match[] = {\n #define DEF_SYSREG(HVF_ID, ...) \\\n QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n \n+#define DEF_SYSREG_EL2(HVF_ID, ...) \\\n+ QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n+\n+#define DEF_SYSREG_VGIC(HVF_ID, ...) \\\n+ QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n+\n+#define DEF_SYSREG_VGIC_EL2(HVF_ID, ...) \\\n+ QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n+\n #include \"sysreg.c.inc\"\n \n #undef DEF_SYSREG\n+#undef DEF_SYSREG_EL2\n+#undef DEF_SYSREG_VGIC\n+#undef DEF_SYSREG_VGIC_EL2\n+\n+#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID},\n+#define DEF_SYSREG_EL2(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, .el2 = true},\n+#define DEF_SYSREG_VGIC(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, .vgic = true},\n+#define DEF_SYSREG_VGIC_EL2(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, true, true},\n+\n+struct hvf_sreg {\n+ hv_sys_reg_t sreg;\n+ bool vgic;\n+ bool el2;\n+};\n \n-#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID,\n-\n-static const hv_sys_reg_t hvf_sreg_list[] = {\n+static struct hvf_sreg hvf_sreg_list[] = {\n #include \"sysreg.c.inc\"\n };\n \n@@ -1052,11 +1073,19 @@ int hvf_arch_init_vcpu(CPUState *cpu)\n \n /* Populate cp list for all known sysregs */\n for (i = 0; i < sregs_match_len; i++) {\n- hv_sys_reg_t hvf_id = hvf_sreg_list[i];\n+ hv_sys_reg_t hvf_id = hvf_sreg_list[i].sreg;\n uint64_t kvm_id = HVF_TO_KVMID(hvf_id);\n uint32_t key = kvm_to_cpreg_id(kvm_id);\n const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);\n \n+ if (hvf_sreg_list[i].vgic && !hvf_irqchip_in_kernel()) {\n+ continue;\n+ }\n+\n+ if (hvf_sreg_list[i].el2 && !hvf_nested_virt_enabled()) {\n+ continue;\n+ }\n+\n if (ri) {\n assert(!(ri->type & ARM_CP_NO_RAW));\n arm_cpu->cpreg_indexes[sregs_cnt++] = kvm_id;\ndiff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc\nindex 067a8603fa..ce4a4fdc68 100644\n--- a/target/arm/hvf/sysreg.c.inc\n+++ b/target/arm/hvf/sysreg.c.inc\n@@ -145,3 +145,38 @@ DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 3, 3, 13, 0, 3)\n DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 3, 3, 14, 3, 1)\n DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 3, 3, 14, 3, 2)\n DEF_SYSREG(HV_SYS_REG_SP_EL1, 3, 4, 4, 1, 0)\n+\n+DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_CTL_EL0, 3, 3, 14, 2, 1)\n+DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_CVAL_EL0, 3, 3, 14, 2, 2)\n+#ifdef SYNC_NO_RAW_REGS\n+DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_TVAL_EL0, 3, 3, 14, 2, 0)\n+#endif\n+\n+DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHCTL_EL2, 3, 4, 14, 1, 0)\n+DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_CVAL_EL2, 3, 4, 14, 2, 2)\n+DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_CTL_EL2, 3, 4, 14, 2, 1)\n+#ifdef SYNC_NO_RAW_REGS\n+DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_TVAL_EL2, 3, 4, 14, 2, 0)\n+#endif\n+DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTVOFF_EL2, 3, 4, 14, 0, 3)\n+\n+DEF_SYSREG_EL2(HV_SYS_REG_CPTR_EL2, 3, 4, 1, 1, 2)\n+DEF_SYSREG_EL2(HV_SYS_REG_ELR_EL2, 3, 4, 4, 0, 1)\n+DEF_SYSREG_EL2(HV_SYS_REG_ESR_EL2, 3, 4, 5, 2, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_FAR_EL2, 3, 4, 6, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_HCR_EL2, 3, 4, 1, 1, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_HPFAR_EL2, 3, 4, 6, 0, 4)\n+DEF_SYSREG_EL2(HV_SYS_REG_MAIR_EL2, 3, 4, 10, 2, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_MDCR_EL2, 3, 4, 1, 1, 1)\n+DEF_SYSREG_EL2(HV_SYS_REG_SCTLR_EL2, 3, 4, 1, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_SPSR_EL2, 3, 4, 4, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_SP_EL2, 3, 6, 4, 1, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_TCR_EL2, 3, 4, 2, 0, 2)\n+DEF_SYSREG_EL2(HV_SYS_REG_TPIDR_EL2, 3, 4, 13, 0, 2)\n+DEF_SYSREG_EL2(HV_SYS_REG_TTBR0_EL2, 3, 4, 2, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_TTBR1_EL2, 3, 4, 2, 0, 1)\n+DEF_SYSREG_EL2(HV_SYS_REG_VBAR_EL2, 3, 4, 12, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_VMPIDR_EL2, 3, 4, 0, 0, 5)\n+DEF_SYSREG_EL2(HV_SYS_REG_VPIDR_EL2, 3, 4, 0, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_VTCR_EL2, 3, 4, 2, 1, 2)\n+DEF_SYSREG_EL2(HV_SYS_REG_VTTBR_EL2, 3, 4, 2, 1, 0)\n", "prefixes": [ "v10", "11/14" ] }