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GET /api/patches/2196482/?format=api
{ "id": 2196482, "url": "http://patchwork.ozlabs.org/api/patches/2196482/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260214034135.220413-8-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260214034135.220413-8-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-02-14T03:41:27", "name": "[RFCv2,07/13] intel_iommu: Handle PASID entry addition for pc_inv_dsc request", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bbca6b762a68afd4d634d418473b75eda5d7915c", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Zhenzhong Duan", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260214034135.220413-8-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 492156, "url": "http://patchwork.ozlabs.org/api/series/492156/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492156", "date": "2026-02-14T03:41:20", "name": "intel_iommu: Enable PASID support for passthrough device", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492156/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196482/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196482/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=mKCToUGD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fCZdQ6k5Rz1xpY\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 14 Feb 2026 14:43:38 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vr6Y0-0005Bd-Bb; Fri, 13 Feb 2026 22:42:20 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1vr6Xw-0005BE-Vp\n for qemu-devel@nongnu.org; Fri, 13 Feb 2026 22:42:17 -0500", "from mgamail.intel.com ([198.175.65.12])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1vr6Xu-0008J1-No\n for qemu-devel@nongnu.org; Fri, 13 Feb 2026 22:42:16 -0500", "from orviesa009.jf.intel.com ([10.64.159.149])\n by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:14 -0800", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:10 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1771040535; x=1802576535;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=/24uhyM/Od+BHezlBFfol4UXOL2XJqBNPTrkAwP14ww=;\n b=mKCToUGDDDz/RW+62z8i6pzmMe4yWan/TH8b64RqlQYs/JDxjbVJPqzF\n 7Or0vCo7/+K5wT7Q9ZhHc7Pj2Vs+qQb0ZwlcjOgtMKJTpZhaINU17eGYQ\n Df9g4H/A+DXtjUQOZNkQL85EOS6cqYM23yW57fDsllhfMk9lJ6YG1KYbz\n qfHhOM0/R9wNkSo6OYMCWbPmeAAlofoatEudBuy9bSTdkkkRa4omjerZq\n XLFIew34CS6SvKzFUuJ/Pz6hCD+oTEmtow58eFy7lG5qk5ezWiWlvq/UG\n RIEOPIifQInx/sjqZCI7kPfHE57qz1KEtUUwmams41DNe7I1pO0W0oroe w==;", "X-CSE-ConnectionGUID": [ "OGPRGOHTSTaWxzbSwbvzOQ==", "9kE6+MAeS4W+ZqSpkJwDQA==" ], "X-CSE-MsgGUID": [ "8BiqaXg8Q6qrSiiQ85I1og==", "Fu7z/v4DSpaLrVS0uOOz8A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11700\"; a=\"83666842\"", "E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"83666842\"", "E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"212933091\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[RFCv2 PATCH 07/13] intel_iommu: Handle PASID entry addition for\n pc_inv_dsc request", "Date": "Fri, 13 Feb 2026 22:41:27 -0500", "Message-ID": "<20260214034135.220413-8-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260214034135.220413-1-zhenzhong.duan@intel.com>", "References": "<20260214034135.220413-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.12;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Structure VTDAddressSpace includes some elements suitable for emulated\ndevice and passthrough device without PASID, e.g., address space,\ndifferent memory regions, etc, it is also protected by vtd iommu lock,\nall these are useless and become a burden for passthrough device with\nPASID.\n\nWhen there are lots of PASIDs used in one device, the AS and MRs are\nall registered to memory core and impact the whole system performance.\n\nSo instead of using VTDAddressSpace to cache pasid entry for each pasid\nof a passthrough device, we define a light weight structure\nVTDACCELPASIDCacheEntry with only necessary elements for each pasid. We\nwill use this struct as a parameter to conduct binding/unbinding to\nnested hwpt and to record the current binded nested hwpt. It's also\ndesigned to support PASID_0.\n\nWhen guest creates new PASID entries, QEMU will capture the pc_inv_dsc\n(pasid cache invalidation) request, walk through each pasid in each\npassthrough device for valid pasid entries, create a new\nVTDACCELPASIDCacheEntry if not existing yet.\n\nSigned-off-by: Yi Liu <yi.l.liu@intel.com>\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\n---\n hw/i386/intel_iommu_accel.h | 13 +++\n hw/i386/intel_iommu_internal.h | 8 ++\n hw/i386/intel_iommu.c | 3 +\n hw/i386/intel_iommu_accel.c | 170 +++++++++++++++++++++++++++++++++\n 4 files changed, 194 insertions(+)", "diff": "diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h\nindex e5f0b077b4..a77fd06fe0 100644\n--- a/hw/i386/intel_iommu_accel.h\n+++ b/hw/i386/intel_iommu_accel.h\n@@ -12,6 +12,13 @@\n #define HW_I386_INTEL_IOMMU_ACCEL_H\n #include CONFIG_DEVICES\n \n+typedef struct VTDACCELPASIDCacheEntry {\n+ VTDHostIOMMUDevice *vtd_hiod;\n+ VTDPASIDEntry pe;\n+ uint32_t pasid;\n+ QLIST_ENTRY(VTDACCELPASIDCacheEntry) next;\n+} VTDACCELPASIDCacheEntry;\n+\n #ifdef CONFIG_VTD_ACCEL\n bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,\n Error **errp);\n@@ -20,6 +27,7 @@ bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp);\n void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_id,\n uint32_t pasid, hwaddr addr,\n uint64_t npages, bool ih);\n+void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info);\n void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops);\n #else\n static inline bool vtd_check_hiod_accel(IntelIOMMUState *s,\n@@ -49,6 +57,11 @@ static inline void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s,\n {\n }\n \n+static inline void vtd_pasid_cache_sync_accel(IntelIOMMUState *s,\n+ VTDPASIDCacheInfo *pc_info)\n+{\n+}\n+\n static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops)\n {\n }\ndiff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex 8b020fb3a4..e4bcc884b0 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -615,6 +615,7 @@ typedef struct VTDRootEntry VTDRootEntry;\n #define VTD_CTX_ENTRY_SCALABLE_SIZE 32\n \n #define PASID_0 0\n+#define VTD_SM_CONTEXT_ENTRY_PDTS(x) extract64((x)->val[0], 9, 3)\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw))\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL\n #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL\n@@ -645,6 +646,7 @@ typedef struct VTDPIOTLBInvInfo {\n #define VTD_PASID_DIR_BITS_MASK (0x3fffULL)\n #define VTD_PASID_DIR_INDEX(pasid) (((pasid) >> 6) & VTD_PASID_DIR_BITS_MASK)\n #define VTD_PASID_DIR_FPD (1ULL << 1) /* Fault Processing Disable */\n+#define VTD_PASID_TABLE_ENTRY_NUM (1ULL << 6)\n #define VTD_PASID_TABLE_BITS_MASK (0x3fULL)\n #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK)\n #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */\n@@ -710,6 +712,7 @@ typedef struct VTDHostIOMMUDevice {\n PCIBus *bus;\n uint8_t devfn;\n HostIOMMUDevice *hiod;\n+ QLIST_HEAD(, VTDACCELPASIDCacheEntry) pasid_cache_list;\n } VTDHostIOMMUDevice;\n \n /*\n@@ -767,6 +770,11 @@ static inline int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2)\n return memcmp(p1, p2, sizeof(*p1));\n }\n \n+static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTDContextEntry *ce)\n+{\n+ return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce) + 7);\n+}\n+\n int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasid,\n VTDPASIDDirEntry *pdire);\n int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid,\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex d257dd95f6..bc7589a776 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -3185,6 +3185,8 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info)\n g_hash_table_foreach(s->vtd_address_spaces, vtd_pasid_cache_sync_locked,\n pc_info);\n vtd_iommu_unlock(s);\n+\n+ vtd_pasid_cache_sync_accel(s, pc_info);\n }\n \n static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s)\n@@ -4743,6 +4745,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,\n vtd_hiod->devfn = (uint8_t)devfn;\n vtd_hiod->iommu_state = s;\n vtd_hiod->hiod = hiod;\n+ QLIST_INIT(&vtd_hiod->pasid_cache_list);\n \n if (!vtd_check_hiod(s, vtd_hiod, errp)) {\n g_free(vtd_hiod);\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex c2757f3bcd..0acf3ae77f 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -257,6 +257,176 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_id,\n vtd_flush_host_piotlb_locked, &piotlb_info);\n }\n \n+static void vtd_find_add_pc(VTDHostIOMMUDevice *vtd_hiod, uint32_t pasid,\n+ VTDPASIDEntry *pe)\n+{\n+ VTDACCELPASIDCacheEntry *vtd_pce;\n+\n+ QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) {\n+ if (vtd_pce->pasid == pasid) {\n+ if (vtd_pasid_entry_compare(pe, &vtd_pce->pe)) {\n+ vtd_pce->pe = *pe;\n+ }\n+ return;\n+ }\n+ }\n+\n+ vtd_pce = g_malloc0(sizeof(VTDACCELPASIDCacheEntry));\n+ vtd_pce->vtd_hiod = vtd_hiod;\n+ vtd_pce->pasid = pasid;\n+ vtd_pce->pe = *pe;\n+ QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next);\n+}\n+\n+/*\n+ * This function walks over PASID range within [start, end) in a single\n+ * PASID table for entries matching @info type/did, then create\n+ * VTDACCELPASIDCacheEntry if not exist yet.\n+ */\n+static void vtd_sm_pasid_table_walk_one(VTDHostIOMMUDevice *vtd_hiod,\n+ dma_addr_t pt_base,\n+ int start,\n+ int end,\n+ VTDPASIDCacheInfo *info)\n+{\n+ IntelIOMMUState *s = vtd_hiod->iommu_state;\n+ VTDPASIDEntry pe;\n+ int pasid;\n+\n+ for (pasid = start; pasid < end; pasid++) {\n+ if (vtd_get_pe_in_pasid_leaf_table(s, pasid, pt_base, &pe) ||\n+ !vtd_pe_present(&pe)) {\n+ continue;\n+ }\n+\n+ if ((info->type == VTD_INV_DESC_PASIDC_G_DSI ||\n+ info->type == VTD_INV_DESC_PASIDC_G_PASID_SI) &&\n+ (info->did != VTD_SM_PASID_ENTRY_DID(&pe))) {\n+ /*\n+ * VTD_PASID_CACHE_DOMSI and VTD_PASID_CACHE_PASIDSI\n+ * requires domain id check. If domain id check fail,\n+ * go to next pasid.\n+ */\n+ continue;\n+ }\n+\n+ vtd_find_add_pc(vtd_hiod, pasid, &pe);\n+ }\n+}\n+\n+/*\n+ * In VT-d scalable mode translation, PASID dir + PASID table is used.\n+ * This function aims at looping over a range of PASIDs in the given\n+ * two level table to identify the pasid config in guest.\n+ */\n+static void vtd_sm_pasid_table_walk(VTDHostIOMMUDevice *vtd_hiod,\n+ dma_addr_t pdt_base,\n+ int start, int end,\n+ VTDPASIDCacheInfo *info)\n+{\n+ VTDPASIDDirEntry pdire;\n+ int pasid = start;\n+ int pasid_next;\n+ dma_addr_t pt_base;\n+\n+ while (pasid < end) {\n+ pasid_next = (pasid + VTD_PASID_TABLE_ENTRY_NUM) &\n+ ~(VTD_PASID_TABLE_ENTRY_NUM - 1);\n+ pasid_next = pasid_next < end ? pasid_next : end;\n+\n+ if (!vtd_get_pdire_from_pdir_table(pdt_base, pasid, &pdire)\n+ && vtd_pdire_present(&pdire)) {\n+ pt_base = pdire.val & VTD_PASID_TABLE_BASE_ADDR_MASK;\n+ vtd_sm_pasid_table_walk_one(vtd_hiod, pt_base, pasid, pasid_next,\n+ info);\n+ }\n+ pasid = pasid_next;\n+ }\n+}\n+\n+static void vtd_replay_pasid_bind_for_dev(VTDHostIOMMUDevice *vtd_hiod,\n+ int start, int end,\n+ VTDPASIDCacheInfo *pc_info)\n+{\n+ IntelIOMMUState *s = vtd_hiod->iommu_state;\n+ VTDContextEntry ce;\n+ int dev_max_pasid = 1 << vtd_hiod->hiod->caps.max_pasid_log2;\n+\n+ if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_hiod->bus),\n+ vtd_hiod->devfn, &ce)) {\n+ VTDPASIDCacheInfo walk_info = *pc_info;\n+ uint32_t ce_max_pasid = vtd_sm_ce_get_pdt_entry_num(&ce) *\n+ VTD_PASID_TABLE_ENTRY_NUM;\n+\n+ end = MIN(end, MIN(dev_max_pasid, ce_max_pasid));\n+\n+ vtd_sm_pasid_table_walk(vtd_hiod, VTD_CE_GET_PASID_DIR_TABLE(&ce),\n+ start, end, &walk_info);\n+ }\n+}\n+\n+/*\n+ * This function replays the guest pasid bindings by walking the two level\n+ * guest PASID table. For each valid pasid entry, it creates an entry\n+ * VTDACCELPASIDCacheEntry dynamically if not exist yet. This entry holds\n+ * info specific to a pasid\n+ */\n+void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info)\n+{\n+ int start = PASID_0, end = 1 << s->pasid;\n+ VTDHostIOMMUDevice *vtd_hiod;\n+ GHashTableIter as_it;\n+\n+ if (!s->fsts) {\n+ return;\n+ }\n+\n+ /*\n+ * VTDPASIDCacheInfo honors PCI pasid but VTDACCELPASIDCacheEntry honors\n+ * iommu pasid\n+ */\n+ if (pc_info->pasid == PCI_NO_PASID) {\n+ pc_info->pasid = PASID_0;\n+ }\n+\n+ switch (pc_info->type) {\n+ case VTD_INV_DESC_PASIDC_G_PASID_SI:\n+ start = pc_info->pasid;\n+ end = pc_info->pasid + 1;\n+ /* fall through */\n+ case VTD_INV_DESC_PASIDC_G_DSI:\n+ /*\n+ * loop all assigned devices, do domain id check in\n+ * vtd_sm_pasid_table_walk_one() after get pasid entry.\n+ */\n+ break;\n+ case VTD_INV_DESC_PASIDC_G_GLOBAL:\n+ /* loop all assigned devices */\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ /*\n+ * In this replay, one only needs to care about the devices which are\n+ * backed by host IOMMU. Those devices have a corresponding vtd_hiod\n+ * in s->vtd_host_iommu_dev. For devices not backed by host IOMMU, it\n+ * is not necessary to replay the bindings since their cache should be\n+ * created in the future DMA address translation.\n+ *\n+ * VTD translation callback never accesses vtd_hiod and its corresponding\n+ * cached pasid entry, so no iommu lock needed here.\n+ */\n+ g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev);\n+ while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) {\n+ if (!object_dynamic_cast(OBJECT(vtd_hiod->hiod),\n+ TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) {\n+ continue;\n+ }\n+ vtd_replay_pasid_bind_for_dev(vtd_hiod, start, end, pc_info);\n+ }\n+}\n+\n static uint64_t vtd_get_host_iommu_quirks(uint32_t type,\n void *caps, uint32_t size)\n {\n", "prefixes": [ "RFCv2", "07/13" ] }