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GET /api/patches/2196472/?format=api
{ "id": 2196472, "url": "http://patchwork.ozlabs.org/api/patches/2196472/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260214034135.220413-6-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260214034135.220413-6-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-02-14T03:41:25", "name": "[RFCv2,05/13] intel_iommu: Change pasid property from bool to uint8", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "989dfebb570adbc81a160945978d278d6740273d", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Zhenzhong Duan", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260214034135.220413-6-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 492156, "url": "http://patchwork.ozlabs.org/api/series/492156/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492156", "date": "2026-02-14T03:41:20", "name": "intel_iommu: Enable PASID support for passthrough device", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492156/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196472/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196472/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=kO6Fd0Vv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Fri, 13 Feb 2026 22:42:08 -0500", "from orviesa009.jf.intel.com ([10.64.159.149])\n by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:06 -0800", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:03 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1771040527; x=1802576527;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=UOlCwBlzHCMuS6OLxbG1uRV5/WHYGyGNEx4/PbnGdYw=;\n b=kO6Fd0Vvafsdc1A6soqs5c1Orf181BfLLp739xVmucsYrQjXinzCgjqr\n 4EnzHknfixAXYlS3K14Yc1IROZL2Mv7C8dz5LXFUFmTAYDRR1UaB/qRUU\n yVP0ICAJELiDJXlHOcMvu2068cUVvOtRDvt0nsg5FpaeTcCC6/kJRnuAH\n kxfaJ/twjA+idodwvNjzBZ/H9CJziOyZT2tfNa3JCpkKXI3l+0VYp9NEq\n qWWhod5n0sR8Ye+KG61BUhC89/l3+WQRdz52zyJT9+rSIYaoNdLryZE8I\n fWN8GOT3ddLsz77QBIj6iaIdcjoTQMA+Gv986tNFCBUva5N3kSe2cqw25 w==;", "X-CSE-ConnectionGUID": [ "IsP/XK5GR7aqLSAS2jYBOg==", "aLyRGausTQmAfUICrvKflA==" ], "X-CSE-MsgGUID": [ "5d6UmafeR4mSm0iWh93NQA==", "q8Y8xv8pSWWJV+2BtW1mhA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11700\"; a=\"83666826\"", "E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"83666826\"", "E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"212933038\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[RFCv2 PATCH 05/13] intel_iommu: Change pasid property from bool to\n uint8", "Date": "Fri, 13 Feb 2026 22:41:25 -0500", "Message-ID": "<20260214034135.220413-6-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260214034135.220413-1-zhenzhong.duan@intel.com>", "References": "<20260214034135.220413-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.12;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "'x-pasid-mode' is a bool property, we need an extra 'pss' property to\nrepresent PASID size supported. Because there is no any device in QEMU\nsupporting pasid capability yet, no guest could use the pasid feature\nuntil now, 'x-pasid-mode' takes no effect.\n\nSo instead of an extra 'pss' property we can use a single 'pasid'\nproperty of uint8 type to represent if pasid is supported and the PASID\nbits size. A value of N > 0 means pasid is supported and N - 1 is the\nvalue in PSS field in ECAP register.\n\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\n---\n hw/i386/intel_iommu_internal.h | 1 -\n include/hw/i386/intel_iommu.h | 2 +-\n hw/i386/intel_iommu.c | 4 ++--\n 3 files changed, 3 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex 11a53aa369..04a9392e8a 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -195,7 +195,6 @@\n #define VTD_ECAP_MHMV (15ULL << 20)\n #define VTD_ECAP_SRS (1ULL << 31)\n #define VTD_ECAP_NWFS (1ULL << 33)\n-#define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid */\n #define VTD_ECAP_PASID (1ULL << 40)\n #define VTD_ECAP_PDS (1ULL << 42)\n #define VTD_ECAP_SMTS (1ULL << 43)\ndiff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h\nindex 54c2b6b77a..bb957b93e0 100644\n--- a/include/hw/i386/intel_iommu.h\n+++ b/include/hw/i386/intel_iommu.h\n@@ -315,7 +315,7 @@ struct IntelIOMMUState {\n OnOffAuto intr_eim; /* Toggle for EIM cabability */\n uint8_t aw_bits; /* Host/IOVA address width (in bits) */\n bool dma_drain; /* Whether DMA r/w draining enabled */\n- bool pasid; /* Whether to support PASID */\n+ uint8_t pasid; /* PASID supported in bits, 0 if not */\n bool fs1gp; /* First Stage 1-GByte Page Support */\n \n /* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex 92a367d657..e27a7c725f 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -4186,7 +4186,7 @@ static const Property vtd_properties[] = {\n DEFINE_PROP_BOOL(\"x-scalable-mode\", IntelIOMMUState, scalable_mode, FALSE),\n DEFINE_PROP_BOOL(\"x-flts\", IntelIOMMUState, fsts, FALSE),\n DEFINE_PROP_BOOL(\"snoop-control\", IntelIOMMUState, snoop_control, false),\n- DEFINE_PROP_BOOL(\"x-pasid-mode\", IntelIOMMUState, pasid, false),\n+ DEFINE_PROP_UINT8(\"pasid\", IntelIOMMUState, pasid, 0),\n DEFINE_PROP_BOOL(\"svm\", IntelIOMMUState, svm, false),\n DEFINE_PROP_BOOL(\"dma-drain\", IntelIOMMUState, dma_drain, true),\n DEFINE_PROP_BOOL(\"stale-tm\", IntelIOMMUState, stale_tm, false),\n@@ -5033,7 +5033,7 @@ static void vtd_cap_init(IntelIOMMUState *s)\n }\n \n if (s->pasid) {\n- s->ecap |= VTD_ECAP_PASID | VTD_ECAP_PSS;\n+ s->ecap = VTD_ECAP_PASID | deposit64(s->ecap, 35, 5, s->pasid - 1);\n }\n }\n \n", "prefixes": [ "RFCv2", "05/13" ] }