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GET /api/patches/2196446/?format=api
{ "id": 2196446, "url": "http://patchwork.ozlabs.org/api/patches/2196446/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260213231428.613164-1-sathyanarayanan.kuppuswamy@linux.intel.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260213231428.613164-1-sathyanarayanan.kuppuswamy@linux.intel.com>", "list_archive_url": null, "date": "2026-02-13T23:14:28", "name": "[v2] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ac8b34d819397e34b8cbdfd468253bbd4b450227", "submitter": { "id": 66129, "url": "http://patchwork.ozlabs.org/api/people/66129/?format=api", "name": "Kuppuswamy Sathyanarayanan", "email": "sathyanarayanan.kuppuswamy@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260213231428.613164-1-sathyanarayanan.kuppuswamy@linux.intel.com/mbox/", "series": [ { "id": 492147, "url": "http://patchwork.ozlabs.org/api/series/492147/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492147", "date": "2026-02-13T23:14:28", "name": "[v2] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492147/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196446/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196446/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47284-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=M4yRTrTM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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a=\"72257492\"", "E=Sophos;i=\"6.21,289,1763452800\";\n d=\"scan'208\";a=\"72257492\"", "E=Sophos;i=\"6.21,289,1763452800\";\n d=\"scan'208\";a=\"211713511\"" ], "X-ExtLoop1": "1", "From": "Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>", "Cc": "Lukas Wunner <lukas@wunner.de>,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable\n PME status", "Date": "Fri, 13 Feb 2026 15:14:28 -0800", "Message-ID": "\n <20260213231428.613164-1-sathyanarayanan.kuppuswamy@linux.intel.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "On Intel Catlow Lake platforms, PCH PCIe root ports do not reliably\nupdate PME status registers (PME Status and PME Requester_ID in the\nRoot Status register) during D3hot to D0 transitions, even though PME\ninterrupts are delivered correctly.\n\nThis issue manifests during PCIe hotplug operations as follows:\n\n1. After a hot-remove event, the PCIe port transitions to D3hot and\n the hotplug interrupt enable (HPIE) flag is disabled as the port\n enters low power state.\n\n2. When a hot-add occurs while the port is in D3hot, a PME interrupt\n fires as expected to wake the port.\n\n3. However, the PME interrupt handler finds the PME_Status and\n PME_Requester_ID registers unpopulated, preventing identification\n of which device triggered the PME. The handler returns IRQ_NONE,\n leaving the port in D3hot.\n\n4. Because the port remains in D3hot with HPIE disabled, the hotplug\n driver ignores the hot-add event, resulting in the newly inserted\n device not being recognized.\n\nThe PME interrupt delivery mechanism itself works correctly;\ninterrupts arrive reliably. The problem is purely the missing status\nregister updates. Verification via IOSF-SideBand (IOSF-SB) backdoor\nreads confirms that these registers remain empty when the PME\ninterrupt fires. Neither BIOS nor kernel code is clearing these\nregisters.\n\nThis issue is present in all steppings of Catlow Lake PCH and affects\ncustomers in production deployments. A public hardware errata document\nis not yet available.\n\nWork around this issue by disabling runtime PM for affected ports,\nkeeping them in D0 during runtime operation. This ensures hotplug\nevents are handled via direct interrupts rather than relying on\nunreliable PME-based wakeup.\n\nDuring system suspend/resume, PCIe ports are resumed unconditionally\nwhen coming out of system sleep due to DPM_FLAG_SMART_SUSPEND set by\npcie_portdrv_probe(), and pciehp re-enables interrupts and checks slot\noccupation status during resume.\n\nThe quirk is applied only to Catlow PCH PCIe root ports (device IDs\n0x7a30 through 0x7a4b). Catlow CPU PCIe ports are not affected as\nthey are not hotplug-capable.\n\nSuggested-by: Lukas Wunner <lukas@wunner.de>\nSigned-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>\n---\n\nChanges since v1:\n * Removed hack in hotplug driver and disabled runtime PM on affected ports.\n * Fixed the commit log and comments accordingly.\n\n drivers/pci/quirks.c | 49 ++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 49 insertions(+)", "diff": "diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 280cd50d693b..779cd65b1a8a 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -6340,3 +6340,52 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev)\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout);\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout);\n #endif\n+\n+/*\n+ * Intel Catlow Lake PCH PCIe root ports have a hardware issue where\n+ * PME status registers (PME Status and PME Requester_ID in Root Status)\n+ * are not reliably updated during D3hot to D0 transitions, even though\n+ * PME interrupts are delivered correctly.\n+ *\n+ * When a hotplug event occurs while the port is in D3hot, the PME\n+ * interrupt fires but the status registers remain empty. This prevents\n+ * the PME handler from identifying the event source, leaving the port\n+ * in D3hot and causing the hotplug driver to miss the event.\n+ *\n+ * Disable runtime PM to keep these ports in D0, ensuring hotplug events\n+ * are handled via direct interrupts.\n+ */\n+static void quirk_intel_catlow_pcie_no_pme_wakeup(struct pci_dev *dev)\n+{\n+\tpm_runtime_disable(&dev->dev);\n+\tpci_info(dev, \"Catlow PCH port: PME status unreliable, disabling runtime PM\\n\");\n+}\n+/* Apply quirk to Catlow Lake PCH root ports (0x7a30 - 0x7a4b) */\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a30, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a31, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a32, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a33, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a34, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a35, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a36, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a37, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a38, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a39, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3a, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3b, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3c, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3d, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3e, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3f, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a40, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a41, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a42, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a43, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a44, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a45, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a46, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a47, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a48, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a49, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a4a, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a4b, quirk_intel_catlow_pcie_no_pme_wakeup);\n", "prefixes": [ "v2" ] }