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GET /api/patches/2196403/?format=api
{ "id": 2196403, "url": "http://patchwork.ozlabs.org/api/patches/2196403/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/AM0PR08MB39716CE154525CF52E69DAE6B061A@AM0PR08MB3971.eurprd08.prod.outlook.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<AM0PR08MB39716CE154525CF52E69DAE6B061A@AM0PR08MB3971.eurprd08.prod.outlook.com>", "list_archive_url": null, "date": "2026-02-13T18:13:49", "name": "[v2] RISC-V: Add LMUL-aware RVV cost model for the Spacemit-X60 core", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4502e4de861b8107159f554f52988e45497c0d0a", "submitter": { "id": 92581, "url": "http://patchwork.ozlabs.org/api/people/92581/?format=api", "name": "Nikola Ratkovac", "email": "Nikola.Ratkovac@rt-rk.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/AM0PR08MB39716CE154525CF52E69DAE6B061A@AM0PR08MB3971.eurprd08.prod.outlook.com/mbox/", "series": [ { "id": 492129, "url": "http://patchwork.ozlabs.org/api/series/492129/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=492129", "date": "2026-02-13T18:13:49", "name": "[v2] RISC-V: Add LMUL-aware RVV cost model for the Spacemit-X60 core", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492129/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196403/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196403/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", 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header.from=rt-rk.com;\n dkim=pass header.d=rt-rk.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=rt-rk.com; h=cc\n :content-type:date:from:message-id:mime-version:subject:to; s=\n s2021; bh=lrVuTdDAXY/ZUwSCZ/vfx4X8+78HH22/SghmcZ7z9JI=; b=ClbcrS\n gJMw2nPGxHgy6Vo/Ltp4Z8k+jvBeihSyvEd0Ystb7MD4cS1QFA3thEcWEnlmI9kN\n DpLRwWyjmb+2xgWMhlJnHPxksj584Re04eL+auaxPeXOJt5y5ZIj79NPvIWLbiGa\n oHaD2D8wJB7zD6SZPY9U/BUi5opltWPYqG1LQRTktQV/sR8HzuuFjb03J5XnOO5V\n eQoEK1RqEpmGwpmMDcZNs1OiVt4tZCpvR77LZRvO/u8Rn/px0HXakVIQROs3CXHt\n IP4nXTQwelT+3+AeBk5qsubG0dXl+dRhAuIg2P4mAYgIJW6Vy3CF/YXwIzbnH2JV\n qmdc1nMx+6PpMsBw==", "From": "Nikola Ratkovac <Nikola.Ratkovac@rt-rk.com>", "To": "\"gcc-patches@gcc.gnu.org\" <gcc-patches@gcc.gnu.org>", "CC": "Dusan Stojkovic <Dusan.Stojkovic@rt-rk.com>, Robin Dapp\n <rdapp.gcc@gmail.com>, \"law@gcc.gnu.org\" <law@gcc.gnu.org>", "Subject": "[PATCH v2] RISC-V: Add LMUL-aware RVV cost model for the Spacemit-X60\n core", "Thread-Topic": "[PATCH v2] RISC-V: Add LMUL-aware RVV cost model for the\n Spacemit-X60 core", "Thread-Index": "AQHcnRNzEk95G6Ay7U+mPuac2IECsg==", "Date": "Fri, 13 Feb 2026 18:13:49 +0000", "Message-ID": "\n <AM0PR08MB39716CE154525CF52E69DAE6B061A@AM0PR08MB3971.eurprd08.prod.outlook.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "yes", "X-MS-TNEF-Correlator": "", "msip_labels": "", "x-ms-publictraffictype": "Email", "x-ms-traffictypediagnostic": "AM0PR08MB3971:EE_|AS8PR08MB9792:EE_", "x-ms-office365-filtering-correlation-id": "04e5a63c-0d5d-4177-77c4-08de6b2ba2ec", "x-ms-exchange-senderadcheck": "1", "x-ms-exchange-antispam-relay": "0", "x-microsoft-antispam": "BCL:0;\n ARA:13230040|19092799006|366016|376014|6049299003|1800799024|4053099003|38070700021;", "x-microsoft-antispam-message-info": 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"Content-Type": "multipart/mixed;\n boundary=\"_002_AM0PR08MB39716CE154525CF52E69DAE6B061AAM0PR08MB3971eurp_\"", "MIME-Version": "1.0", "X-OriginatorOrg": "rt-rk.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "AM0PR08MB3971.eurprd08.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 04e5a63c-0d5d-4177-77c4-08de6b2ba2ec", "X-MS-Exchange-CrossTenant-originalarrivaltime": "13 Feb 2026 18:13:49.3850 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "9bc3ed46-a3ca-43f0-b84e-9a557209a7df", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n 4MGCZ8WQv2qGR3LLLfXJ9X2tebQ8YZzwYMp8eVn8+javcL2vl3xddxPjF7+WXZbyZYY3JRJH8PxHuSY08/YC12ZD10aQUI9uVuvitS0F4Ek=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AS8PR08MB9792", "X-Authority-Analysis": "v=2.4 cv=YaywJgRf c=1 sm=1 tr=0 ts=698f69e0 cx=c_pps\n a=hISv9GAE2vGumUItzbjiRQ==:117 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"1J-D3B6q0wRtUPHXC048K6K5wL81tkdd", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch introduces a vector cost model for the Spacemit-X60 core,\nusing dynamic LMUL scaling with the -madjust-lmul-cost flag.\n\nCompared to the previous patch, I dropped the local 'vector_lmul'\nattribute and the corresponding LMUL-aware cost logic in spacemit-x60.md.\nInstead, Spacemit-X60 tuning now enables -madjust-lmul-cost implicitly,\nand riscv_sched_adjust_cost is updated so that the adjustment applies to\nspacemit_x60 in addition to the generic out-of-order model.\n\nThe stress tests I previously used to tune individual instruction costs\n(with the LMUL-aware logic implemented directly in spacemit-x60.md)\nnow show a regression in performance. The most likely cause is the implicit\n-madjust-lmul-cost scaling, since some instructions performed better\nwith non-power-of-two scaling (or with no LMUL scaling at all), so the\nuniform ×(1,2,4,8) adjustment affects performance.\n\nUpdated performance results:\n\n| Benchmark | Metric | Trunk | Vector Cost Model | Δ (%) |\n|------------------|--------|------------------|-------------------|---------|\n| SciMark2-C | cycles | 311,450,555,453 | 313,278,899,107 | +0.56% |\n|------------------|--------|------------------|-------------------|---------|\n| tramp3d-v4 | cycles | 23,788,980,247 | 21,073,526,428 | -12.89% |\n|------------------|--------|------------------|-------------------|---------|\n| Freebench/neural | cycles | 471,707,641 | 435,842,612 | -8.23% |\n|------------------|--------|------------------|-------------------|---------|\n\nBenchmarks were run from the LLVM test-suite\n(MultiSource/Benchmarks) using:\n\ntaskset -c 0 perf stat -r 10 ./...\n\nSciMark2-C (ANSI C), FreeBench/neural, and tramp3d-v4\nwere used as representative numerical workloads.\n\nFor tramp3d-v4, the workload parameters (--cartvis 1.0 0.0, --rhomin 1e-8,\n-n 20) increase floating-point intensity and dependency pressure, placing\ngreater stress on the scheduler.\n\n2026-02-13 Nikola Ratkovac <Nikola.Ratkovac@rt-rk.com>\n\ngcc/ChangeLog:\n\n * config/riscv/spacemit-x60.md: Add primary vector pipeline model\n for Spacemit-X60.\n (spacemit_x60_dummy): Rename from spacemi6_x60_dummy.\n * config/riscv/riscv.cc (riscv_sched_adjust_cost): Support spacemit_x60.\n (riscv_override_options_internal): Enable TARGET_ADJUST_LMUL_COST\n for spacemit_x60.\n\n\n\nCONFIDENTIALITY: The contents of this e-mail are confidential and intended only for the above addressee(s). If you are not the intended recipient, or the person responsible for delivering it to the intended recipient, copying or delivering it to anyone else or using it in any unauthorized manner is prohibited and may be unlawful. If you receive this e-mail by mistake, please notify the sender and the systems administrator at straymail@rt-rk.com immediately.\n---\n gcc/config/riscv/riscv.cc | 11 +-\n gcc/config/riscv/spacemit-x60.md | 233 ++++++++++++++++++++++++++++++-\n 2 files changed, 234 insertions(+), 10 deletions(-)", "diff": "diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 3baf0a936..8fd4c8ced 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -11842,9 +11842,12 @@ static int\n riscv_sched_adjust_cost (rtx_insn *, int, rtx_insn *insn, int cost,\n \t\t\t unsigned int)\n {\n- /* Only do adjustments for the generic out-of-order scheduling model. */\n- if (!TARGET_VECTOR || riscv_microarchitecture != generic_ooo)\n- return cost;\n+\n+ /* Only do adjustments for the generic out-of-order and spacemit_x60\n+ scheduling model. */\n+ if (!TARGET_VECTOR || (riscv_microarchitecture != generic_ooo\n+ && riscv_microarchitecture != spacemit_x60))\n+ return cost;\n \n if (recog_memoized (insn) < 0)\n return cost;\n@@ -12284,6 +12287,8 @@ riscv_override_options_internal (struct gcc_options *opts)\n const char *tune_string = get_tune_str (opts);\n cpu = riscv_parse_tune (tune_string, false);\n riscv_microarchitecture = cpu->microarchitecture;\n+ if (riscv_microarchitecture == spacemit_x60)\n+ opts->x_TARGET_ADJUST_LMUL_COST = 1;\n tune_param = opts->x_optimize_size\n \t\t ? &optimize_size_tune_info\n \t\t : cpu->tune_param;\ndiff --git a/gcc/config/riscv/spacemit-x60.md b/gcc/config/riscv/spacemit-x60.md\nindex fdd7b87b3..6f9d48928 100644\n--- a/gcc/config/riscv/spacemit-x60.md\n+++ b/gcc/config/riscv/spacemit-x60.md\n@@ -26,10 +26,9 @@\n ;; There's actually two VXU units and ops get split across them\n ;; to give the illusion of a single wider unit with higher \n ;; performance. There are a few ops that can only be fed into\n-;; one of the two units. Probably best to initially model as\n-;; a single unit\n+;; one of the two units. For the purposes of this scheduling\n+;; model, the VXU is treated as a single unit.\n ;;\n-;; The VXU is not currently modeled.\n ;; Some ops like shadd.uw and add.uw, cpop take an extra cycle\n ;; Given everything is in-order, anti-dependencies probably matter\n ;; FP sign injection isn't handled correctly\n@@ -38,7 +37,7 @@\n (define_automaton \"spacemit_x60\")\n (define_cpu_unit \"spacemit_x60_alu0,spacemit_x60_alu1\" \"spacemit_x60\")\n (define_cpu_unit \"spacemit_x60_lsu0,spacemit_x60_lsu1\" \"spacemit_x60\")\n-;;(define_cpu_unit \"spacemit_x60_vxu0\" \"spacemit_x60\")\n+(define_cpu_unit \"spacemit_x60_vxu0\" \"spacemit_x60\")\n (define_cpu_unit \"spacemit_x60_fpalu\" \"spacemit_x60\")\n (define_cpu_unit \"spacemit_x60_fdivsqrt\" \"spacemit_x60\")\n \n@@ -183,8 +182,228 @@\n \t (eq_attr \"mode\" \"DF\")))\n \"spacemit_x60_fdivsqrt*7\")\n \n-(define_insn_reservation \"spacemi6_x60_dummy\" 1\n+;; ----------------------------------------------------\n+;; Vector\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_vsetvl\" 1\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vsetvl_pre,vsetvl,rdvlenb,rdvl\"))\n+ \"spacemit_x60_vxu0\")\n+\n+;; ----------------------------------------------------\n+;; Vector Memory (load/store)\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_vec_load\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vlde,vldr,vldff\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_store\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vste,vstr,vstm\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_mask_load\" 1\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vldm\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_strided\" 10\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vlds,vsts\"))\n+ \"spacemit_x60_vxu0*7\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_indexed\" 10\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vldux,vldox,vstux,vstox,\\\n+ vlsegdux,vlsegdox,vssegtux,vssegtox\"))\n+ \"spacemit_x60_vxu0*7\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_segmented\" 8\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vlsegde,vlsegds,vlsegdff,vssegte,vssegts\"))\n+ \"spacemit_x60_vxu0*7\")\n+\n+;; ----------------------------------------------------\n+;; Vector Integer Arithmetic\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_vec_ialu\" 1\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vialu,vicalu,viminmax,vbrev,vext,\\\n+ vbrev8,vclz,vctz,vcpop,vrol,vror,vandn\"))\n+ \"spacemit_x60_vxu0\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_shift\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vshift\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_sshift\" 1\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vsshift\"))\n+ \"spacemit_x60_vxu0\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_cmp\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vicmp\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_imul\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vimul\"))\n+ \"spacemit_x60_vxu0\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_imuladd\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vimuladd\"))\n+ \"spacemit_x60_vxu0\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_iwalu\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"viwalu,viwmul,viwmuladd,vwsll\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_div\" 12\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vidiv\"))\n+ \"spacemit_x60_vxu0*7\")\n+\n+;; ----------------------------------------------------\n+;; Vector Fixed Point\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_vec_fixed_point\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vsalu,vaalu\"))\n+ \"spacemit_x60_vxu0\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_fixed_point_slow\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vsmul\"))\n+ \"spacemit_x60_vxu0*4\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_narrow_fixed_point\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vnshift,vnclip\"))\n+ \"spacemit_x60_vxu0*4\")\n+\n+;; ----------------------------------------------------\n+;; Vector Floating Point\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_vec_falu\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vfalu,vfmul,vfmuladd,vfminmax,vfrecp,\\\n+ vfcvtitof,vfcvtftoi,vfmerge\"))\n+ \"spacemit_x60_vxu0\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_fwalu\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vfwalu,vfwmul,vfwmuladd,vfwmaccbf16,vfwcvtitof,\\\n+ vfwcvtftoi,vfwcvtftof,vfwcvtbf16,vfncvtitof,vfncvtftoi,vfncvtftof,\\\n+ vfncvtbf16,sf_vfnrclip,sf_vqmacc\"))\n+ \"spacemit_x60_vxu0*4\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_fcmp\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vfcmp\"))\n+ \"spacemit_x60_vxu0\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_fmov\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vfmovfv,vfmov\"))\n+ \"spacemit_x60_vxu0*4\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_fsimple\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vfmovvf,vfclass,vfsgnj\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_fsqrt_fdiv\" 12\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vfsqrt,vfdiv\"))\n+ \"spacemit_x60_vxu0*7\")\n+\n+;; ----------------------------------------------------\n+;; Vector Mask Operations\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_vec_mask_alu\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vmalu\"))\n+ \"spacemit_x60_vxu0\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_mask_pop\" 6\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vmpop,vmffs\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_mask_special\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vmidx,vmiota\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_mask_vmsfs\" 4\n (and (eq_attr \"tune\" \"spacemit_x60\")\n- (eq_attr \"type\" \"viminmax,vfmuladd,vfmovvf,vssegte,vlsegds,rdvlenb,vaesef,vfcmp,vmpop,vwsll,vsha2cl,vfwcvtbf16,vfncvtftoi,vgather,vsha2ch,vsts,vldm,vmsfs,vfmul,vcompress,vaesz,vssegtox,vstox,vclmulh,vghsh,vaalu,vslideup,vfalu,vaeskf1,vfcvtitof,vaesdm,vmffs,vandn,vstm,vgmul,vlds,viwmul,vfmerge,vlsegdff,vshift,vaesem,vaesdf,vste,ghost,viwred,vsalu,vfwredu,vmidx,sf_vfnrclip,vstux,vfslide1down,vfcvtftoi,vfncvtitof,vnshift,vsm3me,vired,vlde,vfwalu,sf_vc_se,vlsegdux,vicmp,vfncvtftof,vror,vfwmaccbf16,vfminmax,vldff,vstr,vsm3c,vfwcvtftoi,vbrev,vaeskf2,vidiv,vfwcvtftof,rdvl,vimul,vfsgnj,vimovvx,vsha2ms,vialu,vfredo,vctz,vlsegde,viwmuladd,vcpop,vsetvl,vldux,vfwmuladd,vector,wrvxrm,vsshift,vfredu,vimerge,vlsegdox,vfrecp,vnclip,vfclass,vbrev8,vslidedown,vldox,vmalu,vext,vimuladd,sf_vqmacc,vldr,vrol,vmov,vsmul,vclmul,vfmov,vislide1up,vssegtux,vclz,rdfrm,vfwcvtitof,vfncvtbf16,vfmovfv,vislide1down,vfwmul,vfsqrt,vrev8,vicalu,vimov,wrfrm,vfdiv,sf_vc,vsm4k,vmiota,vsm4r,viwalu,vsetvl_pre,vimovxv,vfwredo,vfslide1up,vssegts\"))\n- \"nothing\")\n+ (eq_attr \"type\" \"vmsfs\"))\n+ \"spacemit_x60_vxu0\")\n \n+;; ----------------------------------------------------\n+;; Vector Permutations\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_vec_mov\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vmov,vimovxv,vimovvx,vimov\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_merge\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vimerge\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_gather\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vgather\"))\n+ \"spacemit_x60_vxu0*4\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_compress\" 4\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vcompress\"))\n+ \"spacemit_x60_vxu0*3\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_slide\" 2\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vslideup,vslidedown,vislide1up,\\\n+ vislide1down,vfslide1up,vfslide1down\"))\n+ \"spacemit_x60_vxu0\")\n+\n+;; ----------------------------------------------------\n+;; Vector Reductions\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_vec_red\" 8\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vired,viwred,vfredu,vfwredu\"))\n+ \"spacemit_x60_vxu0*2\")\n+\n+(define_insn_reservation \"spacemit_x60_vec_ordered_red\" 10\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vfredo,vfwredo\"))\n+ \"spacemit_x60_vxu0*7\")\n+\n+;; ----------------------------------------------------\n+;; Vector Unknown\n+;; ----------------------------------------------------\n+\n+(define_insn_reservation \"spacemit_x60_dummy\" 1\n+ (and (eq_attr \"tune\" \"spacemit_x60\")\n+ (eq_attr \"type\" \"vaesef,\n+ vsha2cl,vsha2ch,vaesz,vclmulh,vghsh,vaeskf1,vaesdm,vgmul,\n+ vaesem,vaesdf,ghost,vsm3me,sf_vc_se,vsm3c,\n+ vaeskf2,vsha2ms,vector,wrvxrm,\n+ vclmul,rdfrm,wrfrm,sf_vc,vsm4k,vsm4r\"))\n+ \"nothing\")\n\\ No newline at end of file\n", "prefixes": [ "v2" ] }