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GET /api/patches/2196338/?format=api
{ "id": 2196338, "url": "http://patchwork.ozlabs.org/api/patches/2196338/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260213084956.1031000-7-brian.ruley@gehealthcare.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260213084956.1031000-7-brian.ruley@gehealthcare.com>", "list_archive_url": null, "date": "2026-02-13T08:49:55", "name": "[v3,6/6] video: imx: ipuv3: use clock framework", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "93d507667500c3ea4ce29e7ece8e8952e8272eba", "submitter": { "id": 89422, "url": "http://patchwork.ozlabs.org/api/people/89422/?format=api", "name": "Brian Ruley", "email": "brian.ruley@gehealthcare.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260213084956.1031000-7-brian.ruley@gehealthcare.com/mbox/", "series": [ { "id": 492095, "url": "http://patchwork.ozlabs.org/api/series/492095/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=492095", "date": "2026-02-13T08:49:49", "name": "Enable the IPUv3 driver to use CCF", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/492095/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196338/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196338/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gehealthcare.com header.i=@gehealthcare.com\n header.a=rsa-sha256 header.s=selector1 header.b=xToDhIsX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Ip=[165.85.157.49];\n Helo=[mkerelay1.compute.ge-healthcare.net]", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "\n TreatMessagesAsInternal-CH1PEPF0000AD75.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "EA2PR22MB4730", "X-Mailman-Approved-At": "Fri, 13 Feb 2026 14:24:08 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Clocks are now configurable via the common clock framework, however,\nusers have the option use the legacy clocks if desired. The intent is to\nkeep the changes minimal for this old SoC.\n\nSigned-off-by: Brian Ruley <brian.ruley@gehealthcare.com>\n---\n\n(no changes since v2)\n\nChanges in v2:\n- Removed DEBUG define that was missed\n\n drivers/video/imx/ipu_common.c | 75 +++++++++++++---\n drivers/video/imx/ipu_disp.c | 142 +++++++++++++++++++++++++------\n drivers/video/imx/mxc_ipuv3_fb.c | 17 ++++\n 3 files changed, 196 insertions(+), 38 deletions(-)", "diff": "diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c\nindex d994053394f..8630374a055 100644\n--- a/drivers/video/imx/ipu_common.c\n+++ b/drivers/video/imx/ipu_common.c\n@@ -101,7 +101,18 @@ struct ipu_ch_param {\n */\n static int ipu_clk_init(struct ipu_ctx *ctx)\n {\n+#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n \treturn ipu_clk_init_legacy(ctx);\n+#else\n+\tstruct clk *clk;\n+\n+\tclk = devm_clk_get(ctx->dev, \"bus\");\n+\tif (IS_ERR(clk))\n+\t\treturn PTR_ERR(clk);\n+\n+\tctx->ipu_clk = clk;\n+\treturn 0;\n+#endif\n }\n \n /*\n@@ -113,7 +124,13 @@ static int ipu_clk_init(struct ipu_ctx *ctx)\n */\n static int ipu_ldb_clk_init(struct ipu_ctx *ctx)\n {\n+#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n \treturn ipu_ldb_clk_init_legacy(ctx);\n+#else\n+\t/* Set this in the FB driver where we know the display id */\n+\tctx->ldb_clk = NULL;\n+\treturn 0;\n+#endif\n }\n \n /* Static functions */\n@@ -150,6 +167,29 @@ static inline void ipu_ch_param_set_buffer(u32 ch, int buf_num,\n #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)\n #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))\n \n+/*\n+ * Function to initialize the display clocks\n+ *\n+ * @param ctx\t The ipu context for which the function is called\n+ *\n+ * Return: Returns 0 on success or negative error code on error\n+ */\n+static int ipu_di_clk_init(struct ipu_ctx *ctx, int id)\n+{\n+#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n+\tctx->di_clk[id] = NULL;\n+\treturn 0;\n+#else\n+\tstruct clk *clk;\n+\n+\tclk = devm_clk_get(ctx->dev, id ? \"di1\" : \"di0\");\n+\tif (IS_ERR(clk))\n+\t\treturn PTR_ERR(clk);\n+\n+\tctx->di_clk[id] = clk;\n+\treturn 0;\n+#endif\n+}\n /*\n * Function to initialize the pixel clock\n *\n@@ -159,7 +199,12 @@ static inline void ipu_ch_param_set_buffer(u32 ch, int buf_num,\n */\n static int ipu_pixel_clk_init(struct ipu_ctx *ctx, int id)\n {\n+#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n \treturn ipu_pixel_clk_init_legacy(ctx, id);\n+#else\n+\tctx->pixel_clk[id] = ctx->ipu_clk;\n+\treturn 0;\n+#endif\n }\n \n /*\n@@ -230,33 +275,39 @@ struct ipu_ctx *ipu_probe(struct udevice *dev)\n \tipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);\n \tipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);\n \n-\tret = ipu_pixel_clk_init(ctx, 0);\n-\tif (ret)\n-\t\tgoto err;\n-\n-\tret = ipu_pixel_clk_init(ctx, 1);\n-\tif (ret)\n-\t\tgoto err;\n+\tfor (int i = 0; i <= 1; i++) {\n+\t\tret = ipu_pixel_clk_init(ctx, i);\n+\t\tif (ret)\n+\t\t\tgoto err;\n+\t}\n \n \tret = ipu_clk_init(ctx);\n \tif (ret)\n \t\tgoto err;\n \n-\tdebug(\"ipu_clk = %u\\n\", clk_get_rate(ctx->ipu_clk));\n+\tdebug(\"ipu_clk = %lu\\n\", (ulong)clk_get_rate(ctx->ipu_clk));\n \n \tret = ipu_ldb_clk_init(ctx);\n \tif (ret)\n \t\tgoto err;\n \n-\tdebug(\"ldb_clk = %u\\n\", clk_get_rate(ctx->ldb_clk));\n+\tif (ctx->ldb_clk)\n+\t\tdebug(\"ldb_clk = %lu\\n\", (ulong)clk_get_rate(ctx->ldb_clk));\n+\n \tipu_reset();\n \n+#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n \tclk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk);\n \tclk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk);\n+\n \tclk_enable(ctx->ipu_clk);\n+#endif\n \n-\tctx->di_clk[0] = NULL;\n-\tctx->di_clk[1] = NULL;\n+\tfor (int i = 0; i <= 1; i++) {\n+\t\tret = ipu_di_clk_init(ctx, i);\n+\t\tif (ret)\n+\t\t\tgoto err;\n+\t}\n \n \t__raw_writel(0x807FFFFF, IPU_MEM_RST);\n \twhile (__raw_readl(IPU_MEM_RST) & 0x80000000)\n@@ -278,7 +329,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev)\n \t/* Set MCU_T to divide MCU access window into 2 */\n \t__raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);\n \n+#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n \tclk_disable(ctx->ipu_clk);\n+#endif\n \n \treturn ctx;\n err:\ndiff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c\nindex 6a337b13af6..5e78574da9b 100644\n--- a/drivers/video/imx/ipu_disp.c\n+++ b/drivers/video/imx/ipu_disp.c\n@@ -612,6 +612,11 @@ void ipu_dp_dc_enable(struct ipu_ctx *ctx, ipu_channel_t channel)\n \t__raw_writel(reg, DC_WR_CH_CONF(dc_chan));\n \n \tclk_enable(ctx->pixel_clk[di]);\n+#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n+\treg = __raw_readl(IPU_DISP_GEN);\n+\treg |= di ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;\n+\t__raw_writel(reg, IPU_DISP_GEN);\n+#endif\n }\n \n static unsigned char dc_swap;\n@@ -702,6 +707,12 @@ void ipu_dp_dc_disable(struct ipu_ctx *ctx, ipu_channel_t channel,\n \n \t\t/* Clock is already off because it must be done quickly, but\n \t\t we need to fix the ref count */\n+#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n+\t\treg = __raw_readl(IPU_DISP_GEN);\n+\t\treg &= ctx->dc_di_assignment[dc_chan] ? ~DI1_COUNTER_RELEASE :\n+\t\t\t\t\t\t\t~DI0_COUNTER_RELEASE;\n+\t\t__raw_writel(reg, IPU_DISP_GEN);\n+#endif\n \t\tclk_disable(ctx->pixel_clk[ctx->dc_di_assignment[dc_chan]]);\n \t}\n }\n@@ -765,40 +776,21 @@ static int ipu_pixfmt_to_map(u32 fmt)\n *\n * @param\tsig\tBitfield of signal polarities for LCD interface.\n *\n- * Return:\tThis function returns 0 on success or negative error code on\n- *\t\tfail.\n+ * Return:\tThe integer portion of the divider set for the pixel clock.\n */\n-\n-int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig)\n+static u32 ipu_di_clk_config(struct ipu_di_config *di, ipu_di_signal_cfg_t sig)\n {\n \tstruct ipu_ctx *ctx = di->ctx;\n \tint disp = di->disp;\n-\tu32 reg;\n-\tu32 di_gen, vsync_cnt;\n-\tu32 div, rounded_pixel_clk;\n-\tu32 h_total, v_total;\n-\tint map;\n-\tstruct clk *di_parent;\n-\n-\tdebug(\"panel size = %d x %d\\n\", di->width, di->height);\n-\n-\tif ((di->v_sync_width == 0) || (di->h_sync_width == 0))\n-\t\treturn -EINVAL;\n-\n-\t/* adapt panel to ipu restricitions */\n-\tif (di->v_end_width < 2) {\n-\t\tdi->v_end_width = 2;\n-\t\tputs(\"WARNING: v_end_width (lower_margin) must be >= 2, adjusted\\n\");\n-\t}\n-\n-\th_total = di->width + di->h_sync_width + di->h_start_width +\n-\t\t di->h_end_width;\n-\tv_total = di->height + di->v_sync_width + di->v_start_width +\n-\t\t di->v_end_width;\n+\tu32 div;\n \n \t/* Init clocking */\n \tdebug(\"pixel clk = %dHz\\n\", di->pixel_clk_rate);\n \n+#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n+\tu32 rounded_pixel_clk;\n+\tstruct clk *di_parent;\n+\n \tif (sig.ext_clk) {\n \t\tif (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/\n \t\t\t/*\n@@ -830,13 +822,109 @@ int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig)\n \t\tif (clk_get_usecount(ctx->pixel_clk[disp]) != 0)\n \t\t\tclk_set_parent(ctx->pixel_clk[disp], ctx->ipu_clk);\n \t}\n+\n \trounded_pixel_clk =\n \t\tclk_round_rate(ctx->pixel_clk[disp], di->pixel_clk_rate);\n \tclk_set_rate(ctx->pixel_clk[disp], rounded_pixel_clk);\n-\tudelay(5000);\n+\n \t/* Get integer portion of divider */\n \tdiv = clk_get_rate(clk_get_parent(ctx->pixel_clk[disp])) /\n \t rounded_pixel_clk;\n+#else\n+\tstruct clk *clk;\n+\tu32 clkgen0, di_gen;\n+\tulong id;\n+\n+\tif (sig.ext_clk) {\n+\t\t/*\n+\t\t * Bypass the divider, assuming synchronous mode\n+\t\t */\n+\t\tclk = ctx->di_clk[disp];\n+\t\tdiv = 1;\n+\t} else {\n+\n+\t\tulong clk_rate = clk_get_rate(ctx->ipu_clk);\n+\t\tu32 error;\n+\n+\t\tdiv = DIV_ROUND_CLOSEST(clk_rate, di->pixel_clk_rate);\n+\t\tdiv = clamp(div, 1U, 255U);\n+\n+\t\terror = (clk_rate / div) / (di->pixel_clk_rate / 1000);\n+\n+\t\t/*\n+ * Select IPU if the rate is within 1% of requested pixel\n+ * clock, otherwise, use the DI clock\n+ */\n+\t\tif (990 <= error && error < 1010) {\n+\t\t\tclk = ctx->ipu_clk;\n+\t\t} else {\n+\t\t\tclk = ctx->di_clk[disp];\n+\n+\t\t\tclk_set_rate(clk, di->pixel_clk_rate);\n+\t\t\tdiv = DIV_ROUND_CLOSEST(clk_get_rate(clk),\n+\t\t\t\t\t\tdi->pixel_clk_rate);\n+\t\t\tdiv = clamp(div, 1U, 255U);\n+\t\t}\n+\t}\n+\n+\tclkgen0 = div << 4;\n+\n+\tctx->pixel_clk[disp] = clk;\n+\tdebug(\"new pixel rate: %lu Hz\\n\", clk_get_rate(clk));\n+\n+\tid = clk_get_id(clk);\n+\t__raw_writel(clkgen0, DI_BS_CLKGEN0(id));\n+\t__raw_writel((clkgen0 & 0xFFF0) << 12, DI_BS_CLKGEN1(id));\n+\n+\tdi_gen = __raw_readl(DI_GENERAL(id)) & ~DI_GEN_DI_CLK_EXT;\n+\tif (clk == ctx->di_clk[disp])\n+\t\tdi_gen |= DI_GEN_DI_CLK_EXT;\n+\n+\t__raw_writel(di_gen, DI_GENERAL(id));\n+#endif\n+\n+\tudelay(5000);\n+\treturn div;\n+}\n+\n+/*\n+ * This function is called to initialize a synchronous LCD panel.\n+ *\n+ * @param\tdi\tPointer to display data.\n+ *\n+ * @param\tsig\tBitfield of signal polarities for LCD interface.\n+ *\n+ * Return:\tThis function returns 0 on success or negative error code on\n+ *\t\tfail.\n+ */\n+int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig)\n+{\n+\tint disp = di->disp;\n+\tu32 reg;\n+\tu32 di_gen, vsync_cnt;\n+\tu32 div;\n+\tu32 h_total, v_total;\n+\tint map;\n+\n+\tdebug(\"panel size = %d x %d\\n\", di->width, di->height);\n+\n+\tif ((di->v_sync_width == 0) || (di->h_sync_width == 0))\n+\t\treturn -EINVAL;\n+\n+\t/* adapt panel to ipu restricitions */\n+\tif (di->v_end_width < 2) {\n+\t\tdi->v_end_width = 2;\n+\t\tputs(\"WARNING: v_end_width (lower_margin) must be >= 2, adjusted\\n\");\n+\t}\n+\n+\th_total = di->width + di->h_sync_width + di->h_start_width +\n+\t\t di->h_end_width;\n+\tv_total = di->height + di->v_sync_width + di->v_start_width +\n+\t\t di->v_end_width;\n+\n+\tdiv = ipu_di_clk_config(di, sig);\n+\tif (div < 0)\n+\t\treturn div;\n \n \tipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);\n \tipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);\ndiff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c\nindex ab416fdd33c..cfc34972ad1 100644\n--- a/drivers/video/imx/mxc_ipuv3_fb.c\n+++ b/drivers/video/imx/mxc_ipuv3_fb.c\n@@ -36,6 +36,7 @@\n #include <dm.h>\n #include <dm/devres.h>\n #include <video.h>\n+#include <dt-bindings/clock/imx6qdl-clock.h>\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -602,6 +603,22 @@ static int ipuv3_video_probe(struct udevice *dev)\n \tif (ret < 0)\n \t\treturn ret;\n \n+#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n+\tif (of_machine_is_compatible(\"fsl,imx6qp\"))\n+\t\tret = clk_get_by_id(gdisp ? IMX6QDL_CLK_LDB_DI1_PODF :\n+\t\t\t\t\t IMX6QDL_CLK_LDB_DI0_PODF,\n+\t\t\t\t &ctx->ldb_clk);\n+\telse\n+\t\tret = clk_get_by_id(gdisp ? IMX6QDL_CLK_LDB_DI1 :\n+\t\t\t\t\t IMX6QDL_CLK_LDB_DI0,\n+\t\t\t\t &ctx->ldb_clk);\n+\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tdebug(\"ldb_clk = %lu\\n\", clk_get_rate(ctx->ldb_clk));\n+#endif\n+\n \tret = mxcfb_probe(dev, gpixfmt, gdisp, gmode);\n \tif (ret < 0)\n \t\treturn ret;\n", "prefixes": [ "v3", "6/6" ] }