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GET /api/patches/2196310/?format=api
{ "id": 2196310, "url": "http://patchwork.ozlabs.org/api/patches/2196310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260213112717.1256823-4-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260213112717.1256823-4-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-13T11:27:14", "name": "[v2,3/6] misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f9f7c573e1ca8e41c18ead8f29f7da5395a80bea", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260213112717.1256823-4-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 492084, "url": "http://patchwork.ozlabs.org/api/series/492084/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=492084", "date": "2026-02-13T11:27:11", "name": "qcom: Add NVMEM bitfield support and reboot‑mode integration", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492084/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196310/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196310/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ImVd4hvE;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=fB+5Lt8m;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"ImVd4hvE\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"fB+5Lt8m\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fC8zq0cDbz1xr1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 13 Feb 2026 22:28:07 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id B0BF283DEC;\n\tFri, 13 Feb 2026 12:28:00 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 9DAA483DE4; Fri, 13 Feb 2026 12:27:59 +0100 (CET)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 1B2FC83CBD\n for <u-boot@lists.denx.de>; Fri, 13 Feb 2026 12:27:56 +0100 (CET)", "from pps.filterd (m0279868.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 61D7MuuC2628874\n for <u-boot@lists.denx.de>; Fri, 13 Feb 2026 11:27:55 GMT", "from mail-pl1-f199.google.com (mail-pl1-f199.google.com\n [209.85.214.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c9ygurvrf-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Fri, 13 Feb 2026 11:27:55 +0000 (GMT)", "by mail-pl1-f199.google.com with SMTP id\n d9443c01a7336-2aaf0dbd073so9767055ad.3\n for <u-boot@lists.denx.de>; Fri, 13 Feb 2026 03:27:55 -0800 (PST)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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neil.armstrong@linaro.org, peng.fan@nxp.com, quentin.schulz@cherry.de,\n n-francis@ti.com, xypron.glpk@gmx.de, h-vm@ti.com, justin@tidylabs.net,\n jamie.gibbons@microchip.com, ycliang@andestech.com, me@samcday.com,\n sughosh.ganu@arm.com, gchan9527@gmail.com, ilias.apalodimas@linaro.org,\n Aswin Murugan <aswin.murugan@oss.qualcomm.com>", "Subject": "[PATCH v2 3/6] misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver", "Date": "Fri, 13 Feb 2026 16:57:14 +0530", "Message-Id": "<20260213112717.1256823-4-aswin.murugan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260213112717.1256823-1-aswin.murugan@oss.qualcomm.com>", "References": "<20260213112717.1256823-1-aswin.murugan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "_Olh7lwbWZI9NyRRXPDKuVkSPTciQb4p", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEzMDA4NyBTYWx0ZWRfX/oEmzf6KLFDT\n fRbga/ie+sgPZs3IrSvx/Vs7NpZRft5dBlZ24T/ULeE52pmYpjuRvak//SuEqC6IuAEKrwPUCsf\n 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"X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 adultscore=0 bulkscore=0 clxscore=1015 suspectscore=0\n impostorscore=0 phishscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602130087", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Qualcomm PMICs include SDAM (Shared Direct Access Memory) regions which\nare used to store persistent data like reboot reasons that must survive\nacross reboots.\n\nWithout this driver, U-Boot cannot access PMIC storage, preventing\nreboot-to-bootloader functionality and other features that rely on\npersistent state.\n\nAdd qcom-spmi-sdam driver that:\n- Probes SDAM regions from device tree compatible \"qcom,spmi-sdam\"\n- Implements NVMEM provider interface for standard cell-based access\n- Uses SPMI register read/write operations for data access\n\nThis enables reboot-mode and other subsystems to access PMIC storage\nthrough standard NVMEM APIs.\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n---\n drivers/misc/Kconfig | 8 ++\n drivers/misc/Makefile | 1 +\n drivers/misc/qcom-spmi-sdam.c | 200 ++++++++++++++++++++++++++++++++++\n 3 files changed, 209 insertions(+)\n create mode 100644 drivers/misc/qcom-spmi-sdam.c", "diff": "diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig\nindex a0aa290480e..8ace19c1128 100644\n--- a/drivers/misc/Kconfig\n+++ b/drivers/misc/Kconfig\n@@ -92,6 +92,14 @@ config QCOM_GENI\n \t for providing a common interface for various peripherals like UART, I2C, SPI,\n \t etc.\n \n+config QCOM_SPMI_SDAM\n+\tbool \"Qualcomm SPMI SDAM NVMEM driver\"\n+\tdepends on MISC && NVMEM && SPMI\n+\thelp\n+\t Enable support for Qualcomm SPMI SDAM (Shared Direct Access Memory) blocks\n+\t as NVMEM providers. This driver support accessing SDAM blocks in PMICs\n+\t for reboot reason functionality and other NVMEM use cases.\n+\n config ROCKCHIP_EFUSE\n bool \"Rockchip e-fuse support\"\n \tdepends on MISC\ndiff --git a/drivers/misc/Makefile b/drivers/misc/Makefile\nindex 1d950f7a0ab..bed2cb63fcb 100644\n--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -68,6 +68,7 @@ obj-$(CONFIG_QFW_SMBIOS) += qfw_smbios.o\n obj-$(CONFIG_SANDBOX) += qfw_sandbox.o\n endif\n obj-$(CONFIG_QCOM_GENI) += qcom_geni.o\n+obj-$(CONFIG_QCOM_SPMI_SDAM) += qcom-spmi-sdam.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_EFUSE) += rockchip-efuse.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_OTP) += rockchip-otp.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o\ndiff --git a/drivers/misc/qcom-spmi-sdam.c b/drivers/misc/qcom-spmi-sdam.c\nnew file mode 100644\nindex 00000000000..482156f3bb7\n--- /dev/null\n+++ b/drivers/misc/qcom-spmi-sdam.c\n@@ -0,0 +1,200 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Qualcomm SPMI SDAM NVMEM driver\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <dm.h>\n+#include <misc.h>\n+#include <dm/device_compat.h>\n+#include <dm/uclass.h>\n+#include <spmi/spmi.h>\n+\n+#define PID_SHIFT 8\n+#define PID_MASK (0xFF << PID_SHIFT)\n+#define REG_MASK 0xFF\n+#define SDAM_SIZE 0x100\n+\n+struct qcom_sdam_priv {\n+\tu32 base;\n+\tu32 size;\n+\tu32 pmic_usid;\n+\tstruct udevice *spmi_dev;\n+};\n+\n+/**\n+ * qcom_sdam_find_spmi_pmic() - Find SPMI controller and PMIC USID\n+ * @dev: SDAM device\n+ * @spmi_dev: Returns SPMI controller device\n+ * @pmic_usid: Returns PMIC USID for SPMI access\n+ *\n+ * Walks up the device tree to find the PMIC parent and SPMI controller.\n+ * Supports both direct SDAM under PMIC and virtual NVMEM under PON.\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int qcom_sdam_find_spmi_pmic(struct udevice *dev,\n+\t\t\t\t struct udevice **spmi_dev,\n+\t\t\t\t u32 *pmic_usid)\n+{\n+\tstruct udevice *pmic_dev = dev->parent;\n+\tint ret;\n+\n+\tif (!pmic_dev) {\n+\t\tdev_err(dev, \"No parent device found\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = dev_read_u32_index(pmic_dev, \"reg\", 0, pmic_usid);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Could not read PMIC USID: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t*spmi_dev = pmic_dev->parent;\n+\tif (!*spmi_dev || (*spmi_dev)->uclass->uc_drv->id != UCLASS_SPMI) {\n+\t\tdev_err(dev, \"Could not find SPMI controller\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdev_dbg(dev, \"Found PMIC USID=%d, SPMI controller=%s\\n\",\n+\t\t*pmic_usid, (*spmi_dev)->name);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * qcom_sdam_read() - Read data from SDAM/NVMEM region\n+ * @dev: MISC device (SDAM)\n+ * @offset: Offset within SDAM/NVMEM region\n+ * @buf: Buffer to read data into\n+ * @size: Number of bytes to read\n+ *\n+ * Uses the same SPMI register access pattern as pmic_qcom.c driver\n+ * for consistency and reliability. This function is called by the\n+ * NVMEM subsystem via misc_read().\n+ *\n+ * Return: number of bytes read on success, negative error code on failure\n+ */\n+static int qcom_sdam_read(struct udevice *dev, int offset,\n+\t\t\t void *buf, int size)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tu8 *buffer = buf;\n+\tint ret;\n+\n+\tif (offset + size > priv->size)\n+\t\treturn -EINVAL;\n+\n+\tfor (size_t i = 0; i < size; i++) {\n+\t\tu32 reg = priv->base + offset + i;\n+\n+\t\tret = spmi_reg_read(priv->spmi_dev, priv->pmic_usid,\n+\t\t\t\t (reg & PID_MASK) >> PID_SHIFT,\n+\t\t\t\t reg & REG_MASK);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(dev, \"SPMI read failed at 0x%x: %d\\n\", reg, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tbuffer[i] = ret;\n+\n+\t\tdev_dbg(dev, \"Read 0x%02x from 0x%x (PID=0x%02x REG=0x%02x)\\n\",\n+\t\t\tbuffer[i], reg, (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK);\n+\t}\n+\n+\treturn size;\n+}\n+\n+/**\n+ * qcom_sdam_write() - Write data to SDAM/NVMEM region\n+ * @dev: MISC device (SDAM)\n+ * @offset: Offset within SDAM/NVMEM region\n+ * @buf: Buffer containing data to write\n+ * @size: Number of bytes to write\n+ *\n+ * Uses the same SPMI register access pattern as pmic_qcom.c driver\n+ * for consistency and reliability. This function is called by the\n+ * NVMEM subsystem via misc_write().\n+ *\n+ * Return: number of bytes written on success, negative error code on failure\n+ */\n+static int qcom_sdam_write(struct udevice *dev, int offset,\n+\t\t\t const void *buf, int size)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tconst u8 *buffer = buf;\n+\tint ret;\n+\n+\tif (offset + size > priv->size)\n+\t\treturn -EINVAL;\n+\n+\tfor (size_t i = 0; i < size; i++) {\n+\t\tu32 reg = priv->base + offset + i;\n+\n+\t\tret = spmi_reg_write(priv->spmi_dev, priv->pmic_usid,\n+\t\t\t\t (reg & PID_MASK) >> PID_SHIFT,\n+\t\t\t\t reg & REG_MASK,\n+\t\t\t\t buffer[i]);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(dev, \"SPMI write failed at 0x%x: %d\\n\", reg, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tdev_dbg(dev, \"Wrote 0x%02x to 0x%x (PID=0x%02x REG=0x%02x)\\n\",\n+\t\t\tbuffer[i], reg, (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK);\n+\t}\n+\n+\treturn size;\n+}\n+\n+static const struct misc_ops qcom_sdam_ops = {\n+\t.read = qcom_sdam_read,\n+\t.write = qcom_sdam_write,\n+};\n+\n+/**\n+ * qcom_sdam_probe() - Probe SDAM device and register as NVMEM provider\n+ * @dev: SDAM device\n+ *\n+ * Handles both real SDAM blocks and virtual NVMEM under PON blocks.\n+ * For virtual NVMEM, adds the parent PON base address to the offset.\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int qcom_sdam_probe(struct udevice *dev)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\tpriv->base = dev_read_addr(dev);\n+\tif (priv->base == FDT_ADDR_T_NONE) {\n+\t\tdev_err(dev, \"Could not read base address\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpriv->size = dev_read_u32_default(dev, \"qcom,sdam-size\", SDAM_SIZE);\n+\n+\tret = qcom_sdam_find_spmi_pmic(dev, &priv->spmi_dev, &priv->pmic_usid);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdev_info(dev, \"SDAM base=0x%x size=0x%x PMIC_USID=%d\\n\",\n+\t\t priv->base, priv->size, priv->pmic_usid);\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id qcom_sdam_ids[] = {\n+\t{ .compatible = \"qcom,spmi-sdam\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(qcom_spmi_sdam) = {\n+\t.name = \"qcom-spmi-sdam\",\n+\t.id = UCLASS_MISC,\n+\t.of_match = qcom_sdam_ids,\n+\t.probe = qcom_sdam_probe,\n+\t.ops = &qcom_sdam_ops,\n+\t.priv_auto = sizeof(struct qcom_sdam_priv),\n+};\n", "prefixes": [ "v2", "3/6" ] }