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GET /api/patches/2196290/?format=api
{ "id": 2196290, "url": "http://patchwork.ozlabs.org/api/patches/2196290/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260213103942.142823-4-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260213103942.142823-4-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-02-13T10:39:40", "name": "[v6,3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated SMMUv3 devices", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "31529d80208deab51bc34f3ec6ff97cb2333d333", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260213103942.142823-4-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 492079, "url": "http://patchwork.ozlabs.org/api/series/492079/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492079", "date": "2026-02-13T10:39:41", "name": "vEVENTQ support for accelerated SMMUv3 devices", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/492079/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196290/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196290/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=YwvC0ITS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c10d::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=SN4PR2101CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <nicolinc@nvidia.com>, <nathanc@nvidia.com>, <mochs@nvidia.com>,\n <jan@nvidia.com>, <jgg@nvidia.com>, <jonathan.cameron@huawei.com>,\n <zhangfei.gao@linaro.org>, <zhenzhong.duan@intel.com>, <kjaju@nvidia.com>,\n <skolothumtho@nvidia.com>", "Subject": "[PATCH v6 3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated\n SMMUv3 devices", "Date": "Fri, 13 Feb 2026 10:39:40 +0000", "Message-ID": "<20260213103942.142823-4-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260213103942.142823-1-skolothumtho@nvidia.com>", "References": "<20260213103942.142823-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF0001AB4D:EE_|LV2PR12MB5726:EE_", "X-MS-Office365-Filtering-Correlation-Id": "eb10c562-1f94-4456-5b1f-08de6aecb17b", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|376014|1800799024|36860700013;", "X-Microsoft-Antispam-Message-Info": "\n N3zqDgeltrDpZRtN+Cu+BDjyRWGizg4hf3hdFPMFwlG3K4yPJzftWCYlTe5DYo5sxpxuRPZuODWITBHFxueePVVFnZ8s3c6EXFetXx+rXy2jejLOvLwsfzJVfWnJMfuXOnM+MoYu/qrlEzgEPC5YSsZbI8BSaPKd3vEZhSuj9weOPZLhaTeNNgWIp+dtj8L1IfCfEp01HArqSwr4N9NGmPaC9JriqEGA5BxBujlz7ppvgh5/y4cpGyYtgUNfaFDNfLVU/kj1T3a1rNejyB7HOTjPfXqt3lrHBkwveTqGLGwZhLsphgV83rb8oLtZzjp0K9oo4e/JSkLyPcW2HdEnkA3leTQqPAsech9yU9x8DDYs4hjoFNVyr9e3fxg9iCkvRuJj0k02QY2GkCp9w/H3i4KoWePH5QYS+YUofQkIENCPBqTAppsWpg9djHCIw8JmkLeql2hpOqV5VlpIAHu5JI4Cq1+Lvl1FHpfW3TU8HB9WdhoZGx30/lmBiqo0yXCV+LNxcKy84IWpHkng6XK3XuJ7VZBEe9S2T4vcjs4OEVYnQBLjkFPYGjGW1SlGORqyREYYRObZk00rUbUewUy8pBoFZCYHb+JJlgELSBMIu0xiMV1hARPMPtimrgIMqDta7WCsLTFa/3wONgGhm2lblLugoDteb//xz+0Gilsa+1yySpeNmgETDTUleN1gtDHyPpByyJGg9G37T325xMVwWIKr2UYQj4ncsAQycp54V2DMAE2w2XMUePpIRF9tZq7XrN1iMoYrHEuR3oD05hEbgaPzLf2sQ8QWrRwppYA/+0982KvCwzht3TpLEj/xPRIcUNRUk3pamzpfLAsS+cBWhPwqMMHnkU6pxduQbxNV6cCyuz15DyYZFm+vcW2Sn3OT2IZQyoFVQPLP3mlAWql7beIA/ezq12VqNLt0vSPCMZbl+IL0LJ52Ok/3KllBKyjiRFAa+rObEnAUkC1Nkl0qKGH6R9/ht4T47FEK8pAv31UN+jPWC8RlWzij9mtPTiG3yv3EkVDZ9KCW9wJEIgafN+qMcN7VIOA5+GbAnfkNeAlde+zr5WdQUXrh6h8DcwgFiFHBFr+a2EjmSjKShTjPi+3X3wvW90hjr098lWVVNvNf/hmbucKUpQeYYxzRWEWxOiqURcS7dlwyMJ7nEN+6TcRdjea4GzNUj2fzFRfozqHBZw2VVb3pNNTqluoBj5Aw4/fwOohO/ts3n7lJiG5eDDx7fAwe0LYDO5W3OJpmPzsTjU7LIHj7pm5AYGaEE8DjoFSy5xibGoOSx1euzovzakfQZxT8/7Kq0Z7L276xhBCdxUBJzJnropgZJFRKrYAa0qpl5/Tsu4PyDSRKt69ipl14k0KhvVTbEQ6oTtIugk//f602VlrmN/4ZqEOwR3xKnLoHzsVLoRn3+CX9lbxxZRclkEbYiJaGkLb1mDm7wx9MTxWzQqgzfrpxNnBK0XcK68Y9iWdIxawq2ALuKbdwoeXTh+37yZHGOaMXbjg0dkA5ACSfvMTznnT69IUcfoz6xEwH3eztFCvMmKDM/9MFvLa7iyPyte8fdSR2jAaacJyxZsN7XHbOnrGJNA1GK8AXurE8dW4f+EhgNyO3wHYmpoCCmaS/jRlYsSZWB3syeawgiJrlWkdvH+3nG8tBrroyYIBb6uUjWhIDCPsE6D4kqg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL6PEPF0001AB4D.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5726", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nWhen the guest enables the Event Queue and a vIOMMU is present, allocate a\nvEVENTQ object so that host-side events related to the vIOMMU can be\nreceived and propagated back to the guest.\n\nFor cold-plugged devices using SMMUv3 acceleration, the vIOMMU is created\nbefore the guest boots. In this case, the vEVENTQ is allocated when the\nguest writes to SMMU_CR0 and sets EVENTQEN = 1.\n\nIf no cold-plugged device exists at boot (i.e. no vIOMMU initially), the\nvEVENTQ is allocated when a vIOMMU is created, i.e. during the first\ndevice hot-plug.\n\nAlso, rename the local error variable and refactor smmu_writel() to use\na single error accumulator with error_propagate().\n\nEvent read and propagation will be added in a later patch.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nTested-by: Nicolin Chen <nicolinc@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 61 +++++++++++++++++++++++++++++++++++++++++--\n hw/arm/smmuv3-accel.h | 6 +++++\n hw/arm/smmuv3.c | 17 +++++++-----\n 3 files changed, 75 insertions(+), 9 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex c19c526fca..d92fcb1a89 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -390,6 +390,19 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n+static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n+{\n+ IOMMUFDVeventq *veventq = accel->veventq;\n+\n+ if (!veventq) {\n+ return;\n+ }\n+ close(veventq->veventq_fd);\n+ iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id);\n+ g_free(veventq);\n+ accel->veventq = NULL;\n+}\n+\n static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n {\n IOMMUFDViommu *viommu = accel->viommu;\n@@ -397,6 +410,7 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n if (!viommu) {\n return;\n }\n+ smmuv3_accel_free_veventq(accel);\n iommufd_backend_free_id(viommu->iommufd, accel->bypass_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->abort_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->viommu->viommu_id);\n@@ -404,6 +418,41 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n accel->viommu = NULL;\n }\n \n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ SMMUv3AccelState *accel = s->s_accel;\n+ IOMMUFDVeventq *veventq;\n+ uint32_t veventq_id;\n+ uint32_t veventq_fd;\n+\n+ if (!accel || !accel->viommu) {\n+ return true;\n+ }\n+\n+ if (accel->veventq) {\n+ return true;\n+ }\n+\n+ if (!smmuv3_eventq_enabled(s)) {\n+ return true;\n+ }\n+\n+ if (!iommufd_backend_alloc_veventq(accel->viommu->iommufd,\n+ accel->viommu->viommu_id,\n+ IOMMU_VEVENTQ_TYPE_ARM_SMMUV3,\n+ 1 << s->eventq.log2size, &veventq_id,\n+ &veventq_fd, errp)) {\n+ return false;\n+ }\n+\n+ veventq = g_new(IOMMUFDVeventq, 1);\n+ veventq->veventq_id = veventq_id;\n+ veventq->veventq_fd = veventq_fd;\n+ veventq->viommu = accel->viommu;\n+ accel->veventq = veventq;\n+ return true;\n+}\n+\n static bool\n smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n@@ -429,6 +478,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n viommu->viommu_id = viommu_id;\n viommu->s2_hwpt_id = s2_hwpt_id;\n viommu->iommufd = idev->iommufd;\n+ accel->viommu = viommu;\n \n /*\n * Pre-allocate HWPTs for S1 bypass and abort cases. These will be attached\n@@ -448,14 +498,20 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n goto free_abort_hwpt;\n }\n \n+ /* Allocate a vEVENTQ if guest has enabled event queue */\n+ if (!smmuv3_accel_alloc_veventq(s, errp)) {\n+ goto free_bypass_hwpt;\n+ }\n+\n /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */\n hwpt_id = smmuv3_accel_gbpa_hwpt(s, accel);\n if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) {\n- goto free_bypass_hwpt;\n+ goto free_veventq;\n }\n- accel->viommu = viommu;\n return true;\n \n+free_veventq:\n+ smmuv3_accel_free_veventq(accel);\n free_bypass_hwpt:\n iommufd_backend_free_id(idev->iommufd, accel->bypass_hwpt_id);\n free_abort_hwpt:\n@@ -463,6 +519,7 @@ free_abort_hwpt:\n free_viommu:\n iommufd_backend_free_id(idev->iommufd, viommu->viommu_id);\n g_free(viommu);\n+ accel->viommu = NULL;\n return false;\n }\n \ndiff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex a8a64802ec..dba6c71de5 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -22,6 +22,7 @@\n */\n typedef struct SMMUv3AccelState {\n IOMMUFDViommu *viommu;\n+ IOMMUFDVeventq *veventq;\n uint32_t bypass_hwpt_id;\n uint32_t abort_hwpt_id;\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n@@ -50,6 +51,7 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp);\n bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n Error **errp);\n void smmuv3_accel_idr_override(SMMUv3State *s);\n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n void smmuv3_accel_reset(SMMUv3State *s);\n #else\n static inline void smmuv3_accel_init(SMMUv3State *s)\n@@ -80,6 +82,10 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n static inline void smmuv3_accel_idr_override(SMMUv3State *s)\n {\n }\n+static inline bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ return true;\n+}\n static inline void smmuv3_accel_reset(SMMUv3State *s)\n {\n }\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex c08d58c579..f804d3af25 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1597,14 +1597,17 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwaddr offset,\n static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n uint64_t data, MemTxAttrs attrs)\n {\n- Error *local_err = NULL;\n+ Error *err = NULL, *local_err = NULL;\n \n switch (offset) {\n case A_CR0:\n s->cr[0] = data;\n s->cr0ack = data & ~SMMU_CR0_RESERVED;\n /* in case the command queue has been enabled */\n- smmuv3_cmdq_consume(s, &local_err);\n+ smmuv3_cmdq_consume(s, &err);\n+ /* Allocate vEVENTQ if EVENTQ is enabled and a vIOMMU is available */\n+ smmuv3_accel_alloc_veventq(s, &local_err);\n+ error_propagate(&err, local_err);\n break;\n case A_CR1:\n s->cr[1] = data;\n@@ -1621,7 +1624,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n * By acknowledging the CMDQ_ERR, SW may notify cmds can\n * be processed again\n */\n- smmuv3_cmdq_consume(s, &local_err);\n+ smmuv3_cmdq_consume(s, &err);\n break;\n case A_GERROR_IRQ_CFG0: /* 64b */\n s->gerror_irq_cfg0 = deposit64(s->gerror_irq_cfg0, 0, 32, data);\n@@ -1643,7 +1646,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n if (data & R_GBPA_UPDATE_MASK) {\n /* Ignore update bit as write is synchronous. */\n s->gbpa = data & ~R_GBPA_UPDATE_MASK;\n- smmuv3_accel_attach_gbpa_hwpt(s, &local_err);\n+ smmuv3_accel_attach_gbpa_hwpt(s, &err);\n }\n break;\n case A_STRTAB_BASE: /* 64b */\n@@ -1671,7 +1674,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n break;\n case A_CMDQ_PROD:\n s->cmdq.prod = data;\n- smmuv3_cmdq_consume(s, &local_err);\n+ smmuv3_cmdq_consume(s, &err);\n break;\n case A_CMDQ_CONS:\n s->cmdq.cons = data;\n@@ -1711,8 +1714,8 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n break;\n }\n \n- if (local_err) {\n- error_report_err(local_err);\n+ if (err) {\n+ error_report_err(err);\n }\n return MEMTX_OK;\n }\n", "prefixes": [ "v6", "3/5" ] }