Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2196286/?format=api
{ "id": 2196286, "url": "http://patchwork.ozlabs.org/api/patches/2196286/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260213103942.142823-5-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260213103942.142823-5-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-02-13T10:39:41", "name": "[v6,4/5] hw/arm/smmuv3: Introduce a helper function for event propagation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a484fd8e63584d760f38b66ff97cfbafa7d8e526", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260213103942.142823-5-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 492079, "url": "http://patchwork.ozlabs.org/api/series/492079/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492079", "date": "2026-02-13T10:39:41", "name": "vEVENTQ support for accelerated SMMUv3 devices", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/492079/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196286/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196286/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=eDoMJkIj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fC80v6r2tz1xr1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 13 Feb 2026 21:43:59 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vqqe2-0008A6-Jf; Fri, 13 Feb 2026 05:43:30 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <skolothumtho@nvidia.com>)\n id 1vqqe1-00087p-8T; Fri, 13 Feb 2026 05:43:29 -0500", "from mail-westusazlp170120002.outbound.protection.outlook.com\n ([2a01:111:f403:c001::2] helo=SJ2PR03CU001.outbound.protection.outlook.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <skolothumtho@nvidia.com>)\n id 1vqqdz-0006Zh-PD; Fri, 13 Feb 2026 05:43:29 -0500", "from CH5P220CA0022.NAMP220.PROD.OUTLOOK.COM (2603:10b6:610:1ef::28)\n by PH0PR12MB7908.namprd12.prod.outlook.com (2603:10b6:510:28e::10)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9587.22; Fri, 13 Feb\n 2026 10:43:18 +0000", "from CH1PEPF0000AD80.namprd04.prod.outlook.com\n (2603:10b6:610:1ef:cafe::eb) by CH5P220CA0022.outlook.office365.com\n (2603:10b6:610:1ef::28) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9611.14 via Frontend Transport; Fri,\n 13 Feb 2026 10:43:14 +0000", "from mail.nvidia.com (216.228.117.160) by\n CH1PEPF0000AD80.mail.protection.outlook.com (10.167.244.90) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9611.8 via Frontend Transport; Fri, 13 Feb 2026 10:43:17 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 13 Feb\n 2026 02:43:07 -0800", "from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 13 Feb\n 2026 02:43:03 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=PDuOV91HdEdYtLi6AkKJTWrguDzIcsDCETEDUAcTVKOsazJcxO8hbWyNNRRMZIiwWWfFFQz6C+TbHuXAXS/dmUTSE0zNeDGKeFpSvT0ex7y+0LjNOrG9HI7TXinwq2liApVIPDVZ6IV/47XEwKzK/x7/MrQX1V5gXhsEjNy5FpYd0qrGQ5fYn7nCsCWcMm2y+LORXLjs0L86wI3dasPPj0uWbyrsltBRNrLYx/G7SFt9BAEPxAGLuFrVsmiBL34qx11WgUwIv6YKAT47JMHQF47OeLBUJ2szNbItcR/CjN2b/n6Rba9Rr3O6iBlML/uTXShh5y8oCtQp5PxVtetaeg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=Tm5qg++ZxEfyin8nJhyKxvkYdXOUgUcbk/RAi6275gU=;\n b=NSqcTuUH00fbPpc+zti5Jxwvm6BP/WhrGVQBlGJf11tXJ3bp5DXRGomEzB8AQ5xgft4XGJHkoLDYF+FR2NxKTEuzjSYorjXSeC8Gu+vakYdmTftQ8hbceSrsZCI8vz2X+NjxYfQ5BnZdmFQpqmWG583jZG2kGJMDaCgmojbAf3tFFjGr63EdYEq2ORvonWg9ZShya6oIi3ou1veQI8fKKyy9RMszYqMuITNIDaP2g9zBxXulq4VVU3Ovs+oq4LdSCPskD9xkCthOhch2+jZjDMlvZPYyGa+cbxr/IgDdleVqJRDMdfpiZ57DIasTWn6wsaxJL/p67sz1VF1F2fDqdw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Tm5qg++ZxEfyin8nJhyKxvkYdXOUgUcbk/RAi6275gU=;\n b=eDoMJkIjEU+rnXI4NpZeHMu+tz3GJc4d0obV70/EdGKgwONWxEibKXim/oFzzZAoZtLhGO3/75t7nO6Qps8k678271mXedP8Pt4X5Y28lyBPVJgsjVWGcTaGeNC3uJC4HQxMq27txW+GUDgvC9lzxH7tA3/+sXWyfe2EQRnPRqj5KQGW+bzNxUmyH0Y2T06o42ezDyJBrEyTOjNwqfi65zXXQ0jvflaULmPw3+eKa6K3iFDIR7E+RDIO0kPB75CrfejQGZ95iyZ7dltCSTGSrzqMskivrM3rEMosDEClJ+DwXGxXQMzrULj8msItCqtolyK8MYRJaI8PWyBhVlw/Mw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": [ "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c001::2;\n envelope-from=skolothumtho@nvidia.com;\n helo=SJ2PR03CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <nicolinc@nvidia.com>, <nathanc@nvidia.com>, <mochs@nvidia.com>,\n <jan@nvidia.com>, <jgg@nvidia.com>, <jonathan.cameron@huawei.com>,\n <zhangfei.gao@linaro.org>, <zhenzhong.duan@intel.com>, <kjaju@nvidia.com>,\n <skolothumtho@nvidia.com>", "Subject": "[PATCH v6 4/5] hw/arm/smmuv3: Introduce a helper function for event\n propagation", "Date": "Fri, 13 Feb 2026 10:39:41 +0000", "Message-ID": "<20260213103942.142823-5-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260213103942.142823-1-skolothumtho@nvidia.com>", "References": "<20260213103942.142823-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH1PEPF0000AD80:EE_|PH0PR12MB7908:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c0334b47-3b56-478d-0ed1-08de6aecb30b", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|1800799024|36860700013|376014;", "X-Microsoft-Antispam-Message-Info": "\n +j2N1QNfpSFIWzcz2G0pcQ03ofh1jIoSb44n4CBwgL7a4hdSXJtlIyRsWA4CZ1ORrQu3w9xPsp8V9dZrS/oP4aqvPKEscyTqDKA9VnJZkbZZO2H208UswU+uXoh6HNlXWLWRhXK5k1uS3AAdRvWlIvXXQQHxZJABVdy1dZsDgg02Aa3/o4CqReHWB/rTfwuWuRVtZea6ERTocID51pjDaVNqJgGEIDkWn8u/RAARXmNc2EBi9mSvSlj7+KFSsbTLB5AWc7Qg73Hiz/6Gnor9Gyefq7gY8bh+YEdnGNQWDTe/D1eIdJB95V0sY3j99NWVpd94ziio1DUbDu+74y/3N30ZTPiO5D4EdQ/3f1lsyKV844c3aaS8w+FftybZMZ/T5dE8f+B9prmlS9EJas1xis5DuZD1mPRzimuKvkLkbb8e9flqPqM0WLWw99qGXg/ghNIcYJma7gEbgXu+Ki/Trx2dDIMkXFeedH10OU0M5OtG9xNACCKucUzAyAKEC/SYHKkNZmYTkEbDZ4R+GzPgoFRsMVsVZSVyevsFuLcyw2VdiG7rWbrpu9EJbJD/DUpufRY/eYRQoMixt1fGl9fTKaHttlTunY5KCt4l880JLUSnALzA6m+wJANzaD/XvskW/ame0MvBRw9wc9SUKjBS1/m73rfeFUVhQqMHtLVBlFTT7aSQ6mJuZOdrm1ufWNeEUqZSPn5hXh9YF4WBOlpaaOfwKsQhoH29Jci95rCejYrHuCulkRSFSrearqqwUQHa2WLJY+pQem7bK4h4LLsY9hhmYT757Gip4Q+RVDt5le53dGkHsWXg4uAO2TFT2EjsaCQz12SmCbpEJLu24W0zReWrl9amw25v/Q+a6xkQ+amuvC+1rZKgGDKF0tt8qlsJCmoB9HE1ZtGZWO4B1iohdJInFrnaZK/vPfDBF6/PFCS0CTokN3qO1R1bYVyQZ3Ugm3+Z2HW7WDxt2nRcStVc2Tkvrp7NduPIc7LbAGEtR8FBpEdtjZFdjh0qk20og9cdBE9QKYwNxLn2zxxohdSEjWhx1qff2hOnEUda44CWqx2h86rObjLJy7sWgoUx68N4vYcuLnioxburCWEu+kCqwBO3JRhXOvLWH1p3PIbfCrcPx7E8Sue5t6EPOHpNdKVEKkqbNchindI2XAuuwsaEoXLB8s+jtP5Yf4H5qw8EbVkDXqiEE/U3sLLweAxf+7IOeWT3JUerAFJuUblbSkt4XW/JOQYiNO6oszBINCfRmnvBZJzpPkk5Al7qui6EO5GIBsoFGyogywxqJL9/q6+bQ2HCUO0/LcHJ50L7Gu6qi4UtXOzRcd+IPeBFy5+RAYVx7e5TGMB/mV//wbGmxkn6IxIKQHEJl96hOPKVH265ikqS+RYtt/x3JjJBVPmf/hem14C53DnyfmipmwogGGWs4sPK++eWLSf/IcXRGUX8FU5TfAQmenFFuClP1D2wOP7XhxI2hwW9lnRdeiMN2vII58lGxxo3/dEu7+428nGH204ccJ7bGg8bSxmq2rFPdwYJDxlKP+1LXX96WTAGd9iHyJ/FGg8HDJEZpNah3Df8MYRUm6RGUMVf8l4t4/K6+1JNg3T1J6YYbVIlxMXFKyj/CMXNJbLV02y1+pwUcSTM6s4GSvRL5udqEaH8iVVVvtAI+VDeakaVMFke8SL6rvyjPw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014); DIR:OUT;\n SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n flnCeI3Jvglj/U373iCr9CsG4sLiblgdKCtmN2KZ85pBTHeHJ/6Ez2zK3Jp9yMu/6w7+dKCLEXAm9sUE7vl/HQwi0s+rNGXmMlIfGA8DzmqAx117UFVDJD4Q0dCo4l2AGax/AMJItzAV0qFgmrE87ME+J/I1fbaOe8EIO9FTB9HQ118pDQN5pjDL9sUBfBfe6YQYMk2V4zaBliXebErjN5sro6oFWYniE5yN66bsDyrlr43DUzIEucY1FFUvwOkNBp7BhVbhVIRIlIvEIRoVLxOmZ2yfqMQbKzYRy3vriog/OS0R6UYv91Pl3FVxjmegLji+oD2UI/sHJiWBa3kogQGFdDZyHO/vT6IJwEAT8flLsINYUZVzX+Eml5fsAfELmwkZHZHvsF8g464bOHvGKD9/VDlRuztBDTNF8cbyUIV+cvNjZzAylzcGW1XmhF3X", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Feb 2026 10:43:17.9887 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c0334b47-3b56-478d-0ed1-08de6aecb30b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH1PEPF0000AD80.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB7908", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Factor out the code that propagates event records to the guest into a\nhelper function. The accelerated SMMUv3 path can use this to propagate\nhost events in a subsequent patch.\n\nSince this helper may be called from outside the SMMUv3 core, take the\nmutex before accessing the Event Queue.\n\nNo functional change intended.\n\nReviewed-by: Nicolin Chen <nicolinc@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nTested-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-internal.h | 4 ++++\n hw/arm/smmuv3.c | 21 +++++++++++++++------\n hw/arm/trace-events | 2 +-\n 3 files changed, 20 insertions(+), 7 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h\nindex a6464425ec..b666109ad9 100644\n--- a/hw/arm/smmuv3-internal.h\n+++ b/hw/arm/smmuv3-internal.h\n@@ -352,7 +352,11 @@ typedef struct SMMUEventInfo {\n (x)->word[6] = (uint32_t)(addr & 0xffffffff); \\\n } while (0)\n \n+#define EVT_GET_TYPE(x) extract32((x)->word[0], 0, 8)\n+#define EVT_GET_SID(x) ((x)->word[1])\n+\n void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);\n+void smmuv3_propagate_event(SMMUv3State *s, Evt *evt);\n int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event);\n \n static inline int oas2bits(int oas_field)\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex f804d3af25..bcb9176c51 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -168,10 +168,23 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt)\n return MEMTX_OK;\n }\n \n+void smmuv3_propagate_event(SMMUv3State *s, Evt *evt)\n+{\n+ MemTxResult r;\n+\n+ trace_smmuv3_propagate_event(smmu_event_string(EVT_GET_TYPE(evt)),\n+ EVT_GET_SID(evt));\n+ qemu_mutex_lock(&s->mutex);\n+ r = smmuv3_write_eventq(s, evt);\n+ if (r != MEMTX_OK) {\n+ smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MASK);\n+ }\n+ qemu_mutex_unlock(&s->mutex);\n+}\n+\n void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)\n {\n Evt evt = {};\n- MemTxResult r;\n \n if (!smmuv3_eventq_enabled(s)) {\n return;\n@@ -251,11 +264,7 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)\n g_assert_not_reached();\n }\n \n- trace_smmuv3_record_event(smmu_event_string(info->type), info->sid);\n- r = smmuv3_write_eventq(s, &evt);\n- if (r != MEMTX_OK) {\n- smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MASK);\n- }\n+ smmuv3_propagate_event(s, &evt);\n info->recorded = true;\n }\n \ndiff --git a/hw/arm/trace-events b/hw/arm/trace-events\nindex 8135c0c734..3457536fb0 100644\n--- a/hw/arm/trace-events\n+++ b/hw/arm/trace-events\n@@ -40,7 +40,7 @@ smmuv3_cmdq_opcode(const char *opcode) \"<--- %s\"\n smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) \"prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d \"\n smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) \"Error on %s command execution: %d\"\n smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) \"addr: 0x%\"PRIx64\" val:0x%\"PRIx64\" size: 0x%x(%d)\"\n-smmuv3_record_event(const char *type, uint32_t sid) \"%s sid=0x%x\"\n+smmuv3_propagate_event(const char *type, uint32_t sid) \"%s sid=0x%x\"\n smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) \"sid=0x%x features:0x%x, sid_split:0x%x\"\n smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) \"strtab_base:0x%\"PRIx64\" l1ptr:0x%\"PRIx64\" l1_off:0x%x, l2ptr:0x%\"PRIx64\" l2_off:0x%x max_l2_ste:%d\"\n smmuv3_get_ste(uint64_t addr) \"STE addr: 0x%\"PRIx64\n", "prefixes": [ "v6", "4/5" ] }