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GET /api/patches/2196239/?format=api
{ "id": 2196239, "url": "http://patchwork.ozlabs.org/api/patches/2196239/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260213-pinctrl-single-bit-v1-1-c60f2fb80efb@aspeedtech.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260213-pinctrl-single-bit-v1-1-c60f2fb80efb@aspeedtech.com>", "list_archive_url": null, "date": "2026-02-13T08:17:42", "name": "[RFC,1/2] dt-bindings: pinctrl: Add pinctrl-packed", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "350587a2052b6a7d0f6292d4293a9a2dde10716c", "submitter": { "id": 80235, "url": "http://patchwork.ozlabs.org/api/people/80235/?format=api", "name": "Billy Tsai", "email": "billy_tsai@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260213-pinctrl-single-bit-v1-1-c60f2fb80efb@aspeedtech.com/mbox/", "series": [ { "id": 492065, "url": "http://patchwork.ozlabs.org/api/series/492065/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=492065", "date": "2026-02-13T08:17:41", "name": "pinctrl: add syscon-backed packed-field pinctrl driver and DT bindings", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492065/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196239/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196239/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-31650-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-gpio+bounces-31650-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=211.20.114.72", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=aspeedtech.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fC4nF6KMvz1xpY\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 13 Feb 2026 19:18:41 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 8F39330B85C9\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 13 Feb 2026 08:18:14 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1D1C531DD86;\n\tFri, 13 Feb 2026 08:18:08 +0000 (UTC)", "from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AD8E31960D;\n\tFri, 13 Feb 2026 08:18:06 +0000 (UTC)", "from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 13 Feb\n 2026 16:17:55 +0800", "from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Fri, 13 Feb 2026 16:17:55 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770970687; cv=none;\n b=Gmsiu4vKwoJbwuKThqxHCIw9QE0CVi3dH62kATwklCV7UOwQN4X0ueB/ldGTuKRO7xo3iHEi3997bqJrHAVaS3OaYM8x7qKh2rrBRYCFd5spPeEkEnHXL/rT6t2YIkTmD35Bz1St0BzmkeLHeWwlIXkqqjX9jLvoYbXK82BGkfA=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770970687; c=relaxed/simple;\n\tbh=btGp9Y9DY2YDzIKxQ4nzYfeU8KTNhNWyQaI1KcxpA8s=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:\n\t In-Reply-To:To:CC;\n b=ZOaIv+HdItFHXXtA5Cs5vT3g+IpNA8zfSm/gY0Ot2dGAYjlSygqYk4f2TzftqG7ZKHK1ZC91aaf+4K3ajtDGRpzQszt3Mv6g5CeTilycRaTl1nKmRodRjHiJjT4ViJYbJvXmv7hvmuzwWS9M4JDoGkRe+f8qjvH1c31NmhlDQno=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com;\n spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72", "From": "Billy Tsai <billy_tsai@aspeedtech.com>", "Date": "Fri, 13 Feb 2026 16:17:42 +0800", "Subject": "[PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-ID": "<20260213-pinctrl-single-bit-v1-1-c60f2fb80efb@aspeedtech.com>", "References": "<20260213-pinctrl-single-bit-v1-0-c60f2fb80efb@aspeedtech.com>", "In-Reply-To": "<20260213-pinctrl-single-bit-v1-0-c60f2fb80efb@aspeedtech.com>", "To": "Linus Walleij <linusw@kernel.org>, Tony Lindgren <tony@atomide.com>, \"Rob\n Herring\" <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, \"Conor\n Dooley\" <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>, Andrew Jeffery\n\t<andrew@codeconstruct.com.au>, Bartosz Golaszewski <brgl@kernel.org>", "CC": "<patrickw3@meta.com>, <linux-gpio@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>,\n\t<BMC-SW@aspeedtech.com>, Billy Tsai <billy_tsai@aspeedtech.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1770970675; l=6251;\n i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id;\n bh=btGp9Y9DY2YDzIKxQ4nzYfeU8KTNhNWyQaI1KcxpA8s=;\n b=s7ZgCtBuEJiKRU4PE4pTcsjmidOPe6Pr3I1F2LQbrMy2qT2AWW6Qip1McM+yHx0XX+Y2n7bVc\n zLiNwujNN/bAUthtPElUQpJiisIpUfI06GadbLUWPhHZhIFmTf8Wot1", "X-Developer-Key": "i=billy_tsai@aspeedtech.com; a=ed25519;\n pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ=" }, "content": "Add a Devicetree binding for a generic pin controller where pinmux and/or\npin configuration are represented as fixed-width fields packed\nsequentially within shared registers.\n\nThe binding targets controllers that are typically exposed as subnodes of\na syscon node and accessed via regmap-mmio through the parent.\n\nSigned-off-by: Billy Tsai <billy_tsai@aspeedtech.com>\n---\n .../bindings/pinctrl/pinctrl-packed.yaml | 166 +++++++++++++++++++++\n 1 file changed, 166 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml\nnew file mode 100644\nindex 000000000000..dd01ba2fed71\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml\n@@ -0,0 +1,166 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/pinctrl-packed.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Generic Pin Controller with Packed-Field Registers\n+\n+maintainers:\n+ - Billy Tsai <billy_tsai@aspeedtech.com>\n+\n+description:\n+ This binding describes pin controller hardware where pinmux and/or\n+ pin configuration fields are represented as fixed-width fields packed\n+ sequentially within shared registers.\n+\n+ Such controllers are commonly embedded within a larger system control\n+ unit (SCU) register block and may be exposed as subnodes of a syscon\n+ device.\n+\n+ Conceptually, this model is related to the pinctrl-single binding,\n+ but instead of describing individual register offsets via\n+ <offset, value, mask> tuples, the hardware provides fixed-width,\n+ per-pin fields packed linearly within shared registers.\n+\n+properties:\n+ compatible:\n+ oneOf:\n+ - enum:\n+ - pinctrl-packed\n+ - pinconf-packed\n+\n+ reg:\n+ maxItems: 1\n+\n+ '#pinctrl-cells':\n+ description:\n+ The pinctrl provider uses standard state nodes referenced by pinctrl-N\n+ properties; consumers do not pass per-pin arguments via phandle.\n+ const: 1\n+\n+ pinctrl-packed,function-mask:\n+ description: Mask of the allowed register bits for a single pin.\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+\n+ pinctrl-packed,gpio-range:\n+ description: Optional list of pin base, nr pins & gpio function.\n+ $ref: /schemas/types.yaml#/definitions/phandle-array\n+ items:\n+ items:\n+ - description: phandle of a gpio-range node\n+ - description: pin base\n+ - description: number of pins\n+ - description: gpio function\n+\n+patternProperties:\n+ '-pins(-[0-9]+)?$|-pin$':\n+ type: object\n+ additionalProperties: false\n+\n+ properties:\n+ pinctrl-packed,pins:\n+ description: Array of pin index and function selector pairs.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+\n+ pinctrl-packed,bias-pullup:\n+ description: Optional bias pull-up configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 4\n+ items:\n+ - description: Input value.\n+ - description: Enabled pull-up bits.\n+ - description: Disabled pull-up bits.\n+ - description: Pull-up mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,bias-pulldown:\n+ description: Optional bias pull-down configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 4\n+ items:\n+ - description: Input value.\n+ - description: Enabled pull-down bits.\n+ - description: Disabled pull-down bits.\n+ - description: Pull-down mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,drive-strength:\n+ description: Optional drive strength configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 2\n+ items:\n+ - description: Drive strength value.\n+ - description: Drive strength mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,input-schmitt:\n+ description: Optional input Schmitt trigger configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 2\n+ items:\n+ - description: Schmitt trigger value.\n+ - description: Schmitt trigger mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,input-schmitt-enable:\n+ description: Optional input Schmitt enable configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 4\n+ items:\n+ - description: Input value.\n+ - description: Enable bits.\n+ - description: Disable bits.\n+ - description: Schmitt mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,low-power-mode:\n+ description: Optional low power mode configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 2\n+ items:\n+ - description: Low power value.\n+ - description: Low power mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,slew-rate:\n+ description: Optional slew rate configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 2\n+ items:\n+ - description: Slew rate value.\n+ - description: Slew rate mask.\n+ additionalItems: false\n+\n+required:\n+ - compatible\n+ - reg\n+ - \"#pinctrl-cells\"\n+ - pinctrl-packed,function-mask\n+\n+additionalProperties: false\n+\n+allOf:\n+ - $ref: pinctrl.yaml#\n+\n+examples:\n+ - |\n+ syscon@0 {\n+ compatible = \"syscon\", \"simple-mfd\";\n+ reg = <0x0 0x1000>;\n+ ranges;\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+\n+ pinctrl@400 {\n+ compatible = \"pinctrl-packed\";\n+ reg = <0x400 0x80>;\n+ #pinctrl-cells = <1>;\n+ pinctrl-packed,function-mask = <0xf>;\n+\n+ uart0-pins {\n+ /* <pin_index function_select> pairs */\n+ pinctrl-packed,pins = <0 2>, <1 2>;\n+ };\n+ };\n+ };\n", "prefixes": [ "RFC", "1/2" ] }