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GET /api/patches/2196221/?format=api
{ "id": 2196221, "url": "http://patchwork.ozlabs.org/api/patches/2196221/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260213055342.3124872-9-anup.patel@oss.qualcomm.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260213055342.3124872-9-anup.patel@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-13T05:53:42", "name": "[v2,8/8] lib: sbi_irqchip: Allow registering interrupt handlers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2e4698b38ed5c16dc7ee22bebbc4f20d6393061b", "submitter": { "id": 92322, "url": "http://patchwork.ozlabs.org/api/people/92322/?format=api", "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260213055342.3124872-9-anup.patel@oss.qualcomm.com/mbox/", "series": [ { "id": 492060, "url": "http://patchwork.ozlabs.org/api/series/492060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=492060", "date": "2026-02-13T05:53:41", "name": "Extend irqchip framework for M-mode interrupts", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492060/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196221/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196221/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=QpS4xrGd;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=OFD4b4jV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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s=qcppdkim1; bh=QwNUA3lGbDW\n\tzgwOxtOW1RztXcnybH+RGHizW4nuja3c=; b=OFD4b4jVDZjhxboqMF0sHt4EaCX\n\t2wluS8ArtwluYuJnyVsCXmVpBzYdHZLD6/FxiOm27Bq057GDAkeNijBXVE2uR0To\n\tLkpShOPMFaVQea2qiZuOfWP6aLR296n/MJTVtJILc5ZXzIbAjHqFOOHUxtTt4xmD\n\t5MQsAtkyvu2h0Y8l2CU6vbETABZANfp2p48gZ3eP2hbyQGlw4OU9N2tomDiWSP19\n\t6oXEJLMHldHu72ekvMDiM16cc8o0slceXvlAIcJSVx4RtMLRPawNOvxV3ayk6lg8\n\tAklxc+5VrhHReGo3Gmo/hDLg6pp9LsLLpybzMSNTFscFZT7jk7SXELjkUYQ==" ], "From": "Anup Patel <anup.patel@oss.qualcomm.com>", "To": "Atish Patra <atish.patra@linux.dev>", "Cc": "Andrew Jones <andrew.jones@oss.qualcomm.com>,\n Raymond Mao <raymond.mao@riscstar.com>,\n Dave Patel <dave.patel@riscstar.com>,\n Samuel Holland <samuel.holland@sifive.com>,\n Anup Patel <anup@brainfault.org>, opensbi@lists.infradead.org,\n Anup Patel <anup.patel@oss.qualcomm.com>", "Subject": "[PATCH v2 8/8] lib: sbi_irqchip: Allow registering interrupt handlers", "Date": "Fri, 13 Feb 2026 11:23:42 +0530", "Message-ID": "<20260213055342.3124872-9-anup.patel@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260213055342.3124872-1-anup.patel@oss.qualcomm.com>", "References": "<20260213055342.3124872-1-anup.patel@oss.qualcomm.com>", "MIME-Version": "1.0", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-12_05,2026-02-12_03,2025-10-01_01" ], "X-Proofpoint-ORIG-GUID": "reXJwWAZeHecj2I7ycRkD2P_6UyjzGlf", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEzMDA0MiBTYWx0ZWRfX4PicpQGWZvVU\n NZuNeQ2DlVigJHFjZLxJ9r+8pOIrn18xptsdn+vA1TEW6oamPGpNAFSc/9EYqjN03KygVKB7Swr\n Tw6OKvRFkHMwxS7q9DgkofSq0Ea6ajkGbweU9ZPKefLxI2OiX3kH3Os8EOHaL3Lssy1YwIdCB49\n BB1WBgmdED/HV8Jw8bgNRo2oryrfBHnBPSnWP7Yi+w0JpE/p87woKqwukgTFoFDn3e3vlHiqexz\n 8dAO6ZJ6JDFJonB5ZvLNA18AVi/dfv3Vd0KZdRXPPXUU/f6Kx002ias2tYxsePKMqcYikvPr2OW\n e/B1ILwInij09ge/0v6N6jZQsFnnznuEoWVBePnfJgKBNZ/AHsiYNkQ2EHJk9C8WRuM9M8PP25V\n K/dMdGfIkFCsGKc0j+Cr/L78hiLt2h4zzlGkNZydVoyJRkV+mA9rWYtZElosSSpPWaeT//5bfGD\n mvuqPSih5l8pRZXHMMg==", "X-Proofpoint-GUID": "reXJwWAZeHecj2I7ycRkD2P_6UyjzGlf", "X-Authority-Analysis": "v=2.4 cv=CLInnBrD c=1 sm=1 tr=0 ts=698ebc6b cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22\n a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=bDdBU3oEAAAA:8\n a=dxl-2DmbjyPBmnOifdcA:9 a=DN7SgORnOiO7RqxRx1GC:22", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 adultscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0\n malwarescore=0 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602130042", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260212_215451_259904_3D927BFA ", "X-CRM114-Status": "GOOD ( 22.33 )", "X-Spam-Score": "-2.7 (--)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: To handle external interrupts in M-mode,\n the sbi_irqchip framework\n must allow registering interrupt handlers from device drivers.\n Signed-off-by:\n Anup Patel <anup.patel@oss.qualcomm.com> --- include/sbi/sbi_irqchip.h |\n 56 ++++++++++- lib/sbi/sbi_irqchip.c | 203\n +++++++++++++++++++++++++++++++++++++-\n lib/utils/irqchip/aplic.c | 1 [...]\n Content analysis details: (-2.7 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n 0.0 RCVD_IN_VALIDITY_CERTIFIED_BLOCKED RBL: ADMINISTRATOR NOTICE: The\n query to Validity was blocked. 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See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [205.220.168.131 listed in\n sa-accredit.habeas.com]\n -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low\n trust\n [205.220.168.131 listed in list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "To handle external interrupts in M-mode, the sbi_irqchip framework\nmust allow registering interrupt handlers from device drivers.\n\nSigned-off-by: Anup Patel <anup.patel@oss.qualcomm.com>\n---\n include/sbi/sbi_irqchip.h | 56 ++++++++++-\n lib/sbi/sbi_irqchip.c | 203 +++++++++++++++++++++++++++++++++++++-\n lib/utils/irqchip/aplic.c | 1 +\n lib/utils/irqchip/imsic.c | 9 ++\n lib/utils/irqchip/plic.c | 1 +\n 5 files changed, 267 insertions(+), 3 deletions(-)", "diff": "diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h\nindex d2c47ae8..77b54110 100644\n--- a/include/sbi/sbi_irqchip.h\n+++ b/include/sbi/sbi_irqchip.h\n@@ -18,12 +18,21 @@ struct sbi_scratch;\n \n /** irqchip hardware device */\n struct sbi_irqchip_device {\n-\t/** Node in the list of irqchip devices */\n+\t/** Node in the list of irqchip devices (private) */\n \tstruct sbi_dlist node;\n \n+\t/** Internal data of all hardware interrupts of this irqchip (private) */\n+\tstruct sbi_irqchip_hwirq_data *hwirqs;\n+\n+\t/** List of interrupt handlers */\n+\tstruct sbi_dlist handler_list;\n+\n \t/** Unique ID of this irqchip */\n \tu32 id;\n \n+\t/** Number of hardware IRQs of this irqchip */\n+\tu32 num_hwirq;\n+\n \t/** Set of harts targetted by this irqchip */\n \tstruct sbi_hartmask target_harts;\n \n@@ -32,6 +41,21 @@ struct sbi_irqchip_device {\n \n \t/** Process hardware interrupts from this irqchip */\n \tint (*process_hwirqs)(struct sbi_irqchip_device *chip);\n+\n+\t/** Setup a hardware interrupt of this irqchip */\n+\tint (*hwirq_setup)(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+\t/** Cleanup a hardware interrupt of this irqchip */\n+\tvoid (*hwirq_cleanup)(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+\t/** End of hardware interrupt of this irqchip */\n+\tvoid (*hwirq_eoi)(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+\t/** Mask a hardware interrupt of this irqchip */\n+\tvoid (*hwirq_mask)(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+\t/** Unmask a hardware interrupt of this irqchip */\n+\tvoid (*hwirq_unmask)(struct sbi_irqchip_device *chip, u32 hwirq);\n };\n \n /**\n@@ -44,6 +68,36 @@ struct sbi_irqchip_device {\n */\n int sbi_irqchip_process(void);\n \n+/**\n+ * Process a hwirq of an irqchip device\n+ *\n+ * This function is called by irqchip drivers to handle hardware\n+ * interrupts of the irqchip.\n+ */\n+int sbi_irqchip_process_hwirq(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+/** Unmask a hardware interrupt */\n+int sbi_irqchip_unmask_hwirq(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+/** Mask a hardware interrupt */\n+int sbi_irqchip_mask_hwirq(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+/** Default raw hardware interrupt handler */\n+int sbi_irqchip_raw_handler_default(struct sbi_irqchip_device *chip, u32 hwirq);\n+\n+/** Set raw hardware interrupt handler */\n+int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,\n+\t\t\t\tint (*raw_hndl)(struct sbi_irqchip_device *, u32));\n+\n+/** Register a hardware interrupt handler */\n+int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n+\t\t\t\t u32 first_hwirq, u32 num_hwirq,\n+\t\t\t\t int (*callback)(u32 hwirq, void *opaque), void *opaque);\n+\n+/** Unregister a hardware interrupt handler */\n+int sbi_irqchip_unregister_handler(struct sbi_irqchip_device *chip,\n+\t\t\t\t u32 first_hwirq, u32 num_hwirq);\n+\n /** Find an irqchip device based on unique ID */\n struct sbi_irqchip_device *sbi_irqchip_find_device(u32 id);\n \ndiff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c\nindex 5df6189b..f0744830 100644\n--- a/lib/sbi/sbi_irqchip.c\n+++ b/lib/sbi/sbi_irqchip.c\n@@ -7,11 +7,36 @@\n * Anup Patel <apatel@ventanamicro.com>\n */\n \n+#include <sbi/sbi_heap.h>\n #include <sbi/sbi_irqchip.h>\n #include <sbi/sbi_list.h>\n #include <sbi/sbi_platform.h>\n #include <sbi/sbi_scratch.h>\n \n+/** Internal irqchip hardware interrupt data */\n+struct sbi_irqchip_hwirq_data {\n+\t/** raw hardware interrupt handler */\n+\tint (*raw_handler)(struct sbi_irqchip_device *chip, u32 hwirq);\n+};\n+\n+/** Internal irqchip interrupt handler */\n+struct sbi_irqchip_handler {\n+\t/** Node in the list of irqchip handlers (private) */\n+\tstruct sbi_dlist node;\n+\n+\t/** First hardware IRQ handled by this handler */\n+\tu32 first_hwirq;\n+\n+\t/** Number of consecutive hardware IRQs handled by this handler */\n+\tu32 num_hwirq;\n+\n+\t/** Callback function of this handler */\n+\tint (*callback)(u32 hwirq, void *priv);\n+\n+\t/** Callback private data */\n+\tvoid *priv;\n+};\n+\n struct sbi_irqchip_hart_data {\n \tstruct sbi_irqchip_device *chip;\n };\n@@ -30,6 +55,172 @@ int sbi_irqchip_process(void)\n \treturn hd->chip->process_hwirqs(hd->chip);\n }\n \n+int sbi_irqchip_process_hwirq(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tstruct sbi_irqchip_hwirq_data *data;\n+\n+\tif (!chip || chip->num_hwirq <= hwirq)\n+\t\treturn SBI_EINVAL;\n+\n+\tdata = &chip->hwirqs[hwirq];\n+\tif (!data->raw_handler)\n+\t\treturn SBI_ENOENT;\n+\n+\treturn data->raw_handler(chip, hwirq);\n+}\n+\n+int sbi_irqchip_unmask_hwirq(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tif (!chip || chip->num_hwirq <= hwirq)\n+\t\treturn SBI_EINVAL;\n+\n+\tif (chip->hwirq_unmask)\n+\t\tchip->hwirq_unmask(chip, hwirq);\n+\treturn 0;\n+}\n+\n+int sbi_irqchip_mask_hwirq(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tif (!chip || chip->num_hwirq <= hwirq)\n+\t\treturn SBI_EINVAL;\n+\n+\tif (chip->hwirq_mask)\n+\t\tchip->hwirq_mask(chip, hwirq);\n+\treturn 0;\n+}\n+\n+static struct sbi_irqchip_handler *sbi_irqchip_find_handler(struct sbi_irqchip_device *chip,\n+\t\t\t\t\t\t\t u32 hwirq)\n+{\n+\tstruct sbi_irqchip_handler *h;\n+\n+\tif (!chip || chip->num_hwirq <= hwirq)\n+\t\treturn NULL;\n+\n+\tsbi_list_for_each_entry(h, &chip->handler_list, node) {\n+\t\tif (h->first_hwirq <= hwirq && hwirq < (h->first_hwirq + h->num_hwirq))\n+\t\t\treturn h;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+int sbi_irqchip_raw_handler_default(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tstruct sbi_irqchip_handler *h;\n+\tint rc;\n+\n+\tif (!chip || chip->num_hwirq <= hwirq)\n+\t\treturn SBI_EINVAL;\n+\n+\th = sbi_irqchip_find_handler(chip, hwirq);\n+\trc = h->callback(hwirq, h->priv);\n+\n+\tif (chip->hwirq_eoi)\n+\t\tchip->hwirq_eoi(chip, hwirq);\n+\n+\treturn rc;\n+}\n+\n+int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,\n+\t\t\t\tint (*raw_hndl)(struct sbi_irqchip_device *, u32))\n+{\n+\tstruct sbi_irqchip_hwirq_data *data;\n+\n+\tif (!chip || chip->num_hwirq <= hwirq)\n+\t\treturn SBI_EINVAL;\n+\n+\tdata = &chip->hwirqs[hwirq];\n+\tdata->raw_handler = raw_hndl;\n+\treturn 0;\n+}\n+\n+int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n+\t\t\t\t u32 first_hwirq, u32 num_hwirq,\n+\t\t\t\t int (*callback)(u32 hwirq, void *opaque), void *priv)\n+{\n+\tstruct sbi_irqchip_handler *h;\n+\tu32 i, j;\n+\tint rc;\n+\n+\tif (!chip || !num_hwirq || !callback)\n+\t\treturn SBI_EINVAL;\n+\tif (chip->num_hwirq <= first_hwirq ||\n+\t chip->num_hwirq <= (first_hwirq + num_hwirq - 1))\n+\t\treturn SBI_EBAD_RANGE;\n+\n+\th = sbi_irqchip_find_handler(chip, first_hwirq);\n+\tif (h)\n+\t\treturn SBI_EALREADY;\n+\th = sbi_irqchip_find_handler(chip, first_hwirq + num_hwirq - 1);\n+\tif (h)\n+\t\treturn SBI_EALREADY;\n+\n+\th = sbi_zalloc(sizeof(*h));\n+\tif (!h)\n+\t\treturn SBI_ENOMEM;\n+\th->first_hwirq = first_hwirq;\n+\th->num_hwirq = num_hwirq;\n+\th->callback = callback;\n+\th->priv = priv;\n+\tsbi_list_add_tail(&h->node, &chip->handler_list);\n+\n+\tif (chip->hwirq_setup) {\n+\t\tfor (i = 0; i < h->num_hwirq; i++) {\n+\t\t\trc = chip->hwirq_setup(chip, h->first_hwirq + i);\n+\t\t\tif (rc) {\n+\t\t\t\tif (chip->hwirq_cleanup) {\n+\t\t\t\t\tfor (j = 0; j < i; j++)\n+\t\t\t\t\t\tchip->hwirq_cleanup(chip, h->first_hwirq + j);\n+\t\t\t\t}\n+\t\t\t\tsbi_list_del(&h->node);\n+\t\t\t\tsbi_free(h);\n+\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (chip->hwirq_unmask) {\n+\t\tfor (i = 0; i < h->num_hwirq; i++)\n+\t\t\tchip->hwirq_unmask(chip, h->first_hwirq + i);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int sbi_irqchip_unregister_handler(struct sbi_irqchip_device *chip,\n+\t\t\t\t u32 first_hwirq, u32 num_hwirq)\n+{\n+\tstruct sbi_irqchip_handler *fh, *lh;\n+\tu32 i;\n+\n+\tif (!chip || !num_hwirq)\n+\t\treturn SBI_EINVAL;\n+\tif (chip->num_hwirq <= first_hwirq ||\n+\t chip->num_hwirq <= (first_hwirq + num_hwirq - 1))\n+\t\treturn SBI_EBAD_RANGE;\n+\n+\tfh = sbi_irqchip_find_handler(chip, first_hwirq);\n+\tif (!fh || fh->first_hwirq != first_hwirq || fh->num_hwirq != num_hwirq)\n+\t\treturn SBI_ENODEV;\n+\tlh = sbi_irqchip_find_handler(chip, first_hwirq + num_hwirq - 1);\n+\tif (!lh || lh != fh)\n+\t\treturn SBI_ENODEV;\n+\n+\tif (chip->hwirq_mask) {\n+\t\tfor (i = 0; i < fh->num_hwirq; i++)\n+\t\t\tchip->hwirq_mask(chip, fh->first_hwirq + i);\n+\t}\n+\n+\tif (chip->hwirq_cleanup) {\n+\t\tfor (i = 0; i < fh->num_hwirq; i++)\n+\t\t\tchip->hwirq_cleanup(chip, fh->first_hwirq + i);\n+\t}\n+\n+\tsbi_list_del(&fh->node);\n+\treturn 0;\n+}\n+\n struct sbi_irqchip_device *sbi_irqchip_find_device(u32 id)\n {\n \tstruct sbi_irqchip_device *chip;\n@@ -46,9 +237,9 @@ int sbi_irqchip_add_device(struct sbi_irqchip_device *chip)\n {\n \tstruct sbi_irqchip_hart_data *hd;\n \tstruct sbi_scratch *scratch;\n-\tu32 h;\n+\tu32 i, h;\n \n-\tif (!chip || !sbi_hartmask_weight(&chip->target_harts))\n+\tif (!chip || !chip->num_hwirq || !sbi_hartmask_weight(&chip->target_harts))\n \t\treturn SBI_EINVAL;\n \n \tif (sbi_irqchip_find_device(chip->id))\n@@ -68,6 +259,14 @@ int sbi_irqchip_add_device(struct sbi_irqchip_device *chip)\n \t\t}\n \t}\n \n+\tchip->hwirqs = sbi_zalloc(sizeof(*chip->hwirqs) * chip->num_hwirq);\n+\tif (!chip->hwirqs)\n+\t\treturn SBI_ENOMEM;\n+\tfor (i = 0; i < chip->num_hwirq; i++)\n+\t\tsbi_irqchip_set_raw_handler(chip, i, sbi_irqchip_raw_handler_default);\n+\n+\tSBI_INIT_LIST_HEAD(&chip->handler_list);\n+\n \tsbi_list_add_tail(&chip->node, &irqchip_list);\n \treturn 0;\n }\ndiff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c\nindex d47a810b..ec69c82b 100644\n--- a/lib/utils/irqchip/aplic.c\n+++ b/lib/utils/irqchip/aplic.c\n@@ -307,6 +307,7 @@ int aplic_cold_irqchip_init(struct aplic_data *aplic)\n \n \t/* Register irqchip device */\n \taplic->irqchip.id = aplic->unique_id;\n+\taplic->irqchip.num_hwirq = aplic->num_source + 1;\n \trc = sbi_irqchip_add_device(&aplic->irqchip);\n \tif (rc)\n \t\treturn rc;\ndiff --git a/lib/utils/irqchip/imsic.c b/lib/utils/irqchip/imsic.c\nindex 0f296c89..7559a069 100644\n--- a/lib/utils/irqchip/imsic.c\n+++ b/lib/utils/irqchip/imsic.c\n@@ -346,9 +346,17 @@ int imsic_data_check(struct imsic_data *imsic)\n \treturn 0;\n }\n \n+static int imsic_hwirq_setup(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tif (!hwirq || hwirq == IMSIC_IPI_ID)\n+\t\treturn SBI_ENOTSUPP;\n+\treturn 0;\n+}\n+\n static struct sbi_irqchip_device imsic_device = {\n \t.warm_init\t= imsic_warm_irqchip_init,\n \t.process_hwirqs\t= imsic_process_hwirqs,\n+\t.hwirq_setup\t= imsic_hwirq_setup,\n };\n \n int imsic_cold_irqchip_init(struct imsic_data *imsic)\n@@ -392,6 +400,7 @@ int imsic_cold_irqchip_init(struct imsic_data *imsic)\n \n \t/* Register irqchip device */\n \timsic_device.id = imsic->unique_id;\n+\timsic_device.num_hwirq = imsic->num_ids + 1;\n \tsbi_hartmask_set_all(&imsic_device.target_harts);\n \trc = sbi_irqchip_add_device(&imsic_device);\n \tif (rc)\ndiff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c\nindex 973f7c2a..2d721724 100644\n--- a/lib/utils/irqchip/plic.c\n+++ b/lib/utils/irqchip/plic.c\n@@ -281,6 +281,7 @@ int plic_cold_irqchip_init(struct plic_data *plic)\n \n \t/* Register irqchip device */\n \tplic->irqchip.id = plic->unique_id;\n+\tplic->irqchip.num_hwirq = plic->num_src + 1;\n \tplic->irqchip.warm_init = plic_warm_irqchip_init;\n \treturn sbi_irqchip_add_device(&plic->irqchip);\n }\n", "prefixes": [ "v2", "8/8" ] }