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GET /api/patches/2196201/?format=api
{ "id": 2196201, "url": "http://patchwork.ozlabs.org/api/patches/2196201/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260213040852.3340547-5-sherry.sun@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260213040852.3340547-5-sherry.sun@nxp.com>", "list_archive_url": null, "date": "2026-02-13T04:08:44", "name": "[V5,04/12] PCI: imx6: Add support for parsing the reset property in new Root Port binding", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2adca5bbbaf7e9fbefee10489106e95092cc1ce7", "submitter": { "id": 77063, "url": "http://patchwork.ozlabs.org/api/people/77063/?format=api", "name": "Sherry Sun", "email": "sherry.sun@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260213040852.3340547-5-sherry.sun@nxp.com/mbox/", "series": [ { "id": 492056, "url": "http://patchwork.ozlabs.org/api/series/492056/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492056", "date": "2026-02-13T04:08:40", "name": "pci-imx6: Add support for parsing the reset property in new Root Port binding", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/492056/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196201/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196201/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47248-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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"DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=CkiMxUttTum+oCXB5Yhi3HuDFHcVUJHOQlBw69/0sDg=;\n b=dKYDQSw620jtRz+B82nOiTEQXxkMVgyBUNUw3EhjBHdNpXg7vwu4jQMNMkO+NUkpAhHd/vxhXdfsFEkDe5KPfAmO943gfzSLkSXA/tJ9T6M3A8GzSVXG9zTZtmDQHBy2dRgVKyrzdEhsXko0JheqQcG2KiksDvwURvBJNmoF+nyeXjXz7U5wtaY5Ew0eLFxdWyBxwM37UkBHb0wS++0220heIbt9A+dsc7N6bL0ukgAB5tnV3yU5Rza3sD1HJup5Duc0STSBvd6Q3PyvVjZI9jgW1elWAHv0l+0BbVz5Txtj+gRUJE1l7H+utyIUjebvFwXAYGgsrWFaKUg3cr+oPA==", "From": "Sherry Sun <sherry.sun@nxp.com>", "To": "hongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de,\n\tFrank.Li@nxp.com,\n\tbhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\ts.hauer@pengutronix.de,\n\tfestevam@gmail.com", "Cc": "imx@lists.linux.dev,\n\tkernel@pengutronix.de,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH V5 04/12] PCI: imx6: Add support for parsing the reset\n property in new Root Port binding", "Date": "Fri, 13 Feb 2026 12:08:44 +0800", "Message-Id": "<20260213040852.3340547-5-sherry.sun@nxp.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20260213040852.3340547-1-sherry.sun@nxp.com>", "References": "<20260213040852.3340547-1-sherry.sun@nxp.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SG2PR06CA0206.apcprd06.prod.outlook.com\n (2603:1096:4:68::14) To VI0PR04MB12114.eurprd04.prod.outlook.com\n (2603:10a6:800:315::13)", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": 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NaW9grcmudRyE2/PC05rNb/JcCVBMXoEiYetKzhnF2kSg3ynzW8RKjkkFXr1srVwRG7E7erMKEbJzldvbujHqAB8UHTYoGuQU3keVo9+37lkBrM59TswOw9HocXhDe2flmm+hPBE9sriHb8a0faQ/nKGF5vgLhTJAaMOctmeER4Fo1qgsnoLMpm+czXMXbmcfqrfFV2NLc1l0F0e7z/tE73R0HKWHYQBJ8+atyD0mkPH4bbUYCw3qMr0X7WOo/rzsZv8Ek+C+z+WIhdW5dkNHXW1J+g5eh3+jgehBnbjBxFbQBX5BpsRQQWcDdDl5A7zXXaj+QUnoIBgb/f7GYRet3yXgUEltOFBcpQPrHm78PWxB8Loi6RINegW4rY9yZW+e7vYuDP9oZ+jodX2o/Ft8/WJitiUBC/YZSPcKyCVg3dnOUSM37OcC2wjQ1wRoHSNfojCNxsSYmQissWQgvDmE2h3XWy+O9yAzrAe7PXezhVYU2ShiXinqMuVfPwVp4Y51uiREInZ9W67lUgZtb7WEi/uGNoWj12Jr9j0YQd3vghwQ8SNGbu9Ghs1UYM+eoPaiOjezHYWFzwqcwVkGSLbYiin1IEqgCNhucGWi9TmCJM67dldwZSvu8TqeZIgxTc2aVfj7mh7m+nWlkWCkiBh8p60NWJ8onkdZpsHmAXWTBs4S1sScg2AmHnILYySCjaz94dtVXfyw7kBHBHa9pjN/5cFeff1aMHAuk7booDPdbi8QggCaBqOA7pQIqCI8NZ6hxC2qzq61DYIkem+VfEg+Jb63ENK1Ytg5RtMuNSZjfEIDpYRVmNSmfM7wLziT0VISO3G0vjsyYwFRbWa3Gq73EZ6i6Qf3XIy5M7G21NQ/P01jzLsgJAq0TWXnxbodHK6DLeA2PU2ZC6opx8t4mYw20NvS9V4kF8p9cLImVFQyqJQ0oeIutO1jWziVdo478kT6OYgnnDLQR+A1IaX6jV39tcHFggo/VWwoAJVmFWjCtCZ81mk+3Lo00w6TnuDcec+dX0PrSLpX1xZEWFDkX9JUztX7STCo1hkwOHRAyTLEE0l1wsW/u36kB0YGbal5kLtOHsVZxRyrupM6uAgfQUvJ/GreOanJnZDiFO6zwnrzBPsFKGIoIZBCgrnkwC5R2cG5MpjXxIqfGSQxAR+U+t4is9kELoMPgI8Yl4lNjSLjMnL3b6b9bXXvH7vlkrn1oK4WFDgwf9Ialvo1XuDbCijwKTyTPtk05IhOh7K55nDE7Am8FqE60OZqrHRbQh0Twox29itR113hkY4uJzdjI4uClqgp5QJReFd8KIWyudVYed/t+5e08eMTw4TFihAtznO9QTYwnidsRFMuDa59E2Ibze5gu9O/gIZ7rSpZMY+4DrPzbwyGlWuReA4gs/pg9rny2L1m7d2AZf+6v9ATOMxO8BIjckyqf/ugJBp3B44z80U4pNxQ+RGsfLzWb5jD2MJXcJJWUjm5K7bmRiZ79dzWSdzWbjOnC8Rw2uFM/qGqmvkmKDotfGfPh7ZKd+kjRUYRh8+NvdSLms9SP429x3fIPpKsJeOkR9Jgta1SqFzaVYxhvKvV/8yWWR3/sQwWoqh7opvi22CGnpUvoBhqOuRiqLOVrfFk7IoHUcl8DZ7KO4+OVsCKgAkl6lfvpf/aHguWb57IdlGywUryMrUZ6hUm0Kl5Er5HpnuG839panI8b9o5yrO2s56XeLgg4BR6AS0Un8XM4Mzta8EpBXMwxp4vQ==", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1f4a5c24-e860-4023-b54a-08de6ab58197", "X-MS-Exchange-CrossTenant-AuthSource": "VI0PR04MB12114.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Feb 2026 04:08:13.4351\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n LzGAHvJjsGG1ERKuEudVs4diHn/xBJEkKBX8nVccg5oHy3/c8Qdz6jottlXPRHPIF5v6uj+nso/YB/0tifS9hQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DU4PR04MB11900" }, "content": "The current DT binding for pci-imx6 specifies the 'reset-gpios' property\nin the host bridge node. However, the PERST# signal logically belongs to\nindividual Root Ports rather than the host bridge itself. This becomes\nimportant when supporting PCIe KeyE connector and PCI power control\nframework for pci-imx6 driver, which requires properties to be specified\nin Root Port nodes.\n\nAdd support for parsing 'reset-gpios' from Root Port child nodes using\nthe common helper pci_host_common_parse_ports(). The parsed reset GPIOs\nare stored in the bridge's ports list and accessed during core reset\noperations. Pre-allocate pci_host_bridge in imx_pcie_probe() for RC mode\nto enable early Root Port parsing.\n\nTo maintain DT backwards compatibility, fallback to the legacy method of\nparsing the host bridge node if the reset property is not present in the\nRoot Port node.\n\nSigned-off-by: Sherry Sun <sherry.sun@nxp.com>\n---\n drivers/pci/controller/dwc/pci-imx6.c | 81 ++++++++++++++++++++++-----\n 1 file changed, 67 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\nindex a5b8d0b71677..75afd56dad50 100644\n--- a/drivers/pci/controller/dwc/pci-imx6.c\n+++ b/drivers/pci/controller/dwc/pci-imx6.c\n@@ -34,6 +34,7 @@\n #include <linux/pm_runtime.h>\n \n #include \"../../pci.h\"\n+#include \"../pci-host-common.h\"\n #include \"pcie-designware.h\"\n \n #define IMX8MQ_GPR_PCIE_REF_USE_PAD\t\tBIT(9)\n@@ -150,7 +151,6 @@ struct imx_lut_data {\n \n struct imx_pcie {\n \tstruct dw_pcie\t\t*pci;\n-\tstruct gpio_desc\t*reset_gpiod;\n \tstruct clk_bulk_data\t*clks;\n \tint\t\t\tnum_clks;\n \tbool\t\t\tsupports_clkreq;\n@@ -897,29 +897,40 @@ static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)\n \n static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)\n {\n+\tstruct dw_pcie *pci = imx_pcie->pci;\n+\tstruct pci_host_bridge *bridge = pci->pp.bridge;\n+\tstruct pci_host_port *port;\n+\n \treset_control_assert(imx_pcie->pciephy_reset);\n \n \tif (imx_pcie->drvdata->core_reset)\n \t\timx_pcie->drvdata->core_reset(imx_pcie, true);\n \n \t/* Some boards don't have PCIe reset GPIO. */\n-\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);\n+\tif (bridge)\n+\t\tlist_for_each_entry(port, &bridge->ports, list)\n+\t\t\tgpiod_set_value_cansleep(port->reset, 1);\n }\n \n static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)\n {\n+\tstruct dw_pcie *pci = imx_pcie->pci;\n+\tstruct pci_host_bridge *bridge = pci->pp.bridge;\n+\tstruct pci_host_port *port;\n+\n \treset_control_deassert(imx_pcie->pciephy_reset);\n \n \tif (imx_pcie->drvdata->core_reset)\n \t\timx_pcie->drvdata->core_reset(imx_pcie, false);\n \n \t/* Some boards don't have PCIe reset GPIO. */\n-\tif (imx_pcie->reset_gpiod) {\n-\t\tmsleep(100);\n-\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);\n-\t\t/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */\n-\t\tmsleep(100);\n-\t}\n+\tif (bridge)\n+\t\tlist_for_each_entry(port, &bridge->ports, list)\n+\t\t\tif (port->reset) {\n+\t\t\t\tmsleep(PCIE_T_PVPERL_MS);\n+\t\t\t\tgpiod_set_value_cansleep(port->reset, 0);\n+\t\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n+\t\t\t}\n \n \treturn 0;\n }\n@@ -1642,11 +1653,39 @@ static const struct dev_pm_ops imx_pcie_pm_ops = {\n \t\t\t\t imx_pcie_resume_noirq)\n };\n \n+static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)\n+{\n+\tstruct device *dev = pcie->pci->dev;\n+\tstruct pci_host_bridge *bridge = pcie->pci->pp.bridge;\n+\tstruct pci_host_port *port;\n+\tstruct gpio_desc *reset;\n+\n+\tif (!bridge) {\n+\t\tdev_err(dev, \"Bridge not allocated yet\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treset = devm_gpiod_get_optional(dev, \"reset\", GPIOD_OUT_HIGH);\n+\tif (IS_ERR(reset))\n+\t\treturn PTR_ERR(reset);\n+\n+\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n+\tif (!port)\n+\t\treturn -ENOMEM;\n+\n+\tport->reset = reset;\n+\tINIT_LIST_HEAD(&port->list);\n+\tlist_add_tail(&port->list, &bridge->ports);\n+\n+\treturn 0;\n+}\n+\n static int imx_pcie_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n \tstruct dw_pcie *pci;\n \tstruct imx_pcie *imx_pcie;\n+\tstruct pci_host_bridge *bridge;\n \tstruct device_node *np;\n \tstruct device_node *node = dev->of_node;\n \tint i, ret, domain;\n@@ -1688,12 +1727,26 @@ static int imx_pcie_probe(struct platform_device *pdev)\n \t\t\treturn PTR_ERR(imx_pcie->phy_base);\n \t}\n \n-\t/* Fetch GPIOs */\n-\timx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, \"reset\", GPIOD_OUT_HIGH);\n-\tif (IS_ERR(imx_pcie->reset_gpiod))\n-\t\treturn dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),\n-\t\t\t\t \"unable to get reset gpio\\n\");\n-\tgpiod_set_consumer_name(imx_pcie->reset_gpiod, \"PCIe reset\");\n+\t/* For RC mode, allocate bridge early so we can parse Root Ports. */\n+\tif (imx_pcie->drvdata->mode != DW_PCIE_EP_TYPE) {\n+\t\tbridge = devm_pci_alloc_host_bridge(dev, 0);\n+\t\tif (!bridge)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tpci->pp.bridge = bridge;\n+\n+\t\t/* Parse Root Port nodes */\n+\t\tret = pci_host_common_parse_ports(bridge);\n+\t\tif (ret) {\n+\t\t\tif (ret != -ENOENT)\n+\t\t\t\treturn dev_err_probe(dev, ret, \"Failed to parse Root Port\\n\");\n+\n+\t\t\t/* Fallback to legacy binding for DT backwards compatibility */\n+\t\t\tret = imx_pcie_parse_legacy_binding(imx_pcie);\n+\t\t\tif (ret)\n+\t\t\t\treturn dev_err_probe(dev, ret, \"Unable to get reset gpio\\n\");\n+\t\t}\n+\t}\n \n \t/* Fetch clocks */\n \timx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);\n", "prefixes": [ "V5", "04/12" ] }