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GET /api/patches/2196098/?format=api
{ "id": 2196098, "url": "http://patchwork.ozlabs.org/api/patches/2196098/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260212204352.1044699-10-zycai@linux.ibm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212204352.1044699-10-zycai@linux.ibm.com>", "list_archive_url": null, "date": "2026-02-12T20:43:30", "name": "[v8,09/30] s390x/diag: Implement DIAG 320 subcode 2", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fdcd7c305e3603721d2b6084f0330aa61fe684e4", "submitter": { "id": 90643, "url": "http://patchwork.ozlabs.org/api/people/90643/?format=api", "name": "Zhuoying Cai", "email": "zycai@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260212204352.1044699-10-zycai@linux.ibm.com/mbox/", "series": [ { "id": 492021, "url": "http://patchwork.ozlabs.org/api/series/492021/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492021", "date": "2026-02-12T20:43:36", "name": "Secure IPL Support for SCSI Scheme of virtio-blk/virtio-scsi Devices", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/492021/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196098/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196098/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=NzVWsasd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc\n :content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=pp1; bh=6uitRppzEdjvZfhKc\n invYcKa6N4DDSAzGzVxk41ZFZk=; b=NzVWsasdXBIrcLkhlRmWHW6uPPJck/SWO\n UkwZ6tHuDrLDfrrJmRZVO+rncyeXDgWlWquQ/hXmFGVxaGglbS846I3dWel+/9fr\n wR35dypRqFrCesYpnSWzvf/qouH8m+xpbfppXwYy7IAS/Mvnek/l25hU0x/hly8T\n lNxzEJ9LNvhiVKEGCt1ig/+EWnMI5ovAfbQiM6E2BMBQC+yDjxFPi+pEMf9FdjGz\n 3J6YTsVdNctIwHj1PpuW6z1O55ygWcUNwXvkx+EkbUGV5QY/6gTbbDBif1JoHue+\n /AQpMJN4ft38jCCkMg2I25sf8a3En1iro4AbenjUfqeNRKg/YZjcA==", "From": "Zhuoying Cai <zycai@linux.ibm.com>", "To": "thuth@redhat.com, berrange@redhat.com, richard.henderson@linaro.org,\n jrossi@linux.ibm.com, qemu-s390x@nongnu.org, qemu-devel@nongnu.org", "Cc": "david@kernel.org, walling@linux.ibm.com, jjherne@linux.ibm.com,\n pasic@linux.ibm.com, borntraeger@linux.ibm.com, farman@linux.ibm.com,\n mjrosato@linux.ibm.com, iii@linux.ibm.com, eblake@redhat.com,\n armbru@redhat.com, zycai@linux.ibm.com, alifm@linux.ibm.com,\n brueckner@linux.ibm.com", "Subject": "[PATCH v8 09/30] s390x/diag: Implement DIAG 320 subcode 2", "Date": "Thu, 12 Feb 2026 15:43:30 -0500", "Message-ID": "<20260212204352.1044699-10-zycai@linux.ibm.com>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20260212204352.1044699-1-zycai@linux.ibm.com>", "References": "<20260212204352.1044699-1-zycai@linux.ibm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-GUID": "zpa33YNch1DUz10RabHkAzNJMjir94yH", "X-Proofpoint-ORIG-GUID": "zpa33YNch1DUz10RabHkAzNJMjir94yH", "X-Authority-Analysis": "v=2.4 cv=JdWxbEKV c=1 sm=1 tr=0 ts=698e3b9e cx=c_pps\n a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17\n a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22\n a=GgsMoib0sEa3-_RKJdDe:22 a=VnNF1IyMAAAA:8 a=61SagOTT2uTz2cUW2SIA:9", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEyMDE1NyBTYWx0ZWRfX5iI0km7eoGvm\n j6GyB4Q/GfpncRimjlZbgDCRxd3yCUFpN76JHDIFPSP/QKRduKp5wNrCzJUmk1/orCZi9ZigA2w\n b/k0qdKohJHrycWPue2N3+fDB/ZHR1QEkvS+PM4BOB2EGXmrQ1DxvCOIFn4C1tCXNSzP+y4vDa7\n OoOzsyawj4418vM4sqYQ5eFnmdlwpp6CBeGWs8Q52guJr0XvrvXPBToXrsOPQZbpmFXC3Su4hxt\n znZ18GVUXxRQ+nO51WHITy+INOR59Mlbg+/PidyioeHoNDRqN6LY7z3tJbPhnxdOBt9Ivqw9q+B\n AKelnyB1lu05T7Ur6/kdScZRd8Nype3jWT9i3mIZUWbx6Y9tczNcixqQ7bNc/yLsOCFQ8AE5ejz\n M6ciavCTi95QTMFbipFP/ZrVrTmhXk7yOrEVWYCTdDWsFZ1Ooc68FO8dVWJZwRYSACfcOMTIy8E\n eYc+L1WjOCvFTbPMfpA==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-12_05,2026-02-12_03,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 clxscore=1015 impostorscore=0 bulkscore=0\n lowpriorityscore=0 suspectscore=0 adultscore=0 spamscore=0 malwarescore=0\n phishscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2602120157", "Received-SPF": "pass client-ip=148.163.158.5; envelope-from=zycai@linux.ibm.com;\n helo=mx0b-001b2d01.pphosted.com", "X-Spam_score_int": "-26", "X-Spam_score": "-2.7", "X-Spam_bar": "--", "X-Spam_report": "(-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "DIAG 320 subcode 2 provides verification-certificates (VCs) that are in the\ncertificate store. Only X509 certificates in DER format and SHA-256 hash\ntype are recognized.\n\nThe subcode value is denoted by setting the second-left-most bit\nof an 8-byte field.\n\nThe Verification Certificate Block (VCB) contains the output data\nwhen the operation completes successfully. It includes a common\nheader followed by zero or more Verification Certificate Entries (VCEs),\ndepending on the VCB input length and the VC range (from the first VC\nindex to the last VC index) in the certificate store.\n\nEach VCE contains information about a certificate retrieved from\nthe S390IPLCertificateStore, such as the certificate name, key type,\nkey ID length, hash length, and the raw certificate data.\nThe key ID and hash are extracted from the raw certificate by the crypto API.\n\nNote: SHA2-256 VC hash type is required for retrieving the hash\n(fingerprint) of the certificate.\n\nSigned-off-by: Zhuoying Cai <zycai@linux.ibm.com>\n---\n docs/specs/s390x-secure-ipl.rst | 22 +++\n hw/s390x/cert-store.h | 3 +-\n include/hw/s390x/ipl/diag320.h | 50 +++++\n target/s390x/diag.c | 328 +++++++++++++++++++++++++++++++-\n 4 files changed, 400 insertions(+), 3 deletions(-)", "diff": "diff --git a/docs/specs/s390x-secure-ipl.rst b/docs/specs/s390x-secure-ipl.rst\nindex d3ece8a82d..22da589162 100644\n--- a/docs/specs/s390x-secure-ipl.rst\n+++ b/docs/specs/s390x-secure-ipl.rst\n@@ -38,3 +38,25 @@ Subcode 1 - query verification certificate storage information\n The output is returned in the verification-certificate-storage-size block\n (VCSSB). A VCSSB length of 4 indicates that no certificates are available\n in the CS.\n+\n+Subcode 2 - store verification certificates\n+ Provides VCs that are in the certificate store.\n+\n+ The output is provided in a VCB, which includes a common header followed by\n+ zero or more verification-certificate entries (VCEs).\n+\n+ The instruction expects the cert store to\n+ maintain an origin of 1 for the index (i.e. a retrieval of the first\n+ certificate in the store should be denoted by setting first-VC to 1).\n+\n+ The first-VC index and last-VC index fields of VCB specify the range of VCs\n+ to be stored by subcode 2. Stored count and remained count fields specify\n+ the number of VCs stored and could not be stored in the VCB due to\n+ insufficient storage specified in the VCB input length field.\n+\n+ Each VCE contains a header followed by information extracted from a\n+ certificate within the certificate store. The information includes:\n+ key-id, hash, and certificate data. This information is stored\n+ contiguously in a VCE (with zero-padding). Following the header, the\n+ key-id is immediately stored. The hash and certificate data follow and\n+ may be accessed via the respective offset fields stored in the VCE.\ndiff --git a/hw/s390x/cert-store.h b/hw/s390x/cert-store.h\nindex 50e36e2389..bacd353ead 100644\n--- a/hw/s390x/cert-store.h\n+++ b/hw/s390x/cert-store.h\n@@ -11,10 +11,9 @@\n #define HW_S390_CERT_STORE_H\n \n #include \"hw/s390x/ipl/qipl.h\"\n+#include \"hw/s390x/ipl/diag320.h\"\n #include \"crypto/x509-utils.h\"\n \n-#define CERT_NAME_MAX_LEN 64\n-\n #define CERT_KEY_ID_LEN QCRYPTO_HASH_DIGEST_LEN_SHA256\n #define CERT_HASH_LEN QCRYPTO_HASH_DIGEST_LEN_SHA256\n \ndiff --git a/include/hw/s390x/ipl/diag320.h b/include/hw/s390x/ipl/diag320.h\nindex 6e4779c699..9ed5fc0e5d 100644\n--- a/include/hw/s390x/ipl/diag320.h\n+++ b/include/hw/s390x/ipl/diag320.h\n@@ -12,19 +12,32 @@\n \n #define DIAG_320_SUBC_QUERY_ISM 0\n #define DIAG_320_SUBC_QUERY_VCSI 1\n+#define DIAG_320_SUBC_STORE_VC 2\n \n #define DIAG_320_RC_OK 0x0001\n #define DIAG_320_RC_NOT_SUPPORTED 0x0102\n #define DIAG_320_RC_INVAL_VCSSB_LEN 0x0202\n+#define DIAG_320_RC_INVAL_VCB_LEN 0x0204\n+#define DIAG_320_RC_BAD_RANGE 0x0302\n \n #define DIAG_320_ISM_QUERY_SUBCODES 0x80000000\n #define DIAG_320_ISM_QUERY_VCSI 0x40000000\n+#define DIAG_320_ISM_STORE_VC 0x20000000\n \n #define VCSSB_NO_VC 4\n #define VCSSB_MIN_LEN 128\n #define VCE_HEADER_LEN 128\n+#define VCE_INVALID_LEN 72\n #define VCB_HEADER_LEN 64\n \n+#define CERT_NAME_MAX_LEN 64\n+\n+#define DIAG_320_VCE_FLAGS_VALID 0x80\n+#define DIAG_320_VCE_KEYTYPE_SELF_DESCRIBING 0\n+#define DIAG_320_VCE_KEYTYPE_ECDSA_P521 1\n+#define DIAG_320_VCE_FORMAT_X509_DER 1\n+#define DIAG_320_VCE_HASHTYPE_SHA2_256 1\n+\n struct VCStorageSizeBlock {\n uint32_t length;\n uint8_t reserved0[3];\n@@ -39,4 +52,41 @@ struct VCStorageSizeBlock {\n };\n typedef struct VCStorageSizeBlock VCStorageSizeBlock;\n \n+struct VCBlock {\n+ uint32_t in_len;\n+ uint32_t reserved0;\n+ uint16_t first_vc_index;\n+ uint16_t last_vc_index;\n+ uint32_t reserved1[5];\n+ uint32_t out_len;\n+ uint8_t reserved2[4];\n+ uint16_t stored_ct;\n+ uint16_t remain_ct;\n+ uint32_t reserved3[5];\n+ uint8_t vce_buf[];\n+};\n+typedef struct VCBlock VCBlock;\n+\n+struct VCEntry {\n+ uint32_t len;\n+ uint8_t flags;\n+ uint8_t key_type;\n+ uint16_t cert_idx;\n+ uint8_t name[CERT_NAME_MAX_LEN];\n+ uint8_t format;\n+ uint8_t reserved0;\n+ uint16_t keyid_len;\n+ uint8_t reserved1;\n+ uint8_t hash_type;\n+ uint16_t hash_len;\n+ uint32_t reserved2;\n+ uint32_t cert_len;\n+ uint32_t reserved3[2];\n+ uint16_t hash_offset;\n+ uint16_t cert_offset;\n+ uint32_t reserved4[7];\n+ uint8_t cert_buf[];\n+};\n+typedef struct VCEntry VCEntry;\n+\n #endif\ndiff --git a/target/s390x/diag.c b/target/s390x/diag.c\nindex 3c7e64eb05..e70375d2a9 100644\n--- a/target/s390x/diag.c\n+++ b/target/s390x/diag.c\n@@ -17,6 +17,7 @@\n #include \"s390x-internal.h\"\n #include \"hw/watchdog/wdt_diag288.h\"\n #include \"system/cpus.h\"\n+#include \"hw/s390x/cert-store.h\"\n #include \"hw/s390x/ipl.h\"\n #include \"hw/s390x/ipl/diag320.h\"\n #include \"hw/s390x/s390-virtio-ccw.h\"\n@@ -24,6 +25,7 @@\n #include \"kvm/kvm_s390x.h\"\n #include \"target/s390x/kvm/pv.h\"\n #include \"qemu/error-report.h\"\n+#include \"crypto/x509-utils.h\"\n \n \n static inline bool diag_parm_addr_valid(uint64_t addr, size_t size, bool write)\n@@ -235,8 +237,324 @@ static int handle_diag320_query_vcsi(S390CPU *cpu, uint64_t addr, uint64_t r1,\n return DIAG_320_RC_OK;\n }\n \n+static bool is_cert_valid(const S390IPLCertificate *cert)\n+{\n+ int rc;\n+ Error *err = NULL;\n+\n+ rc = qcrypto_x509_check_cert_times(cert->raw, cert->size, &err);\n+ if (rc != 0) {\n+ error_report_err(err);\n+ return false;\n+ }\n+\n+ return true;\n+}\n+\n+static int handle_key_id(VCEntry *vce, const S390IPLCertificate *cert)\n+{\n+ int rc;\n+ g_autofree unsigned char *key_id_data = NULL;\n+ size_t key_id_len;\n+ Error *err = NULL;\n+\n+ rc = qcrypto_x509_get_cert_key_id(cert->raw, cert->size,\n+ QCRYPTO_HASH_ALGO_SHA256,\n+ &key_id_data, &key_id_len, &err);\n+ if (rc < 0) {\n+ error_report_err(err);\n+ return -1;\n+ }\n+\n+ if (VCE_HEADER_LEN + key_id_len > be32_to_cpu(vce->len)) {\n+ error_report(\"Unable to write key ID: exceeds buffer bounds\");\n+ return -1;\n+ }\n+\n+ vce->keyid_len = cpu_to_be16(key_id_len);\n+\n+ memcpy(vce->cert_buf, key_id_data, key_id_len);\n+\n+ return 0;\n+}\n+\n+static int handle_hash(VCEntry *vce, const S390IPLCertificate *cert,\n+ uint16_t keyid_field_len)\n+{\n+ int rc;\n+ uint16_t hash_offset;\n+ g_autofree void *hash_data = NULL;\n+ size_t hash_len;\n+ Error *err = NULL;\n+\n+ hash_len = CERT_HASH_LEN;\n+ hash_data = g_malloc0(hash_len);\n+ rc = qcrypto_get_x509_cert_fingerprint(cert->raw, cert->size,\n+ QCRYPTO_HASH_ALGO_SHA256,\n+ hash_data, &hash_len, &err);\n+ if (rc < 0) {\n+ error_report_err(err);\n+ return -1;\n+ }\n+\n+ hash_offset = VCE_HEADER_LEN + keyid_field_len;\n+ if (hash_offset + hash_len > be32_to_cpu(vce->len)) {\n+ error_report(\"Unable to write hash: exceeds buffer bounds\");\n+ return -1;\n+ }\n+\n+ vce->hash_len = cpu_to_be16(hash_len);\n+ vce->hash_type = DIAG_320_VCE_HASHTYPE_SHA2_256;\n+ vce->hash_offset = cpu_to_be16(hash_offset);\n+\n+ memcpy((uint8_t *)vce + hash_offset, hash_data, hash_len);\n+\n+ return 0;\n+}\n+\n+static int handle_cert(VCEntry *vce, const S390IPLCertificate *cert,\n+ uint16_t hash_field_len)\n+{\n+ int rc;\n+ uint16_t cert_offset;\n+ g_autofree uint8_t *cert_der = NULL;\n+ size_t der_size;\n+ Error *err = NULL;\n+\n+ rc = qcrypto_x509_convert_cert_der(cert->raw, cert->size,\n+ &cert_der, &der_size, &err);\n+ if (rc < 0) {\n+ error_report_err(err);\n+ return -1;\n+ }\n+\n+ cert_offset = be16_to_cpu(vce->hash_offset) + hash_field_len;\n+ if (cert_offset + der_size > be32_to_cpu(vce->len)) {\n+ error_report(\"Unable to write certificate: exceeds buffer bounds\");\n+ return -1;\n+ }\n+\n+ vce->format = DIAG_320_VCE_FORMAT_X509_DER;\n+ vce->cert_len = cpu_to_be32(der_size);\n+ vce->cert_offset = cpu_to_be16(cert_offset);\n+\n+ memcpy((uint8_t *)vce + cert_offset, cert_der, der_size);\n+\n+ return 0;\n+}\n+\n+static int get_key_type(const S390IPLCertificate *cert)\n+{\n+ int rc;\n+ Error *err = NULL;\n+\n+ rc = qcrypto_x509_check_ecc_curve_p521(cert->raw, cert->size, &err);\n+ if (rc == -1) {\n+ error_report_err(err);\n+ return -1;\n+ }\n+\n+ return (rc == 1) ? DIAG_320_VCE_KEYTYPE_ECDSA_P521 :\n+ DIAG_320_VCE_KEYTYPE_SELF_DESCRIBING;\n+}\n+\n+static int build_vce_header(VCEntry *vce, const S390IPLCertificate *cert, int idx)\n+{\n+ int key_type;\n+\n+ vce->len = cpu_to_be32(VCE_HEADER_LEN);\n+ vce->cert_idx = cpu_to_be16(idx + 1);\n+ memcpy(vce->name, cert->name, CERT_NAME_MAX_LEN);\n+\n+ key_type = get_key_type(cert);\n+ if (key_type == -1) {\n+ return -1;\n+ }\n+ vce->key_type = key_type;\n+\n+ return 0;\n+}\n+\n+static int build_vce_data(VCEntry *vce, const S390IPLCertificate *cert)\n+{\n+ uint16_t keyid_field_len;\n+ uint16_t hash_field_len;\n+ uint32_t cert_field_len;\n+ uint32_t vce_len;\n+ int rc;\n+\n+ rc = handle_key_id(vce, cert);\n+ if (rc) {\n+ return -1;\n+ }\n+ keyid_field_len = ROUND_UP(be16_to_cpu(vce->keyid_len), 4);\n+\n+ rc = handle_hash(vce, cert, keyid_field_len);\n+ if (rc) {\n+ return -1;\n+ }\n+ hash_field_len = ROUND_UP(be16_to_cpu(vce->hash_len), 4);\n+\n+ rc = handle_cert(vce, cert, hash_field_len);\n+ if (rc || !is_cert_valid(cert)) {\n+ return -1;\n+ }\n+ cert_field_len = ROUND_UP(be32_to_cpu(vce->cert_len), 4);\n+\n+ vce_len = VCE_HEADER_LEN + keyid_field_len + hash_field_len + cert_field_len;\n+ if (vce_len > be32_to_cpu(vce->len)) {\n+ return -1;\n+ }\n+\n+ vce->flags |= DIAG_320_VCE_FLAGS_VALID;\n+\n+ /* Update vce length to reflect the actual size used by vce */\n+ vce->len = cpu_to_be32(vce_len);\n+\n+ return 0;\n+}\n+\n+static VCEntry *diag_320_build_vce(const S390IPLCertificate *cert, int idx)\n+{\n+ g_autofree VCEntry *vce = NULL;\n+ uint32_t vce_max_size;\n+ int rc;\n+\n+ /*\n+ * Each field of the VCE is word-aligned.\n+ * Allocate enough space for the largest possible size for this VCE.\n+ * As the certificate fields (key-id, hash, data) are parsed, the\n+ * VCE's length field will be updated accordingly.\n+ */\n+ vce_max_size = VCE_HEADER_LEN +\n+ ROUND_UP(CERT_KEY_ID_LEN, 4) +\n+ ROUND_UP(CERT_HASH_LEN, 4) +\n+ ROUND_UP(cert->der_size, 4);\n+\n+ vce = g_malloc0(vce_max_size);\n+ rc = build_vce_header(vce, cert, idx);\n+ if (rc) {\n+ vce->len = cpu_to_be32(VCE_INVALID_LEN);\n+ goto out;\n+ }\n+\n+ vce->len = cpu_to_be32(vce_max_size);\n+ rc = build_vce_data(vce, cert);\n+ if (rc) {\n+ vce->len = cpu_to_be32(VCE_INVALID_LEN);\n+ }\n+\n+out:\n+ return g_steal_pointer(&vce);\n+}\n+\n+static int handle_diag320_store_vc(S390CPU *cpu, uint64_t addr, uint64_t r1, uintptr_t ra,\n+ S390IPLCertificateStore *cs)\n+{\n+ g_autofree VCBlock *vcb = NULL;\n+ size_t entry_offset;\n+ size_t remaining_space;\n+ uint32_t vce_len;\n+ uint16_t first_vc_index;\n+ uint16_t last_vc_index;\n+ int cs_start_index;\n+ int cs_end_index;\n+ uint32_t in_len;\n+\n+ vcb = g_new0(VCBlock, 1);\n+ if (s390_cpu_virt_mem_read(cpu, addr, r1, vcb, sizeof(*vcb))) {\n+ s390_cpu_virt_mem_handle_exc(cpu, ra);\n+ return -1;\n+ }\n+\n+ in_len = be32_to_cpu(vcb->in_len);\n+ first_vc_index = be16_to_cpu(vcb->first_vc_index);\n+ last_vc_index = be16_to_cpu(vcb->last_vc_index);\n+\n+ if (in_len % TARGET_PAGE_SIZE != 0) {\n+ return DIAG_320_RC_INVAL_VCB_LEN;\n+ }\n+\n+ if (first_vc_index > last_vc_index) {\n+ return DIAG_320_RC_BAD_RANGE;\n+ }\n+\n+ vcb->out_len = VCB_HEADER_LEN;\n+\n+ /*\n+ * DIAG 320 subcode 2 expects to query a certificate store that\n+ * maintains an index origin of 1. However, the S390IPLCertificateStore\n+ * maintains an index origin of 0. Thus, the indices must be adjusted\n+ * for correct access into the cert store. A couple of special cases\n+ * must also be accounted for.\n+ */\n+\n+ /* Both indices are 0; return header with no certs */\n+ if (first_vc_index == 0 && last_vc_index == 0) {\n+ goto out;\n+ }\n+\n+ /* Normalize indices */\n+ cs_start_index = (first_vc_index == 0) ? 0 : first_vc_index - 1;\n+ cs_end_index = last_vc_index - 1;\n+\n+ /* Requested range is outside the cert store; return header with no certs */\n+ if (cs_start_index >= cs->count || cs_end_index >= cs->count) {\n+ goto out;\n+ }\n+\n+ entry_offset = VCB_HEADER_LEN;\n+ remaining_space = in_len - VCB_HEADER_LEN;\n+\n+ for (int i = cs_start_index; i <= cs_end_index; i++) {\n+ VCEntry *vce;\n+ const S390IPLCertificate *cert = &cs->certs[i];\n+\n+ vce = diag_320_build_vce(cert, i);\n+ vce_len = be32_to_cpu(vce->len);\n+\n+ /*\n+ * If there is no more space to store the cert,\n+ * set the remaining verification cert count and\n+ * break early.\n+ */\n+ if (remaining_space < vce_len) {\n+ vcb->remain_ct = cpu_to_be16(last_vc_index - i);\n+ g_free(vce);\n+ break;\n+ }\n+\n+ /* Write VCE */\n+ if (s390_cpu_virt_mem_write(cpu, addr + entry_offset, r1, vce, vce_len)) {\n+ s390_cpu_virt_mem_handle_exc(cpu, ra);\n+ g_free(vce);\n+ return -1;\n+ }\n+\n+ entry_offset += vce_len;\n+ vcb->out_len += vce_len;\n+ remaining_space -= vce_len;\n+ vcb->stored_ct++;\n+\n+ g_free(vce);\n+ }\n+ vcb->stored_ct = cpu_to_be16(vcb->stored_ct);\n+\n+out:\n+ vcb->out_len = cpu_to_be32(vcb->out_len);\n+\n+ if (s390_cpu_virt_mem_write(cpu, addr, r1, vcb, VCB_HEADER_LEN)) {\n+ s390_cpu_virt_mem_handle_exc(cpu, ra);\n+ return -1;\n+ }\n+\n+ return DIAG_320_RC_OK;\n+}\n+\n QEMU_BUILD_BUG_MSG(sizeof(VCStorageSizeBlock) != VCSSB_MIN_LEN,\n \"size of VCStorageSizeBlock is wrong\");\n+QEMU_BUILD_BUG_MSG(sizeof(VCBlock) != VCB_HEADER_LEN, \"size of VCBlock is wrong\");\n+QEMU_BUILD_BUG_MSG(sizeof(VCEntry) != VCE_HEADER_LEN, \"size of VCEntry is wrong\");\n \n void handle_diag_320(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)\n {\n@@ -267,7 +585,8 @@ void handle_diag_320(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)\n * for now.\n */\n uint32_t ism_word0 = cpu_to_be32(DIAG_320_ISM_QUERY_SUBCODES |\n- DIAG_320_ISM_QUERY_VCSI);\n+ DIAG_320_ISM_QUERY_VCSI |\n+ DIAG_320_ISM_STORE_VC);\n \n if (s390_cpu_virt_mem_write(cpu, addr, r1, &ism_word0, sizeof(ism_word0))) {\n s390_cpu_virt_mem_handle_exc(cpu, ra);\n@@ -293,6 +612,13 @@ void handle_diag_320(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)\n }\n env->regs[r1 + 1] = rc;\n break;\n+ case DIAG_320_SUBC_STORE_VC:\n+ rc = handle_diag320_store_vc(cpu, addr, r1, ra, cs);\n+ if (rc == -1) {\n+ return;\n+ }\n+ env->regs[r1 + 1] = rc;\n+ break;\n default:\n env->regs[r1 + 1] = DIAG_320_RC_NOT_SUPPORTED;\n break;\n", "prefixes": [ "v8", "09/30" ] }