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GET /api/patches/2196050/?format=api
{ "id": 2196050, "url": "http://patchwork.ozlabs.org/api/patches/2196050/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260212191818.3625264-2-dcostantino@meta.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212191818.3625264-2-dcostantino@meta.com>", "list_archive_url": null, "date": "2026-02-12T19:18:17", "name": "[1/2] PCI/DPC: Clear Interrupt Status in dpc_reset_link()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ab7fbf5992e3a7ad69b477d1d0254bfd003f2d04", "submitter": { "id": 92636, "url": "http://patchwork.ozlabs.org/api/people/92636/?format=api", "name": "Danielle Costantino", "email": "dcostantino@meta.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260212191818.3625264-2-dcostantino@meta.com/mbox/", "series": [ { "id": 492009, "url": "http://patchwork.ozlabs.org/api/series/492009/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492009", "date": "2026-02-12T19:18:16", "name": "PCI/DPC: Fix EDR recovery path issues", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492009/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196050/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196050/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47224-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=meta.com header.i=@meta.com header.a=rsa-sha256\n header.s=s2048-2025-q2 header.b=wEs8uEwW;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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a=rsa-sha256; c=relaxed/relaxed; d=meta.com; h=cc\n\t:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to; s=s2048-2025-q2;\n\t bh=cswab+TVCRhY8hUaODrd2b4Mvnm+yEHqtCJfechSy34=; b=wEs8uEwWqQrM\n\tbKNGdbQe/l2hijgYgtqpNzKm9VQvaOoziugj20eIX0O1FMiRBmuwARIa1M2A1iH8\n\tDyLyeVYSpp8FQ26m8vu4VdogusWa8FnO9b9M/L/cn4VmNiDqlknQgrYSGm2jKfz/\n\t1sWuKpSC6e2rG/GbGKjuG4370FVx165JkvJhpRcEMP9zoj62Fqa9UCF6EiFKD2rm\n\t0Y5go2mweZH4dcp+eS3CYhmjFwRhgQrvLSDoJG7Oba8RAO/51T1t4fDpf1ZNwzr7\n\tsIQ3QjiyYG02ut057LpbzWFTb2YN83lsdXE6Efjd1JblbGpByOgAspcAi3nRHOgH\n\tqSxxmWC/RQ==", "From": "Danielle Costantino <dcostantino@meta.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>", "CC": "Keith Busch <kbusch@kernel.org>,\n Kuppuswamy Sathyanarayanan\n\t<sathyanarayanan.kuppuswamy@linux.intel.com>,\n Lukas Wunner <lukas@wunner.de>,\n Mahesh J Salgaonkar <mahesh@linux.ibm.com>,\n Oliver O'Halloran\n\t<oohall@gmail.com>, <linux-pci@vger.kernel.org>,\n Danielle Costantino\n\t<dcostantino@meta.com>", "Subject": "[PATCH 1/2] PCI/DPC: Clear Interrupt Status in dpc_reset_link()", "Date": "Thu, 12 Feb 2026 11:18:17 -0800", "Message-ID": "<20260212191818.3625264-2-dcostantino@meta.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260212191818.3625264-1-dcostantino@meta.com>", "References": "<20260212191818.3625264-1-dcostantino@meta.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "wTvAF_MHhQr8BDRarAI9UD3AihSB45yc", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEyMDE0OSBTYWx0ZWRfX8sFI5AEwjH2Y\n MJxwyZbotbFyXH/QIvMAQ7+xx8GE7LSC9cW2sJJktnIfZRUZJ6pSI5PO7+7K24lTEzWz94TN25t\n ozIKG5sjOVlY8PZoUJVNuSmYEnw2w5rYDQe8/BYTzqJC4cmvvcp46p6mBC0hkoc0BTS5/Qcz3o7\n iOTtmkxz1/mRQISu5IEq0mwK/mc+QkxtlwMIGB/ypuGbxQocubGHSlY4imjSE23yfiyZZVQ60kN\n hDmMjmOn+PaWTFS+ViORB6W6abGs0ci13ZBFFtvafzUZqTd5PsNZuCkpCuhyyxdm1LONFwznn9V\n dXW3aAVwWW9pmLeytfTEZ6Nio2/thq1sYOvCxbf0NX071bRVJnwmB2TxSN9v69rmADqvCVQhs8a\n MOgpNstu8YvVaoMQcfIvY98aqfQ/h0sA8lSQhEtYiKV+ASGr3OIx94gRsZQ4RP7lf/6irUAKsUe\n vmyOJ7XPgHwBgUCapSA==", "X-Proofpoint-ORIG-GUID": "wTvAF_MHhQr8BDRarAI9UD3AihSB45yc", "X-Authority-Analysis": "v=2.4 cv=brNBxUai c=1 sm=1 tr=0 ts=698e2791 cx=c_pps\n a=CB4LiSf2rd0gKozIdrpkBw==:117 a=CB4LiSf2rd0gKozIdrpkBw==:17\n a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22\n a=GgsMoib0sEa3-_RKJdDe:22 a=VabnemYjAAAA:8 a=aYVGL-vDrxpcnfgFjpMA:9\n a=gKebqoRLp9LExxC7YDUY:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-12_05,2026-02-12_03,2025-10-01_01" }, "content": "In the native DPC interrupt path, dpc_irq() clears\nPCI_EXP_DPC_STATUS_INTERRUPT before scheduling the threaded handler\nthat eventually calls dpc_reset_link(). However, in the firmware-first\nEDR path, dpc_irq() is never invoked -- firmware owns the DPC interrupt\nand notifies the OS via an ACPI EDR notification. dpc_reset_link() is\nthen called directly from edr_handle_event() via pcie_do_recovery().\n\nBecause dpc_reset_link() only clears PCI_EXP_DPC_STATUS_TRIGGER, the\nInterrupt Status bit (bit 3) is left set permanently after every EDR\nevent.\n\nClear PCI_EXP_DPC_STATUS_INTERRUPT alongside PCI_EXP_DPC_STATUS_TRIGGER\nin dpc_reset_link(). Both bits are RW1C in the DPC Status register per\nPCIe r6.1, sec 7.9.14.5, so writing them together is safe. The native\npath is unaffected because dpc_irq() has already cleared the Interrupt\nStatus bit before dpc_reset_link() runs.\n\nFixes: aea47413e7ce (\"PCI/DPC: Expose dpc_process_error(), dpc_reset_link() for use by EDR\")\nSigned-off-by: Danielle Costantino <dcostantino@meta.com>\n---\n drivers/pci/pcie/dpc.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c\nindex fc18349614d7..9baa2345e33e 100644\n--- a/drivers/pci/pcie/dpc.c\n+++ b/drivers/pci/pcie/dpc.c\n@@ -171,8 +171,16 @@ pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)\n \t\tgoto out;\n \t}\n \n+\t/*\n+\t * Clear both DPC Trigger Status and DPC Interrupt Status. In the\n+\t * native DPC path, dpc_irq() already clears Interrupt Status before\n+\t * the threaded handler runs. But in the EDR (firmware-first) path,\n+\t * dpc_irq() is never called, so Interrupt Status must be cleared\n+\t * here to prevent it from remaining stale indefinitely.\n+\t */\n \tpci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,\n-\t\t\t PCI_EXP_DPC_STATUS_TRIGGER);\n+\t\t\t PCI_EXP_DPC_STATUS_TRIGGER |\n+\t\t\t PCI_EXP_DPC_STATUS_INTERRUPT);\n \n \tif (pci_bridge_wait_for_secondary_bus(pdev, \"DPC\")) {\n \t\tclear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);\n", "prefixes": [ "1/2" ] }