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GET /api/patches/2196027/?format=api
{ "id": 2196027, "url": "http://patchwork.ozlabs.org/api/patches/2196027/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260212184330.8B61F2043D@pchp3.se.axis.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212184330.8B61F2043D@pchp3.se.axis.com>", "list_archive_url": null, "date": "2026-02-12T18:43:30", "name": "[committed,1/3] CRIS: Make sure movsf doesn't have two memory operands", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "86ccfe499756708a53745e8c447202c56dbe5033", "submitter": { "id": 78298, "url": "http://patchwork.ozlabs.org/api/people/78298/?format=api", "name": "Hans-Peter Nilsson", "email": "hp@axis.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260212184330.8B61F2043D@pchp3.se.axis.com/mbox/", "series": [ { "id": 492004, "url": "http://patchwork.ozlabs.org/api/series/492004/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=492004", "date": "2026-02-12T18:41:46", "name": "CRIS: A few performance tweaks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492004/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196027/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196027/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=axis.com header.i=@axis.com header.a=rsa-sha256\n header.s=selector1 header.b=ailqf/4O;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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Ip=[195.60.68.100];\n Helo=[mail.axis.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM2PEPF0001C716.eurprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "FRWPR02MB11557", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Experimenting, I noticed movsf could get two memory operands, and\nwhen the pass I was hacking, adjusted both operands, the rtl-ssa\nframework didn't like the situation and signalled failure, for\nexample compiling gcc.c-torture/compile/pr85945.c. While that's\narguably a wart in rtl-ssa and may be a problem by itself, this\nshouldn't happen: one operand should be either a register or\nconstant 0. It usually doesn't matter because RA fixes up\noperands per the constraints. Still, this is low-handing fruit\nfor improved performance, letting the RTL passes work on more\ncorrect information ...and also, a plausible excuse for not also\nhacking rtl-ssa proper. Either way, the port is responsible for\nguarding operand validity, so tweak it. Incidental observation:\nthe two-memory-operands case happened already at expand time.\nThis mem-to-mem situation doesn't happen for movsi, because it has\nspecial precautions to keep one operand a register or const_int 0,\nwhich were added for reasons of condition-code handling. That\nparticular condition, checking for REG_P or the subreg being REG_P\nlooks too restrictive though, not allowing the (subreg mem) case\nthat register_operand deliberately allows.\n\n\t* config/cris/cris.md (SISF): New mode_iterator for SI and SF.\n\t(\"mov<mode>\"): Make \"movsi\" a define_expand to include SFmode by\n\tmeans of the SISF iterator and adjust to also handle SFmode.\n\t(\"*movsf_internal\"): Anonymize \"movsf\"; make it a match-only pattern.\n\tAdd conditions to guard from source and destination both being memory\n\toperands.\n---\n gcc/config/cris/cris.md | 25 ++++++++++++++++---------\n 1 file changed, 16 insertions(+), 9 deletions(-)", "diff": "diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md\nindex 6c5945d3ab56..c18813f306a9 100644\n--- a/gcc/config/cris/cris.md\n+++ b/gcc/config/cris/cris.md\n@@ -173,6 +173,9 @@ (define_attr \"enabled\" \"no,yes\"\n (define_mode_iterator BWD [SI HI QI])\n (define_mode_iterator BWDD [DI SI HI QI])\n \n+;; Need to handle SI and SF similarly, at least in the expander.\n+(define_mode_iterator SISF [SI SF])\n+\n ;; To be able to refer to the same mode_attr for both a multi-mode\n ;; and a mode-specific pattern, we use some singleton iterators.\n (define_mode_iterator DI_ [DI])\n@@ -560,11 +563,11 @@ (define_insn_and_split \"*movdi_insn\"\n \f\n ;; Normal move patterns from SI on.\n \n-(define_expand \"movsi\"\n+(define_expand \"mov<mode>\"\n [(parallel\n [(set\n- (match_operand:SI 0 \"nonimmediate_operand\")\n- (match_operand:SI 1 \"general_operand\"))\n+ (match_operand:SISF 0 \"nonimmediate_operand\")\n+ (match_operand:SISF 1 \"general_operand\"))\n (clobber (reg:CC CRIS_CC0_REGNUM))])]\n \"\"\n {\n@@ -572,14 +575,16 @@ (define_expand \"movsi\"\n input. */\n if (MEM_P (operands[0])\n && ! REG_S_P (operands[1])\n- && operands[1] != const0_rtx\n+ && operands[1] != CONST0_RTX (<MODE>mode)\n && can_create_pseudo_p ())\n- operands[1] = force_reg (SImode, operands[1]);\n+ operands[1] = force_reg (<MODE>mode, operands[1]);\n \n /* At post-reload time, we'll get here for e.g. split multi-mode insns\n with a memory destination. Go directly to the clobber-less variant.\n- FIXME: Also applies to special-register source or destination. */\n- if (reload_completed\n+ FIXME: Also applies to special-register source or destination.\n+ Only do this for integer modes. */\n+ if (SCALAR_INT_MODE_P (<MODE>mode)\n+ && reload_completed\n && (MEM_P (operands[0]) || operands[1] == const0_rtx))\n {\n emit_insn (gen_rtx_SET (operands[0], operands[1]));\n@@ -778,11 +783,13 @@ (define_insn \"movstrictqi\"\n ;; all ones); the worthwhile one is \"0.0\".\n ;; It will use clear, so we know ALL types of immediate 0 never change cc.\n \n-(define_insn \"movsf\"\n+(define_insn \"*movsf_internal\"\n [(set (match_operand:SF 0 \"nonimmediate_operand\" \"=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x\")\n \t(match_operand:SF 1 \"general_operand\" \"r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g\"))\n (clobber (reg:CC CRIS_CC0_REGNUM))]\n- \"\"\n+ \"(register_operand (operands[0], SFmode)\n+ || register_operand (operands[1], SFmode)\n+ || operands[1] == CONST0_RTX (SFmode))\"\n \"@\n move.d %1,%0\n move.d %1,%0\n", "prefixes": [ "committed", "1/3" ] }