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GET /api/patches/2195898/?format=api
{ "id": 2195898, "url": "http://patchwork.ozlabs.org/api/patches/2195898/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-6-linopeng@andestech.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212091326.2240990-6-linopeng@andestech.com>", "list_archive_url": null, "date": "2026-02-12T09:13:23", "name": "[5/8] RISC-V: Plumb altfmt through vsetvl patterns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "40adde9046f57abede821ef40bc34c30f1e0ec92", "submitter": { "id": 92634, "url": "http://patchwork.ozlabs.org/api/people/92634/?format=api", "name": "Lino Hsing-Yu Peng", "email": "linopeng@andestech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-6-linopeng@andestech.com/mbox/", "series": [ { "id": 491947, "url": "http://patchwork.ozlabs.org/api/series/491947/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491947", "date": "2026-02-12T09:13:18", "name": "*** Add RISC-V zvfofp8min intrinsic ***", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491947/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195898/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195898/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n dmarc=permerror header.from=andestech.com", "sourceware.org; spf=pass smtp.mailfrom=andestech.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=60.248.187.195" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fBVK72Zg2z1xqf\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 12 Feb 2026 20:25:47 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 7A9124BA23FF\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 12 Feb 2026 09:25:45 +0000 (GMT)", "from Atcsqr.andestech.com (unknown [60.248.187.195])\n by sourceware.org (Postfix) with ESMTPS id 9E2914B9DB7E\n for <gcc-patches@gcc.gnu.org>; Thu, 12 Feb 2026 09:24:11 +0000 (GMT)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 61C9O6Os011913;\n Thu, 12 Feb 2026 17:24:06 +0800 (+08)\n (envelope-from linopeng@andestech.com)", "from atccpl01.andestech.com (10.0.15.149) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Feb\n 2026 17:24:06 +0800" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 7A9124BA23FF", "OpenDKIM Filter v2.11.0 sourceware.org 9E2914B9DB7E" ], "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 9E2914B9DB7E", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1770888252; cv=none;\n b=BXKCtgZXdFY4Uk87i15fkyZfDBHXm8uNra37ClTW+rQseWwy9YrMHoxGBbj1ghqQvlMasYXUbTKwJiyiIwIb83eq8W0DSowqd36s/ksQOLemZkAdhhYzOY43eJCEkNh9idf1ESR0y0vJDtG8eBVNOWlRUGTOFYy2trUpajTiI24=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1770888252; c=relaxed/simple;\n bh=Krm7n9qdtKKm0kPOaVQr0Ps+2ZqeDQmFnRfZSH6cDLY=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=tKALMiiusHdsCbJzu5PYw4x9VSwGnYrvl2RLLMa/cjUG1xI4whYooqqTQKHorGEl0F00jjXjVC01+5ndsb+qpYojdYCOb5PcbBqvcYZAcUDXl/EKXbUcsGNcJ0BZNhbTy5+sKPUVD1G39cII6MVK/DJ5MJFzo54zdwm0Eyidcn0=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Lino Hsing-Yu Peng <linopeng@andestech.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "Lino Hsing-Yu Peng <linopeng1019@gmail.com>", "Subject": "[PATCH 5/8] RISC-V: Plumb altfmt through vsetvl patterns", "Date": "Thu, 12 Feb 2026 17:13:23 +0800", "Message-ID": "<20260212091326.2240990-6-linopeng@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260212091326.2240990-5-linopeng@andestech.com>", "References": "<20260212091326.2240990-1-linopeng@andestech.com>\n <20260212091326.2240990-2-linopeng@andestech.com>\n <20260212091326.2240990-3-linopeng@andestech.com>\n <20260212091326.2240990-4-linopeng@andestech.com>\n <20260212091326.2240990-5-linopeng@andestech.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.149]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 61C9O6Os011913", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Lino Hsing-Yu Peng <linopeng1019@gmail.com>\n\nThread an explicit altfmt attribute through vsetvl patterns and their\ncallers so vsetvl emission can request e<sew>alt encoding when needed.\nKeep ALTFMT_NONE as the default for existing expansion paths.\n\ngcc/ChangeLog:\n\n\t* config/riscv/vector.md (altfmt): New attribute.\n\t(@vsetvl<mode>, vsetvl_vtype_change_only): Add altfmt operand and\n\temit e%sewalt when requested.\n\t(@vsetvl_discard_result<mode>, @vsetvl<mode>_volatile): Likewise.\n\t(@vsetvl<mode>_no_side_effects, *vsetvldi_no_side_effects_si_extend):\n\tCarry altfmt through attributes.\n\t* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl,\n\tgen_no_side_effects_vsetvl_rtx): Pass ALTFMT_NONE.\n\t* config/riscv/riscv-vsetvl.cc (get_vsetvl_pat): Pass default altfmt.\n\t* config/riscv/riscv-vector-builtins-bases.cc: Include insn-attr.h.\n\t(vsetvl::expand): Add ALTFMT_NONE operand.\n---\n gcc/config/riscv/riscv-v.cc | 8 +-\n .../riscv/riscv-vector-builtins-bases.cc | 4 +\n gcc/config/riscv/riscv-vsetvl.cc | 8 +-\n gcc/config/riscv/vector.md | 74 +++++++++++++------\n 4 files changed, 66 insertions(+), 28 deletions(-)", "diff": "diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc\nindex 29dc3ebccd6..ac102498ad3 100644\n--- a/gcc/config/riscv/riscv-v.cc\n+++ b/gcc/config/riscv/riscv-v.cc\n@@ -866,9 +866,10 @@ void\n emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl)\n {\n unsigned int sew = get_sew (vmode);\n+ rtx altfmt = gen_int_mode (ALTFMT_NONE, Pmode);\n emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),\n-\t\t\t gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,\n-\t\t\t const0_rtx));\n+\t\t\t gen_int_mode (get_vlmul (vmode), Pmode), altfmt,\n+\t\t\t const0_rtx, const0_rtx));\n }\n \n void\n@@ -2506,11 +2507,12 @@ rtx\n gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl)\n {\n unsigned int sew = get_sew (vmode);\n+ rtx altfmt = gen_int_mode (ALTFMT_NONE, Pmode);\n rtx tail_policy = gen_int_mode (get_prefer_tail_policy (), Pmode);\n rtx mask_policy = gen_int_mode (get_prefer_mask_policy (), Pmode);\n return gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, Pmode),\n \t\t\t\t gen_int_mode (get_vlmul (vmode), Pmode),\n-\t\t\t\t tail_policy, mask_policy);\n+\t\t\t\t altfmt, tail_policy, mask_policy);\n }\n \n /* GET VL * 2 rtx. */\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc\nindex 5c68f3a690c..e64729b4adf 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc\n@@ -27,6 +27,7 @@\n #include \"tm_p.h\"\n #include \"memmodel.h\"\n #include \"insn-codes.h\"\n+#include \"insn-attr.h\"\n #include \"optabs.h\"\n #include \"recog.h\"\n #include \"expr.h\"\n@@ -109,6 +110,9 @@ public:\n \te.add_input_operand (Pmode, gen_int_mode (get_vlmul (e8_mode), Pmode));\n }\n \n+ /* ALTFMT_NONE. */\n+ e.add_input_operand (Pmode, gen_int_mode (ALTFMT_NONE, Pmode));\n+\n /* TAIL_ANY. */\n e.add_input_operand (Pmode,\n \t\t\t gen_int_mode (get_prefer_tail_policy (), Pmode));\ndiff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc\nindex e2ba8e1c3d1..c62295ee89b 100644\n--- a/gcc/config/riscv/riscv-vsetvl.cc\n+++ b/gcc/config/riscv/riscv-vsetvl.cc\n@@ -1288,15 +1288,17 @@ public:\n avl = GEN_INT (0);\n rtx sew = gen_int_mode (get_sew (), Pmode);\n rtx vlmul = gen_int_mode (get_vlmul (), Pmode);\n+ rtx altfmt = const0_rtx;\n rtx ta = gen_int_mode (get_ta (), Pmode);\n rtx ma = gen_int_mode (get_ma (), Pmode);\n \n if (change_vtype_only_p ())\n- return gen_vsetvl_vtype_change_only (sew, vlmul, ta, ma);\n+ return gen_vsetvl_vtype_change_only (sew, vlmul, altfmt, ta, ma);\n else if (has_vl () && !ignore_vl)\n- return gen_vsetvl (Pmode, get_vl (), avl, sew, vlmul, ta, ma);\n+ return gen_vsetvl (Pmode, get_vl (), avl, sew, vlmul, altfmt, ta, ma);\n else\n- return gen_vsetvl_discard_result (Pmode, avl, sew, vlmul, ta, ma);\n+ return gen_vsetvl_discard_result (Pmode, avl, sew, vlmul, altfmt, ta,\n+\t\t\t\t\tma);\n }\n \n /* Return true that the non-AVL operands of THIS will be modified\ndiff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md\nindex 219ecdac68b..e76f6a5f277 100644\n--- a/gcc/config/riscv/vector.md\n+++ b/gcc/config/riscv/vector.md\n@@ -60,6 +60,10 @@\n \t (const_string \"true\")]\n \t(const_string \"false\")))\n \n+;; Alternate FP8 format requirement. Most instructions do not care.\n+(define_attr \"altfmt\" \"none,alt,any\"\n+ (const_string \"any\"))\n+\n ;; True if the type is RVV instructions that include VL\n ;; global status register in the use op list.\n ;; The instruction need vector length to be specified is set\n@@ -1667,8 +1671,9 @@\n ;; operands[1]: AVL.\n ;; operands[2]: SEW\n ;; operands[3]: LMUL\n-;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)\n-;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)\n+;; operands[4]: ALTFMT 0 or 1 (none/alt)\n+;; operands[5]: Tail policy 0 or 1 (undisturbed/agnostic)\n+;; operands[6]: Mask policy 0 or 1 (undisturbed/agnostic)\n \n ;; We define 2 types of \"vsetvl*\" instruction patterns:\n \n@@ -1760,7 +1765,8 @@\n \t\t (match_operand 2 \"const_int_operand\" \"i\")\n \t\t (match_operand 3 \"const_int_operand\" \"i\")\n \t\t (match_operand 4 \"const_int_operand\" \"i\")\n-\t\t (match_operand 5 \"const_int_operand\" \"i\")] UNSPEC_VSETVL))\n+\t\t (match_operand 5 \"const_int_operand\" \"i\")\n+\t\t (match_operand 6 \"const_int_operand\" \"i\")] UNSPEC_VSETVL))\n (set (reg:SI VL_REGNUM)\n \t(unspec:SI [(match_dup 1)\n \t\t (match_dup 2)\n@@ -1769,15 +1775,18 @@\n \t(unspec:SI [(match_dup 2)\n \t\t (match_dup 3)\n \t\t (match_dup 4)\n-\t\t (match_dup 5)] UNSPEC_VSETVL))]\n+\t\t (match_dup 5)\n+\t\t (match_dup 6)] UNSPEC_VSETVL))]\n \"TARGET_VECTOR\"\n- \"vset%i1vli\\t%0,%1,e%2,%m3,t%p4,m%p5\"\n+ \"* return INTVAL (operands[4]) ? \\\"vset%i1vli\\\\t%0,%1,e%2alt,%m3,t%p5,m%p6\\\" : \\\"vset%i1vli\\\\t%0,%1,e%2,%m3,t%p5,m%p6\\\";\"\n [(set_attr \"type\" \"vsetvl\")\n (set_attr \"mode\" \"<MODE>\")\n (set (attr \"sew\") (symbol_ref \"INTVAL (operands[2])\"))\n (set (attr \"vlmul\") (symbol_ref \"INTVAL (operands[3])\"))\n- (set (attr \"ta\") (symbol_ref \"INTVAL (operands[4])\"))\n- (set (attr \"ma\") (symbol_ref \"INTVAL (operands[5])\"))])\n+ (set (attr \"altfmt\")\n+\t(symbol_ref \"((enum attr_altfmt) INTVAL (operands[4]))\"))\n+ (set (attr \"ta\") (symbol_ref \"INTVAL (operands[5])\"))\n+ (set (attr \"ma\") (symbol_ref \"INTVAL (operands[6])\"))])\n \n ;; vsetvl zero,zero,vtype instruction.\n ;; This pattern has no side effects and does not set X0 register.\n@@ -1787,15 +1796,18 @@\n \t [(match_operand 0 \"const_int_operand\" \"i\")\n \t (match_operand 1 \"const_int_operand\" \"i\")\n \t (match_operand 2 \"const_int_operand\" \"i\")\n-\t (match_operand 3 \"const_int_operand\" \"i\")] UNSPEC_VSETVL))]\n+\t (match_operand 3 \"const_int_operand\" \"i\")\n+\t (match_operand 4 \"const_int_operand\" \"i\")] UNSPEC_VSETVL))]\n \"TARGET_VECTOR\"\n- \"vsetvli\\tzero,zero,e%0,%m1,t%p2,m%p3\"\n+ \"* return INTVAL (operands[2]) ? \\\"vsetvli\\\\tzero,zero,e%0alt,%m1,t%p3,m%p4\\\" : \\\"vsetvli\\\\tzero,zero,e%0,%m1,t%p3,m%p4\\\";\"\n [(set_attr \"type\" \"vsetvl\")\n (set_attr \"mode\" \"SI\")\n (set (attr \"sew\") (symbol_ref \"INTVAL (operands[0])\"))\n (set (attr \"vlmul\") (symbol_ref \"INTVAL (operands[1])\"))\n- (set (attr \"ta\") (symbol_ref \"INTVAL (operands[2])\"))\n- (set (attr \"ma\") (symbol_ref \"INTVAL (operands[3])\"))])\n+ (set (attr \"altfmt\")\n+\t(symbol_ref \"((enum attr_altfmt) INTVAL (operands[2]))\"))\n+ (set (attr \"ta\") (symbol_ref \"INTVAL (operands[3])\"))\n+ (set (attr \"ma\") (symbol_ref \"INTVAL (operands[4])\"))])\n \n ;; vsetvl zero,rs1,vtype instruction.\n ;; The reason we need this pattern since we should avoid setting X0 register\n@@ -1809,15 +1821,18 @@\n \t(unspec:SI [(match_dup 1)\n \t\t (match_dup 2)\n \t\t (match_operand 3 \"const_int_operand\" \"i\")\n-\t\t (match_operand 4 \"const_int_operand\" \"i\")] UNSPEC_VSETVL))]\n+\t\t (match_operand 4 \"const_int_operand\" \"i\")\n+\t\t (match_operand 5 \"const_int_operand\" \"i\")] UNSPEC_VSETVL))]\n \"TARGET_VECTOR\"\n- \"vset%i0vli\\tzero,%0,e%1,%m2,t%p3,m%p4\"\n+ \"* return INTVAL (operands[3]) ? \\\"vset%i0vli\\\\tzero,%0,e%1alt,%m2,t%p4,m%p5\\\" : \\\"vset%i0vli\\\\tzero,%0,e%1,%m2,t%p4,m%p5\\\";\"\n [(set_attr \"type\" \"vsetvl\")\n (set_attr \"mode\" \"<MODE>\")\n (set (attr \"sew\") (symbol_ref \"INTVAL (operands[1])\"))\n (set (attr \"vlmul\") (symbol_ref \"INTVAL (operands[2])\"))\n- (set (attr \"ta\") (symbol_ref \"INTVAL (operands[3])\"))\n- (set (attr \"ma\") (symbol_ref \"INTVAL (operands[4])\"))])\n+ (set (attr \"altfmt\")\n+\t(symbol_ref \"((enum attr_altfmt) INTVAL (operands[3]))\"))\n+ (set (attr \"ta\") (symbol_ref \"INTVAL (operands[4])\"))\n+ (set (attr \"ma\") (symbol_ref \"INTVAL (operands[5])\"))])\n \n ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.\n ;; Since we have many optimization passes from \"expand\" to \"reload_completed\",\n@@ -1828,22 +1843,29 @@\n \t\t (match_operand 2 \"const_int_operand\" \"i\")\n \t\t (match_operand 3 \"const_int_operand\" \"i\")\n \t\t (match_operand 4 \"const_int_operand\" \"i\")\n-\t\t (match_operand 5 \"const_int_operand\" \"i\")] UNSPEC_VSETVL))]\n+\t\t (match_operand 5 \"const_int_operand\" \"i\")\n+\t\t (match_operand 6 \"const_int_operand\" \"i\")] UNSPEC_VSETVL))]\n \"TARGET_VECTOR\"\n \"#\"\n \"&& epilogue_completed\"\n [(parallel\n [(set (match_dup 0)\n \t (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)\n-\t\t (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))\n+\t\t (match_dup 4) (match_dup 5) (match_dup 6)] UNSPEC_VSETVL))\n (set (reg:SI VL_REGNUM)\n \t (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))\n (set (reg:SI VTYPE_REGNUM)\n \t (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)\n-\t\t (match_dup 5)] UNSPEC_VSETVL))])]\n+\t\t (match_dup 5) (match_dup 6)] UNSPEC_VSETVL))])]\n \"\"\n [(set_attr \"type\" \"vsetvl\")\n- (set_attr \"mode\" \"SI\")])\n+ (set_attr \"mode\" \"SI\")\n+ (set (attr \"sew\") (symbol_ref \"INTVAL (operands[2])\"))\n+ (set (attr \"vlmul\") (symbol_ref \"INTVAL (operands[3])\"))\n+ (set (attr \"altfmt\")\n+\t(symbol_ref \"((enum attr_altfmt) INTVAL (operands[4]))\"))\n+ (set (attr \"ta\") (symbol_ref \"INTVAL (operands[5])\"))\n+ (set (attr \"ma\") (symbol_ref \"INTVAL (operands[6])\"))])\n \n ;; This pattern use to combine below two insns and then further remove\n ;; unnecessary sign_extend operations:\n@@ -1872,7 +1894,8 @@\n \t\t (match_operand 2 \"const_int_operand\")\n \t\t (match_operand 3 \"const_int_operand\")\n \t\t (match_operand 4 \"const_int_operand\")\n-\t\t (match_operand 5 \"const_int_operand\")] UNSPEC_VSETVL) 0)))]\n+\t\t (match_operand 5 \"const_int_operand\")\n+\t\t (match_operand 6 \"const_int_operand\")] UNSPEC_VSETVL) 0)))]\n \"TARGET_VECTOR && TARGET_64BIT\"\n \"#\"\n \"&& 1\"\n@@ -1881,10 +1904,17 @@\n (match_dup 2)\n (match_dup 3)\n (match_dup 4)\n- (match_dup 5)] UNSPEC_VSETVL))]\n+ (match_dup 5)\n+ (match_dup 6)] UNSPEC_VSETVL))]\n \"\"\n [(set_attr \"type\" \"vsetvl\")\n- (set_attr \"mode\" \"SI\")])\n+ (set_attr \"mode\" \"SI\")\n+ (set (attr \"sew\") (symbol_ref \"INTVAL (operands[2])\"))\n+ (set (attr \"vlmul\") (symbol_ref \"INTVAL (operands[3])\"))\n+ (set (attr \"altfmt\")\n+\t(symbol_ref \"((enum attr_altfmt) INTVAL (operands[4]))\"))\n+ (set (attr \"ta\") (symbol_ref \"INTVAL (operands[5])\"))\n+ (set (attr \"ma\") (symbol_ref \"INTVAL (operands[6])\"))])\n \n ;; RVV machine description matching format\n ;; (define_insn \"\"\n", "prefixes": [ "5/8" ] }