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GET /api/patches/2195896/?format=api
{ "id": 2195896, "url": "http://patchwork.ozlabs.org/api/patches/2195896/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-3-linopeng@andestech.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212091326.2240990-3-linopeng@andestech.com>", "list_archive_url": null, "date": "2026-02-12T09:13:20", "name": "[2/8] RISC-V: Add zvfofp8min FP8 to BF16 vector conversions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "19df9109eaaf959783988fc65db5bcdac3716c65", "submitter": { "id": 92634, "url": "http://patchwork.ozlabs.org/api/people/92634/?format=api", "name": "Lino Hsing-Yu Peng", "email": "linopeng@andestech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-3-linopeng@andestech.com/mbox/", "series": [ { "id": 491947, "url": "http://patchwork.ozlabs.org/api/series/491947/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491947", "date": "2026-02-12T09:13:18", "name": "*** Add RISC-V zvfofp8min intrinsic ***", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491947/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195896/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195896/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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Thu, 12 Feb 2026 09:23:21 +0000 (GMT)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 61C9NHSj011528;\n Thu, 12 Feb 2026 17:23:17 +0800 (+08)\n (envelope-from linopeng@andestech.com)", "from atccpl01.andestech.com (10.0.15.149) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Feb\n 2026 17:23:17 +0800" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 1410C4BA23FF", "OpenDKIM Filter v2.11.0 sourceware.org 2B5304B9DB4B" ], "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 2B5304B9DB4B", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1770888202; cv=none;\n b=mK27Nh8IS+7x+6R4U//+O8A4xMPAX/kktqcEHQbgZ0SDiKzp8Rl2850N4cdpVf0peWH5rgh61oV8CNv7od3VlQUqgusYsrX7vUo47aXwjc35u6eXRlsjkcbN1ZrHuzs0ZknxVMV+WReeplAArrZEv/s4JwItz7Epfg+ZFLQ/O6Q=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1770888202; c=relaxed/simple;\n bh=8HwjgkaX8SxF1giCzsS/5NCTQ1Kapzz8vTqQOwHet/k=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=Qd98tUthAC3TRMgOqiBFFXi4mH38o5huAwwE3/jXwJziPliOITyiqR5NSd1H2mFBuHgsiiFM4a3CIjswj+Bp2Hv1M7ti+IcV/OVHGxcC3hp884/1KapYp/kVEUxdK/rVlSdygTmWICv/ArfBsLOsc19/GdKtzTqiBqacCXMTLik=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Lino Hsing-Yu Peng <linopeng@andestech.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "Lino Hsing-Yu Peng <linopeng1019@gmail.com>", "Subject": "[PATCH 2/8] RISC-V: Add zvfofp8min FP8 to BF16 vector conversions", "Date": "Thu, 12 Feb 2026 17:13:20 +0800", "Message-ID": "<20260212091326.2240990-3-linopeng@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260212091326.2240990-2-linopeng@andestech.com>", "References": "<20260212091326.2240990-1-linopeng@andestech.com>\n <20260212091326.2240990-2-linopeng@andestech.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.149]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 61C9NHSj011528", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Lino Hsing-Yu Peng <linopeng1019@gmail.com>\n\nImplement Zvfofp8min widening conversions from FP8 to BF16 across the RVV\nbuiltin framework and machine descriptions. This adds the float8 pattern\ndefinitions and wires new shapes, types, and unspecs for these operations.\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-vector-builtins-bases.cc: Add f8 widening conversions.\n\t* config/riscv/riscv-vector-builtins-functions.def: Add zvfofp8min builtins.\n\t* config/riscv/riscv-vector-builtins-shapes.cc: Add f8 shapes and naming.\n\t* config/riscv/riscv-vector-builtins-shapes.h: Declare f8 shapes.\n\t* config/riscv/riscv-vector-builtins.cc: Add f8_to_bf16 operand info.\n\t* config/riscv/riscv-vector-builtins-types.def: Add bf16 ops list.\n\t* config/riscv/riscv.md: Add zvfofp8min unspecs and include vector-float8.md.\n\t* config/riscv/vector-float8.md: New file.\n---\n .../riscv/riscv-vector-builtins-bases.cc | 30 ++++++-\n .../riscv/riscv-vector-builtins-functions.def | 6 ++\n .../riscv/riscv-vector-builtins-shapes.cc | 88 +++++++++++++++++--\n .../riscv/riscv-vector-builtins-shapes.h | 3 +\n .../riscv/riscv-vector-builtins-types.def | 14 +++\n gcc/config/riscv/riscv-vector-builtins.cc | 14 +++\n gcc/config/riscv/riscv.md | 6 ++\n gcc/config/riscv/vector-float8.md | 63 +++++++++++++\n 8 files changed, 216 insertions(+), 8 deletions(-)\n create mode 100644 gcc/config/riscv/vector-float8.md", "diff": "diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc\nindex 525a622882a..58ab57db5d4 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc\n@@ -1516,13 +1516,41 @@ public:\n }\n };\n \n+enum altfmt\n+{\n+ F8NONE,\n+ F8E4M3,\n+ F8E5M2\n+};\n+\n+static altfmt\n+get_altfmt (const function_expander &e)\n+{\n+ if (e.shape == shapes::alu_f8e4m3)\n+ return F8E4M3;\n+ if (e.shape == shapes::alu_f8e5m2)\n+ return F8E5M2;\n+ return F8NONE;\n+}\n class vfwcvt_f : public function_base\n {\n public:\n rtx expand (function_expander &e) const override\n {\n if (e.op_info->op == OP_TYPE_f_v)\n- return e.use_exact_insn (code_for_pred_extend (e.vector_mode ()));\n+ {\n+\tswitch (get_altfmt (e))\n+\t {\n+\t case F8E4M3:\n+\t return e.use_exact_insn (\n+\t code_for_pred_extend_to (UNSPEC_F8E4M3, e.vector_mode ()));\n+\t case F8E5M2:\n+\t return e.use_exact_insn (\n+\t code_for_pred_extend_to (UNSPEC_F8E5M2, e.vector_mode ()));\n+\t default:\n+\t return e.use_exact_insn (code_for_pred_extend (e.vector_mode ()));\n+\t }\n+ }\n if (e.op_info->op == OP_TYPE_x_v)\n return e.use_exact_insn (code_for_pred_widen (FLOAT, e.vector_mode ()));\n if (e.op_info->op == OP_TYPE_xu_v)\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def\nindex 3ae3de80897..185d811e2b7 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-functions.def\n+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def\n@@ -769,6 +769,12 @@ DEF_RVV_FUNCTION (vfncvtbf16_f_frm, narrow_alu_frm, full_preds, f32_to_bf16_f_w_\n DEF_RVV_FUNCTION (vfwcvtbf16_f, alu, full_preds, bf16_to_f32_f_v_ops)\n #undef REQUIRED_EXTENSIONS\n \n+/* Zvfofp8min */\n+#define REQUIRED_EXTENSIONS ZVFOFP8MIN_EXT\n+DEF_RVV_FUNCTION (vfwcvt_f, alu_f8e4m3, full_preds, f8_to_bf16_f_v_ops)\n+DEF_RVV_FUNCTION (vfwcvt_f, alu_f8e5m2, full_preds, f8_to_bf16_f_v_ops)\n+#undef REQUIRED_EXTENSIONS\n+\n /* Zvfbfwma */\n #define REQUIRED_EXTENSIONS ZVFBFWMA_EXT\n DEF_RVV_FUNCTION (vfwmaccbf16, alu, full_preds, f32_wwvv_ops)\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc\nindex 3bf40c432c2..3533ef01714 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc\n@@ -89,15 +89,14 @@ supports_vectype_p (const function_group_info &group, unsigned int vec_type_idx)\n /* Only judge for bf16 vector type */\n if (*group.shape == shapes::loadstore\n || *group.shape == shapes::indexed_loadstore\n- || *group.shape == shapes::vundefined\n- || *group.shape == shapes::misc\n- || *group.shape == shapes::vset\n- || *group.shape == shapes::vget\n- || *group.shape == shapes::vcreate\n- || *group.shape == shapes::fault_load\n+ || *group.shape == shapes::vundefined || *group.shape == shapes::misc\n+ || *group.shape == shapes::vset || *group.shape == shapes::vget\n+ || *group.shape == shapes::vcreate || *group.shape == shapes::fault_load\n || *group.shape == shapes::seg_loadstore\n || *group.shape == shapes::seg_indexed_loadstore\n- || *group.shape == shapes::seg_fault_load)\n+ || *group.shape == shapes::seg_fault_load\n+ || *group.shape == shapes::alu_f8e4m3\n+ || *group.shape == shapes::alu_f8e5m2)\n return true;\n return false;\n }\n@@ -424,6 +423,78 @@ struct alu_def : public build_base\n }\n };\n \n+static void\n+append_f8_suffix (function_builder &b, vector_type_index vti,\n+\t\t const char *altfmt)\n+{\n+ if (vti == VECTOR_TYPE_INVALID)\n+ return;\n+\n+ const char *suffix = type_suffixes[vti].vector;\n+ if (!suffix)\n+ return;\n+\n+ if (strncmp (suffix, \"_u8\", 3) == 0)\n+ {\n+ b.append_name (\"_\");\n+ b.append_name (altfmt);\n+ b.append_name (suffix + 3);\n+ }\n+ else\n+ b.append_name (suffix);\n+}\n+\n+static char *\n+build_f8_name (function_builder &b, const function_instance &instance,\n+\t bool overloaded_p, const char *altfmt)\n+{\n+ if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))\n+ return nullptr;\n+\n+ b.append_base_name (instance.base_name);\n+\n+ if (overloaded_p)\n+ {\n+ b.append_name (\"_\");\n+ b.append_name (altfmt);\n+ b.append_name (\"_bf16\");\n+ }\n+ else\n+ {\n+ b.append_name (operand_suffixes[instance.op_info->op]);\n+ append_f8_suffix (b,\n+\t\t\tinstance.op_info->args[0].get_function_type_index (\n+\t\t\t instance.type.index),\n+\t\t\taltfmt);\n+ b.append_name (type_suffixes[instance.type.index].vector);\n+ }\n+\n+ if (overloaded_p && instance.pred == PRED_TYPE_m)\n+ return b.finish_name ();\n+ b.append_name (predication_suffixes[instance.pred]);\n+ return b.finish_name ();\n+}\n+\n+/* alu_f8e4m3_def class. */\n+struct alu_f8e4m3_def : public alu_def\n+{\n+ char *get_name (function_builder &b, const function_instance &instance,\n+\t\t bool overloaded_p) const override\n+ {\n+ return build_f8_name (b, instance, overloaded_p, \"f8e4m3\");\n+ }\n+};\n+\n+/* alu_f8e5m2_def class. */\n+struct alu_f8e5m2_def : public alu_def\n+{\n+ char *get_name (function_builder &b, const function_instance &instance,\n+\t\t bool overloaded_p) const override\n+ {\n+ return build_f8_name (b, instance, overloaded_p, \"f8e5m2\");\n+ }\n+};\n+\n /* The base class for frm build. */\n struct build_frm_base : public build_base\n {\n@@ -1431,4 +1502,7 @@ SHAPE (sf_vqmacc, sf_vqmacc)\n SHAPE (sf_vfnrclip, sf_vfnrclip)\n SHAPE(sf_vcix_se, sf_vcix_se)\n SHAPE(sf_vcix, sf_vcix)\n+/* Zvfofp8min */\n+SHAPE (alu_f8e4m3, alu_f8e4m3)\n+SHAPE (alu_f8e5m2, alu_f8e5m2)\n } // end namespace riscv_vector\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h\nindex d9502d4c5b4..d700d76da30 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-shapes.h\n+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h\n@@ -64,6 +64,9 @@ extern const function_shape *const sf_vqmacc;\n extern const function_shape *const sf_vfnrclip;\n extern const function_shape *const sf_vcix_se;\n extern const function_shape *const sf_vcix;\n+/* Zvfofp8min extension. */\n+extern const function_shape *const alu_f8e4m3;\n+extern const function_shape *const alu_f8e5m2;\n }\n \n } // end namespace riscv_vector\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def\nindex 56f55109188..b4c1b693910 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-types.def\n+++ b/gcc/config/riscv/riscv-vector-builtins-types.def\n@@ -42,6 +42,12 @@ along with GCC; see the file COPYING3. If not see\n #define DEF_RVV_B_OPS(TYPE, REQUIRE)\n #endif\n \n+/* Use \"DEF_RVV_BF_OPS\" macro include bfloat16 floating-point which will be\n+ iterated and registered as intrinsic functions. */\n+#ifndef DEF_RVV_BF_OPS\n+#define DEF_RVV_BF_OPS(TYPE, REQUIRE)\n+#endif\n+\n /* Use \"DEF_RVV_WEXTI_OPS\" macro include Double-Widening signed integer which\n will be iterated and registered as intrinsic functions. */\n #ifndef DEF_RVV_WEXTI_OPS\n@@ -477,6 +483,13 @@ DEF_RVV_B_OPS (vbool4_t, 0)\n DEF_RVV_B_OPS (vbool2_t, 0)\n DEF_RVV_B_OPS (vbool1_t, 0)\n \n+DEF_RVV_BF_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_ELEN_64)\n+DEF_RVV_BF_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16)\n+DEF_RVV_BF_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16)\n+DEF_RVV_BF_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16)\n+DEF_RVV_BF_OPS (vbfloat16m4_t, RVV_REQUIRE_ELEN_BF_16)\n+DEF_RVV_BF_OPS (vbfloat16m8_t, RVV_REQUIRE_ELEN_BF_16)\n+\n DEF_RVV_WEXTI_OPS (vint16mf4_t, RVV_REQUIRE_ELEN_64)\n DEF_RVV_WEXTI_OPS (vint16mf2_t, 0)\n DEF_RVV_WEXTI_OPS (vint16m1_t, 0)\n@@ -1546,6 +1559,7 @@ DEF_RVV_F16_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)\n #undef DEF_RVV_U_OPS\n #undef DEF_RVV_F_OPS\n #undef DEF_RVV_B_OPS\n+#undef DEF_RVV_BF_OPS\n #undef DEF_RVV_WEXTI_OPS\n #undef DEF_RVV_QEXTI_OPS\n #undef DEF_RVV_OEXTI_OPS\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc\nindex 5892ae5e466..a7ad068b00a 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins.cc\n@@ -277,6 +277,12 @@ static const rvv_type_info b_ops[] = {\n #include \"riscv-vector-builtins-types.def\"\n {NUM_VECTOR_TYPES, 0}};\n \n+/* A list of all bfloat will be registered for intrinsic functions. */\n+static const rvv_type_info bf_ops[] = {\n+#define DEF_RVV_BF_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},\n+#include \"riscv-vector-builtins-types.def\"\n+ {NUM_VECTOR_TYPES, 0}};\n+\n /* A list of all float will be registered for intrinsic functions. */\n static const rvv_type_info f_ops[] = {\n #define DEF_RVV_F_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},\n@@ -2052,6 +2058,14 @@ static CONSTEXPR const rvv_op_info f_to_nf_f_w_ops\n rvv_arg_type_info (RVV_BASE_double_trunc_float_vector), /* Return type */\n v_args /* Args */};\n \n+/* A static operand information for vector_type func (vector_type)\n+ * function registration. */\n+static CONSTEXPR const rvv_op_info f8_to_bf16_f_v_ops\n+ = {bf_ops,\t\t\t\t /* Types */\n+ OP_TYPE_f_v,\t\t\t /* Suffix */\n+ rvv_arg_type_info (RVV_BASE_vector), /* Return type */\n+ w_xu_v_args /* Args */};\n+\n /* A static operand information for vector_type func (vector_type)\n * function registration. */\n static CONSTEXPR const rvv_op_info f32_to_bf16_f_w_ops\ndiff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 3fe0ad0ccdf..a5e5ecae3e7 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -103,6 +103,11 @@\n ;; Stack Smash Protector\n UNSPEC_SSP_SET\n UNSPEC_SSP_TEST\n+ ;; Zvfofp8min\n+ UNSPEC_F8E4M3\n+ UNSPEC_F8E5M2\n+ UNSPEC_F8E4M3_SAT\n+ UNSPEC_F8E5M2_SAT\n ])\n \n (define_c_enum \"unspecv\" [\n@@ -4971,6 +4976,7 @@\n (include \"vector.md\")\n (include \"vector-crypto.md\")\n (include \"vector-bfloat16.md\")\n+(include \"vector-float8.md\")\n (include \"zicond.md\")\n (include \"mips-insn.md\")\n (include \"sfb.md\")\ndiff --git a/gcc/config/riscv/vector-float8.md b/gcc/config/riscv/vector-float8.md\nnew file mode 100644\nindex 00000000000..2a3eeeaa1db\n--- /dev/null\n+++ b/gcc/config/riscv/vector-float8.md\n@@ -0,0 +1,63 @@\n+;; Machine description for RISC-V Zvfofp8 extension conversions.\n+;; Copyright (C) 2026 Free Software Foundation, Inc.\n+\n+;; This file is part of GCC.\n+\n+;; GCC is free software; you can redistribute it and/or modify\n+;; it under the terms of the GNU General Public License as published by\n+;; the Free Software Foundation; either version 3, or (at your option)\n+;; any later version.\n+\n+;; GCC is distributed in the hope that it will be useful,\n+;; but WITHOUT ANY WARRANTY; without even the implied warranty of\n+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+;; General Public License for more details.\n+\n+;; You should have received a copy of the GNU General Public License\n+;; along with GCC; see the file COPYING3. If not see\n+;; <http://www.gnu.org/licenses/>.\n+\n+(define_mode_iterator VWEXTF_ZVFOFP8MIN [\n+ (RVVM8BF \"TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\")\n+ (RVVM4BF \"TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\")\n+ (RVVM2BF \"TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\")\n+ (RVVM1BF \"TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\")\n+ (RVVMF2BF \"TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\")\n+ (RVVMF4BF \"TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN && TARGET_MIN_VLEN > 32\")\n+])\n+\n+(define_mode_attr VBF_DOUBLE_TRUNC [\n+ (RVVM8BF \"RVVM4QI\")\n+ (RVVM4BF \"RVVM2QI\")\n+ (RVVM2BF \"RVVM1QI\")\n+ (RVVM1BF \"RVVMF2QI\")\n+ (RVVMF2BF \"RVVMF4QI\")\n+ (RVVMF4BF \"RVVMF8QI\")\n+])\n+\n+(define_int_iterator ALTFMT [UNSPEC_F8E4M3 UNSPEC_F8E5M2])\n+(define_int_attr altfmt\n+ [(UNSPEC_F8E4M3 \"f8e4m3\")\n+ (UNSPEC_F8E5M2 \"f8e5m2\")])\n+\n+;; Zvfofp8min extension: FP8 to BF16 widening conversions.\n+\n+(define_insn \"@pred_extend_<altfmt>_to_<mode>\"\n+ [(set (match_operand:VWEXTF_ZVFOFP8MIN 0 \"register_operand\" \"=&vr, &vr\")\n+ (if_then_else:VWEXTF_ZVFOFP8MIN\n+ (unspec:<VM>\n+ [(match_operand:<VM> 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n+ (match_operand 4 \"vector_length_operand\" \" rK, rK\")\n+ (match_operand 5 \"const_int_operand\" \" i, i\")\n+ (match_operand 6 \"const_int_operand\" \" i, i\")\n+ (match_operand 7 \"const_int_operand\" \" i, i\")\n+ (reg:SI VL_REGNUM)\n+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n+ (unspec:VWEXTF_ZVFOFP8MIN\n+ [(float_extend:VWEXTF_ZVFOFP8MIN\n+ (match_operand:<VBF_DOUBLE_TRUNC> 3 \"register_operand\" \" vr, vr\"))] ALTFMT)\n+ (match_operand:VWEXTF_ZVFOFP8MIN 2 \"vector_merge_operand\" \" vu, 0\")))]\n+ \"TARGET_VECTOR && TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\"\n+ \"vfwcvtbf16.f.f.v\\t%0,%3%p1\"\n+ [(set_attr \"type\" \"vfwcvtbf16\")\n+ (set_attr \"mode\" \"<VBF_DOUBLE_TRUNC>\")])\n", "prefixes": [ "2/8" ] }