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GET /api/patches/2195894/?format=api
{ "id": 2195894, "url": "http://patchwork.ozlabs.org/api/patches/2195894/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-5-linopeng@andestech.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212091326.2240990-5-linopeng@andestech.com>", "list_archive_url": null, "date": "2026-02-12T09:13:22", "name": "[4/8] RISC-V: Add zvfofp8min FP32 to FP8 narrowing conversions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d9822e279900cec3be8e31b72685da23646d3085", "submitter": { "id": 92634, "url": "http://patchwork.ozlabs.org/api/people/92634/?format=api", "name": "Lino Hsing-Yu Peng", "email": "linopeng@andestech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-5-linopeng@andestech.com/mbox/", "series": [ { "id": 491947, "url": "http://patchwork.ozlabs.org/api/series/491947/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491947", "date": "2026-02-12T09:13:18", "name": "*** Add RISC-V zvfofp8min intrinsic ***", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491947/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195894/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195894/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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Thu, 12 Feb 2026 09:23:51 +0000 (GMT)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 61C9NjUK011634;\n Thu, 12 Feb 2026 17:23:45 +0800 (+08)\n (envelope-from linopeng@andestech.com)", "from atccpl01.andestech.com (10.0.15.149) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Feb\n 2026 17:23:45 +0800" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 468444B9DB61", "OpenDKIM Filter v2.11.0 sourceware.org 8AF534B9DB5E" ], "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 8AF534B9DB5E", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1770888232; cv=none;\n b=O+bcwl1Wn31cEd4WZ+pmn0+MHUIMfDwCgI5NrE52KydKpGE6zdaH6dmYRRO63oo2EFnYBsCzpdpGB/E0ULdWdzbvizJaxZ3Nt6+F0KX683hcOMBdmJImOFQ1d85yjyH/v9kgc8CE7xehmnw1mkQMmv1dygvlLF9BExTPb0Lw0Fs=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1770888232; c=relaxed/simple;\n bh=igsiR6RJXKlEw/TwYPBf2rk5ypldzhwg2KYLpITpZQQ=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=jE6oNDWW98rxqKUkrAvNx7mjsGUAlcXqd8eqGcYYw4zKT4g7+kbcFAqh4ajpVSgs+zIojHh5nzYEjoURrMjwgxpRwTK2oJrO+7MYJ+wq3HDBLgUY8wt4q7mJrCvhdzUUGF27prqByRO+LSSQcpHqA2WUn0JV5/m+CWqpd38lr+I=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Lino Hsing-Yu Peng <linopeng@andestech.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "Lino Hsing-Yu Peng <linopeng1019@gmail.com>", "Subject": "[PATCH 4/8] RISC-V: Add zvfofp8min FP32 to FP8 narrowing conversions", "Date": "Thu, 12 Feb 2026 17:13:22 +0800", "Message-ID": "<20260212091326.2240990-5-linopeng@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260212091326.2240990-4-linopeng@andestech.com>", "References": "<20260212091326.2240990-1-linopeng@andestech.com>\n <20260212091326.2240990-2-linopeng@andestech.com>\n <20260212091326.2240990-3-linopeng@andestech.com>\n <20260212091326.2240990-4-linopeng@andestech.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.149]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 61C9NjUK011634", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Lino Hsing-Yu Peng <linopeng1019@gmail.com>\n\nAdd Zvfofp8min narrowing support from FP32 to FP8 by extending builtin\noperation typing and generated indices for quad-trunc forms. Hook the new\noperations into the RVV builtins and float8 machine description patterns.\n\ngcc/ChangeLog:\n\n\t* config/riscv/genrvv-type-indexer.cc: Add QUAD_TRUNC_UNSIGNED entries.\n\t* config/riscv/riscv-vector-builtins-bases.cc: Add f32 to f8 quad-trunc handling.\n\t* config/riscv/riscv-vector-builtins-functions.def: Add f32 to f8 builtins.\n\t* config/riscv/riscv-vector-builtins-shapes.cc: Adjust f8 narrow naming for f_q.\n\t* config/riscv/riscv-vector-builtins.cc: Add f32_to_f8 operand info.\n\t* config/riscv/riscv-vector-builtins.def: Add f_q op type.\n\t* config/riscv/vector-float8.md: Add f32 to f8 narrowing patterns.\n---\n gcc/config/riscv/genrvv-type-indexer.cc | 10 +++\n .../riscv/riscv-vector-builtins-bases.cc | 30 +++++++++\n .../riscv/riscv-vector-builtins-functions.def | 8 +++\n .../riscv/riscv-vector-builtins-shapes.cc | 12 ++--\n gcc/config/riscv/riscv-vector-builtins.cc | 38 +++++++-----\n gcc/config/riscv/riscv-vector-builtins.def | 8 ++-\n gcc/config/riscv/vector-float8.md | 62 ++++++++++++++++---\n 7 files changed, 140 insertions(+), 28 deletions(-)", "diff": "diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc\nindex 040a5aee9ac..533e39ebe58 100644\n--- a/gcc/config/riscv/genrvv-type-indexer.cc\n+++ b/gcc/config/riscv/genrvv-type-indexer.cc\n@@ -274,6 +274,7 @@ main (int argc, const char **argv)\n fprintf (fp, \" /*SHIFT*/ INVALID,\\n\");\n fprintf (fp, \" /*DOUBLE_TRUNC*/ INVALID,\\n\");\n fprintf (fp, \" /*QUAD_TRUNC*/ INVALID,\\n\");\n+ fprintf (fp, \" /*QUAD_TRUNC_UNSIGNED*/ INVALID,\\n\");\n fprintf (fp, \" /*QUAD_EMUL*/ INVALID,\\n\");\n fprintf (fp, \" /*QUAD_EMUL_SIGNED*/ INVALID,\\n\");\n fprintf (fp, \" /*QUAD_EMUL_UNSIGNED*/ INVALID,\\n\");\n@@ -357,6 +358,9 @@ main (int argc, const char **argv)\n \t\t same_ratio_eew_type (sew, lmul_log2, sew / 4, unsigned_p,\n \t\t\t\t\t false)\n \t\t .c_str ());\n+\t fprintf (fp, \" /*QUAD_TRUNC_UNSIGNED*/ %s,\\n\",\n+\t\t same_ratio_eew_type (sew, lmul_log2, sew / 4, true, false)\n+\t\t .c_str ());\n \t fprintf (fp, \" /*QUAD_EMUL*/ %s,\\n\",\n \t\t inttype (8, lmul_log2 - 1, unsigned_p).c_str ());\n \t fprintf (fp, \" /*QUAD_EMUL_SIGNED*/ %s,\\n\",\n@@ -473,6 +477,9 @@ main (int argc, const char **argv)\n \tfprintf (fp, \" /*DOUBLE_TRUNC*/ %s,\\n\",\n \t\t same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ());\n \tfprintf (fp, \" /*QUAD_TRUNC*/ INVALID,\\n\");\n+\tfprintf (\n+\t fp, \" /*QUAD_TRUNC_UNSIGNED*/ %s,\\n\",\n+\t same_ratio_eew_type (16, lmul_log2, 16 / 4, true, false).c_str ());\n \tfprintf (fp, \" /*QUAD_EMUL*/ INVALID,\\n\");\n \tfprintf (fp, \" /*QUAD_EMUL_SIGNED*/ INVALID,\\n\");\n \tfprintf (fp, \" /*QUAD_EMUL_UNSIGNED*/ INVALID,\\n\");\n@@ -555,6 +562,9 @@ main (int argc, const char **argv)\n \t\t same_ratio_eew_type (sew, lmul_log2, sew / 2, false, true)\n \t\t .c_str ());\n \t fprintf (fp, \" /*QUAD_TRUNC*/ INVALID,\\n\");\n+\t fprintf (fp, \" /*QUAD_TRUNC_UNSIGNED*/ %s,\\n\",\n+\t\t same_ratio_eew_type (sew, lmul_log2, sew / 4, true, false)\n+\t\t .c_str ());\n \t fprintf (fp, \" /*QUAD_EMUL*/ INVALID,\\n\");\n \t fprintf (fp, \" /*QUAD_EMUL_SIGNED*/ INVALID,\\n\");\n \t fprintf (fp, \" /*QUAD_EMUL_UNSIGNED*/ INVALID,\\n\");\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc\nindex 3fa3ebb5d14..5c68f3a690c 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc\n@@ -1620,6 +1620,20 @@ public:\n \t return e.use_exact_insn (code_for_pred_trunc (e.vector_mode ()));\n \t }\n }\n+ if (e.op_info->op == OP_TYPE_f_q)\n+ {\n+\tswitch (get_altfmt (e))\n+\t {\n+\t case F8E4M3:\n+\t return e.use_exact_insn (\n+\t code_for_pred_quad_trunc_to (e.vector_mode (), UNSPEC_F8E4M3));\n+\t case F8E5M2:\n+\t return e.use_exact_insn (\n+\t code_for_pred_quad_trunc_to (e.vector_mode (), UNSPEC_F8E5M2));\n+\t default:\n+\t gcc_unreachable ();\n+\t }\n+ }\n if (e.op_info->op == OP_TYPE_x_w)\n return e.use_exact_insn (code_for_pred_narrow (FLOAT, e.arg_mode (0)));\n if (e.op_info->op == OP_TYPE_xu_w)\n@@ -1656,6 +1670,22 @@ public:\n \t break;\n \t }\n }\n+ if (e.op_info->op == OP_TYPE_f_q)\n+ {\n+\tswitch (get_altfmt (e))\n+\t {\n+\t case F8E4M3:\n+\t return e.use_exact_insn (\n+\t code_for_pred_quad_trunc_to (e.vector_mode (),\n+\t\t\t\t\t UNSPEC_F8E4M3_SAT));\n+\t case F8E5M2:\n+\t return e.use_exact_insn (\n+\t code_for_pred_quad_trunc_to (e.vector_mode (),\n+\t\t\t\t\t UNSPEC_F8E5M2_SAT));\n+\t default:\n+\t gcc_unreachable ();\n+\t }\n+ }\n gcc_unreachable ();\n }\n };\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def\nindex 49ad8585933..ed34dfa0dfe 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-functions.def\n+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def\n@@ -775,13 +775,21 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu_f8e4m3, full_preds, f8_to_bf16_f_v_ops)\n DEF_RVV_FUNCTION (vfwcvt_f, alu_f8e5m2, full_preds, f8_to_bf16_f_v_ops)\n DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e4m3, full_preds, bf16_to_f8_f_w_ops)\n DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e5m2, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e4m3, full_preds, f32_to_f8_f_q_ops)\n+DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e5m2, full_preds, f32_to_f8_f_q_ops)\n DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e4m3, full_preds, bf16_to_f8_f_w_ops)\n DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e5m2, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e4m3, full_preds, f32_to_f8_f_q_ops)\n+DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e5m2, full_preds, f32_to_f8_f_q_ops)\n \n DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e4m3, full_preds, bf16_to_f8_f_w_ops)\n DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e5m2, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e4m3, full_preds, f32_to_f8_f_q_ops)\n+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e5m2, full_preds, f32_to_f8_f_q_ops)\n DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e4m3, full_preds, bf16_to_f8_f_w_ops)\n DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e5m2, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e4m3, full_preds, f32_to_f8_f_q_ops)\n+DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e5m2, full_preds, f32_to_f8_f_q_ops)\n #undef REQUIRED_EXTENSIONS\n \n /* Zvfbfwma */\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc\nindex 8385a49f517..d593ff28ce0 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc\n@@ -824,9 +824,12 @@ build_f8_narrow_name (function_builder &b, const function_instance &instance,\n vector_type_index vti\n \t= instance.op_info->args[0].get_function_type_index (\n \t instance.type.index);\n- const char *src_scalar\n-\t= vti == VECTOR_TYPE_INVALID ? nullptr : type_suffixes[vti].scalar;\n- b.append_name (src_scalar ? src_scalar : \"_bf16\");\n+ if (instance.op_info->op == OP_TYPE_f_w)\n+\t{\n+\t const char *src_scalar\n+\t = vti == VECTOR_TYPE_INVALID ? nullptr : type_suffixes[vti].scalar;\n+\t b.append_name (src_scalar ? src_scalar : \"_bf16\");\n+\t}\n b.append_name (\"_\");\n b.append_name (altfmt);\n }\n@@ -836,7 +839,8 @@ build_f8_narrow_name (function_builder &b, const function_instance &instance,\n vector_type_index vti\n \t= instance.op_info->args[0].get_function_type_index (\n \t instance.type.index);\n- if (vti != VECTOR_TYPE_INVALID)\n+ /* Additional type suffix before output type suffix. */\n+ if (vti != VECTOR_TYPE_INVALID && instance.op_info->op != OP_TYPE_f_q)\n \tb.append_name (type_suffixes[vti].vector);\n append_f8_suffix (b,\n \t\t\tinstance.op_info->ret.get_function_type_index (\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc\nindex c671b133c85..ed5af47c3a2 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins.cc\n@@ -2067,6 +2067,14 @@ static CONSTEXPR const rvv_op_info bf16_to_f8_f_w_ops\n RVV_BASE_double_trunc_unsigned_vector), /* Return type */\n v_args /* Args */};\n \n+/* A static operand information for vector_type func (vector_type)\n+ * function registration. */\n+static CONSTEXPR const rvv_op_info f32_to_f8_f_q_ops\n+ = {f32_ops,\t\t\t\t\t\t /* Types */\n+ OP_TYPE_f_q,\t\t\t\t\t /* Suffix */\n+ rvv_arg_type_info (RVV_BASE_quad_trunc_unsigned_vector), /* Return type */\n+ v_args /* Args */};\n+\n /* A static operand information for vector_type func (vector_type)\n * function registration. */\n static CONSTEXPR const rvv_op_info f8_to_bf16_f_v_ops\n@@ -3468,20 +3476,21 @@ static CONSTEXPR const rvv_op_info sf_vc_v_fvw_ops\n static CONSTEXPR const function_type_info function_types[] = {\n #define DEF_RVV_TYPE_INDEX( \\\n VECTOR, MASK, SIGNED, UNSIGNED, SIGNED_EEW8_INDEX, EEW8_INDEX, EEW16_INDEX, \\\n- EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_EMUL, \\\n- QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED, \\\n- QUAD_FIX_UNSIGNED, OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, \\\n- DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR, \\\n- DOUBLE_TRUNC_BFLOAT_SCALAR, DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, \\\n- LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, XFQF, EEW8_INTERPRET, \\\n- EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET, \\\n- BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET, \\\n- BOOL32_INTERPRET, BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET, \\\n- SIGNED_EEW16_LMUL1_INTERPRET, SIGNED_EEW32_LMUL1_INTERPRET, \\\n- SIGNED_EEW64_LMUL1_INTERPRET, UNSIGNED_EEW8_LMUL1_INTERPRET, \\\n- UNSIGNED_EEW16_LMUL1_INTERPRET, UNSIGNED_EEW32_LMUL1_INTERPRET, \\\n- UNSIGNED_EEW64_LMUL1_INTERPRET, X2, X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT,\\\n- X16_VLMUL_EXT, X32_VLMUL_EXT, X64_VLMUL_EXT, TUPLE_SUBPART) \\\n+ EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, \\\n+ QUAD_TRUNC_UNSIGNED, QUAD_EMUL, QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, \\\n+ QUAD_FIX, QUAD_FIX_SIGNED, QUAD_FIX_UNSIGNED, OCT_TRUNC, \\\n+ DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED, \\\n+ DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_BFLOAT_SCALAR, \\\n+ DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, QLMUL1, \\\n+ QLMUL1_SIGNED, QLMUL1_UNSIGNED, XFQF, EEW8_INTERPRET, EEW16_INTERPRET, \\\n+ EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET, BOOL2_INTERPRET, \\\n+ BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET, BOOL32_INTERPRET, \\\n+ BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET, \\\n+ SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET, \\\n+ UNSIGNED_EEW8_LMUL1_INTERPRET, UNSIGNED_EEW16_LMUL1_INTERPRET, \\\n+ UNSIGNED_EEW32_LMUL1_INTERPRET, UNSIGNED_EEW64_LMUL1_INTERPRET, X2, \\\n+ X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT, \\\n+ X64_VLMUL_EXT, TUPLE_SUBPART) \\\n { \\\n VECTOR_TYPE_##VECTOR, \\\n VECTOR_TYPE_INVALID, \\\n@@ -3506,6 +3515,7 @@ static CONSTEXPR const function_type_info function_types[] = {\n VECTOR_TYPE_##SHIFT, \\\n VECTOR_TYPE_##DOUBLE_TRUNC, \\\n VECTOR_TYPE_##QUAD_TRUNC, \\\n+ VECTOR_TYPE_##QUAD_TRUNC_UNSIGNED, \\\n VECTOR_TYPE_##QUAD_EMUL, \\\n VECTOR_TYPE_##QUAD_EMUL_SIGNED, \\\n VECTOR_TYPE_##QUAD_EMUL_UNSIGNED, \\\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def\nindex 01e7409f5dc..eebc8d7c001 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.def\n+++ b/gcc/config/riscv/riscv-vector-builtins.def\n@@ -70,10 +70,10 @@ along with GCC; see the file COPYING3. If not see\n #ifndef DEF_RVV_TYPE_INDEX\n #define DEF_RVV_TYPE_INDEX( \\\n VECTOR, MASK, SIGNED, UNSIGNED, SIGNED_EEW8_INDEX, EEW8_INDEX, EEW16_INDEX, \\\n- EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_EMUL, \\\n- QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED, \\\n+ EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, QUAD_TRUNC_UNSIGNED, \\\n+ QUAD_EMUL, QUAD_EMUL_SIGNED, QUAD_EMUL_UNSIGNED, QUAD_FIX, QUAD_FIX_SIGNED, \\\n QUAD_FIX_UNSIGNED, OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, \\\n- DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR, \\\n+ DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR, \\\n DOUBLE_TRUNC_BFLOAT_SCALAR, DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, \\\n LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, XFQF, EEW8_INTERPRET, \\\n EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET, \\\n@@ -633,6 +633,7 @@ DEF_RVV_OP_TYPE (f)\n DEF_RVV_OP_TYPE (f_v)\n DEF_RVV_OP_TYPE (xu_v)\n DEF_RVV_OP_TYPE (f_w)\n+DEF_RVV_OP_TYPE (f_q)\n DEF_RVV_OP_TYPE (xu_w)\n DEF_RVV_OP_TYPE (s)\n DEF_RVV_OP_TYPE (4x8x4)\n@@ -708,6 +709,7 @@ DEF_RVV_BASE_TYPE (eew64_index, get_vector_type (type_idx))\n DEF_RVV_BASE_TYPE (shift_vector, get_vector_type (type_idx))\n DEF_RVV_BASE_TYPE (double_trunc_vector, get_vector_type (type_idx))\n DEF_RVV_BASE_TYPE (quad_trunc_vector, get_vector_type (type_idx))\n+DEF_RVV_BASE_TYPE (quad_trunc_unsigned_vector, get_vector_type (type_idx))\n DEF_RVV_BASE_TYPE (quad_emul_vector, get_vector_type (type_idx))\n DEF_RVV_BASE_TYPE (quad_emul_signed_vector, get_vector_type (type_idx))\n DEF_RVV_BASE_TYPE (quad_emul_unsigned_vector, get_vector_type (type_idx))\ndiff --git a/gcc/config/riscv/vector-float8.md b/gcc/config/riscv/vector-float8.md\nindex 423b490b811..20c656a948b 100644\n--- a/gcc/config/riscv/vector-float8.md\n+++ b/gcc/config/riscv/vector-float8.md\n@@ -26,6 +26,14 @@\n (RVVMF4BF \"TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN && TARGET_MIN_VLEN > 32\")\n ])\n \n+(define_mode_iterator VWEXT4_ZVFOFP8MIN [\n+ (RVVM8SF \"TARGET_ZVFOFP8MIN\")\n+ (RVVM4SF \"TARGET_ZVFOFP8MIN\")\n+ (RVVM2SF \"TARGET_ZVFOFP8MIN\")\n+ (RVVM1SF \"TARGET_ZVFOFP8MIN\")\n+ (RVVMF2SF \"TARGET_ZVFOFP8MIN\")\n+])\n+\n (define_mode_attr VBF_DOUBLE_TRUNC [\n (RVVM8BF \"RVVM4QI\")\n (RVVM4BF \"RVVM2QI\")\n@@ -35,8 +43,22 @@\n (RVVMF4BF \"RVVMF8QI\")\n ])\n \n-(define_int_iterator ALTFMT [UNSPEC_F8E4M3 UNSPEC_F8E5M2 UNSPEC_F8E4M3_SAT UNSPEC_F8E5M2_SAT])\n-(define_int_attr altfmt\n+(define_mode_attr VF_QUAD_TRUNC [\n+ (RVVM8SF \"RVVM2QI\")\n+ (RVVM4SF \"RVVM1QI\")\n+ (RVVM2SF \"RVVMF2QI\")\n+ (RVVM1SF \"RVVMF4QI\")\n+ (RVVMF2SF \"RVVMF8QI\")\n+])\n+\n+(define_int_iterator ALTFMT_BASE [UNSPEC_F8E4M3 UNSPEC_F8E5M2])\n+(define_int_iterator ALTFMT_SAT [UNSPEC_F8E4M3 UNSPEC_F8E5M2 UNSPEC_F8E4M3_SAT UNSPEC_F8E5M2_SAT])\n+\n+(define_int_attr altfmt_base\n+ [(UNSPEC_F8E4M3 \"f8e4m3\")\n+ (UNSPEC_F8E5M2 \"f8e5m2\")])\n+\n+(define_int_attr altfmt_sat\n [(UNSPEC_F8E4M3 \"f8e4m3\")\n (UNSPEC_F8E5M2 \"f8e5m2\")\n (UNSPEC_F8E4M3_SAT \"f8e4m3_sat\")\n@@ -50,7 +72,7 @@\n \n ;; Zvfofp8min extension: FP8 to BF16 widening conversions.\n \n-(define_insn \"@pred_extend_<altfmt>_to_<mode>\"\n+(define_insn \"@pred_extend_<altfmt_base>_to_<mode>\"\n [(set (match_operand:VWEXTF_ZVFOFP8MIN 0 \"register_operand\" \"=&vr, &vr\")\n (if_then_else:VWEXTF_ZVFOFP8MIN\n (unspec:<VM>\n@@ -63,8 +85,8 @@\n (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n (unspec:VWEXTF_ZVFOFP8MIN\n [(float_extend:VWEXTF_ZVFOFP8MIN\n- (match_operand:<VBF_DOUBLE_TRUNC> 3 \"register_operand\" \" vr, vr\"))] ALTFMT)\n- (match_operand:VWEXTF_ZVFOFP8MIN 2 \"vector_merge_operand\" \" vu, 0\")))]\n+ (match_operand:<VBF_DOUBLE_TRUNC> 3 \"register_operand\" \" vr, vr\"))] ALTFMT_BASE)\n+ (match_operand:VWEXTF_ZVFOFP8MIN 2 \"vector_merge_operand\" \" vu, 0\")))]\n \"TARGET_VECTOR && TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\"\n \"vfwcvtbf16.f.f.v\\t%0,%3%p1\"\n [(set_attr \"type\" \"vfwcvtbf16\")\n@@ -72,7 +94,7 @@\n \n ;; Zvfofp8min extension: BF16 to FP8 narrowing conversions.\n \n-(define_insn \"@pred_trunc_<mode>_to_<altfmt>\"\n+(define_insn \"@pred_trunc_<mode>_to_<altfmt_sat>\"\n [(set (match_operand:<VBF_DOUBLE_TRUNC> 0 \"register_operand\" \"=vd, vd, vr, vr, &vr, &vr\")\n (if_then_else:<VBF_DOUBLE_TRUNC>\n (unspec:<VM>\n@@ -87,7 +109,7 @@\n (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)\n \t (unspec:<VBF_DOUBLE_TRUNC>\n [(float_truncate:<VBF_DOUBLE_TRUNC>\n-\t (match_operand:VWEXTF_ZVFOFP8MIN 3 \"register_operand\" \" 0, 0, 0, 0, vr, vr\"))] ALTFMT)\n+\t (match_operand:VWEXTF_ZVFOFP8MIN 3 \"register_operand\" \" 0, 0, 0, 0, vr, vr\"))] ALTFMT_SAT)\n (match_operand:<VBF_DOUBLE_TRUNC> 2 \"vector_merge_operand\" \" vu, 0, vu, 0, vu, 0\")))]\n \"TARGET_VECTOR && TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\"\n \"vfncvtbf16<sat>.f.f.w\\t%0,%3%p1\"\n@@ -95,3 +117,29 @@\n (set_attr \"mode\" \"<VBF_DOUBLE_TRUNC>\")\n (set (attr \"frm_mode\")\n (symbol_ref \"riscv_vector::get_frm_mode (operands[8])\"))])\n+\n+;; Zvfofp8min extension: F32 to FP8 narrowing conversions.\n+\n+(define_insn \"@pred_quad_trunc_<mode>_to_<altfmt_sat>\"\n+ [(set (match_operand:<VF_QUAD_TRUNC> 0 \"register_operand\" \"=vd, vd, vr, vr, &vr, &vr\")\n+ (if_then_else:<VF_QUAD_TRUNC>\n+ (unspec:<VM>\n+ [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm, vm,Wc1,Wc1,vmWc1,vmWc1\")\n+ (match_operand 4 \"vector_length_operand\" \" rK, rK, rK, rK, rK, rK\")\n+ (match_operand 5 \"const_int_operand\" \" i, i, i, i, i, i\")\n+ (match_operand 6 \"const_int_operand\" \" i, i, i, i, i, i\")\n+ (match_operand 7 \"const_int_operand\" \" i, i, i, i, i, i\")\n+ (match_operand 8 \"const_int_operand\" \" i, i, i, i, i, i\")\n+ (reg:SI VL_REGNUM)\n+ (reg:SI VTYPE_REGNUM)\n+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)\n+\t (unspec:<VF_QUAD_TRUNC>\n+ [(float_truncate:<VF_QUAD_TRUNC>\n+ (match_operand:VWEXT4_ZVFOFP8MIN 3 \"register_operand\" \" 0, 0, 0, 0, vr, vr\"))] ALTFMT_SAT)\n+ (match_operand:<VF_QUAD_TRUNC> 2 \"vector_merge_operand\" \" vu, 0, vu, 0, vu, 0\")))]\n+ \"TARGET_VECTOR && TARGET_ZVFOFP8MIN\"\n+ \"vfncvt<sat>.f.f.q\\t%0,%3%p1\"\n+ [(set_attr \"type\" \"vfncvtbf16\")\n+ (set_attr \"mode\" \"<VF_QUAD_TRUNC>\")\n+ (set (attr \"frm_mode\")\n+ (symbol_ref \"riscv_vector::get_frm_mode (operands[8])\"))])\n", "prefixes": [ "4/8" ] }