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GET /api/patches/2195893/?format=api
{ "id": 2195893, "url": "http://patchwork.ozlabs.org/api/patches/2195893/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-4-linopeng@andestech.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212091326.2240990-4-linopeng@andestech.com>", "list_archive_url": null, "date": "2026-02-12T09:13:21", "name": "[3/8] RISC-V: Add zvfofp8min BF16 to FP8 narrowing conversions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5ae6e0e266548c04527700347bbb8b53f792ea85", "submitter": { "id": 92634, "url": "http://patchwork.ozlabs.org/api/people/92634/?format=api", "name": "Lino Hsing-Yu Peng", "email": "linopeng@andestech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-4-linopeng@andestech.com/mbox/", "series": [ { "id": 491947, "url": "http://patchwork.ozlabs.org/api/series/491947/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491947", "date": "2026-02-12T09:13:18", "name": "*** Add RISC-V zvfofp8min intrinsic ***", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491947/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195893/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195893/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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Thu, 12 Feb 2026 09:23:36 +0000 (GMT)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 61C9NUTh011568;\n Thu, 12 Feb 2026 17:23:30 +0800 (+08)\n (envelope-from linopeng@andestech.com)", "from atccpl01.andestech.com (10.0.15.149) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Feb\n 2026 17:23:30 +0800" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 510144B9DB76", "OpenDKIM Filter v2.11.0 sourceware.org 7506D4BA23E6" ], "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 7506D4BA23E6", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1770888217; cv=none;\n b=e3AIKmxvhyGKNlMSkgcpJ/lYCuUyBqOPIXurRTMz4MIXFNYQQCFF9CSgaBR02NNrIAwEzIsFrIbQ8cyYIl3IH2ElA5osDIzyzvG3Bgf+bVZ8YVqnzZPBp3dbUUrs3njojJz5QiKgFf10F/4fbjqlGGamjQaD+z2Tr0qSaUkDW4w=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1770888217; c=relaxed/simple;\n bh=FsCTU617gkYvl71rPqUzZsW5sCwPcIqfQlS/L99JqHU=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=QKgDvVd4c35GwzjTHEBwYfO6sdTikY4wfnGBLT1SQuFoz8/XrKME3oNV3n9sdHAQDK02t3dzDm3oUAUaR3Ck9u8Jn6uM7BOlaq3F76Vtg+DKkaE5VzfpGrYXbqRuhn63WjsAOapnbMEfMRH586Dj/6hwRNzwe/qe9pZtEt6nxxU=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Lino Hsing-Yu Peng <linopeng@andestech.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "Lino Hsing-Yu Peng <linopeng1019@gmail.com>", "Subject": "[PATCH 3/8] RISC-V: Add zvfofp8min BF16 to FP8 narrowing conversions", "Date": "Thu, 12 Feb 2026 17:13:21 +0800", "Message-ID": "<20260212091326.2240990-4-linopeng@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260212091326.2240990-3-linopeng@andestech.com>", "References": "<20260212091326.2240990-1-linopeng@andestech.com>\n <20260212091326.2240990-2-linopeng@andestech.com>\n <20260212091326.2240990-3-linopeng@andestech.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.149]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 61C9NUTh011568", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Lino Hsing-Yu Peng <linopeng1019@gmail.com>\n\nImplement Zvfofp8min narrowing conversions from BF16 to FP8, including\nthe saturating variants exposed by the RVV builtin layer. Update builtin\nshapes, operand metadata, and float8 md patterns to cover these forms.\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-vector-builtins-bases.cc: Add f8 narrow and sat conversions.\n\t* config/riscv/riscv-vector-builtins-bases.h: Declare vfncvt_sat_f bases.\n\t* config/riscv/riscv-vector-builtins-functions.def: Add bf16-to-f8 narrow builtins.\n\t* config/riscv/riscv-vector-builtins-shapes.cc: Add f8 narrow shapes and naming.\n\t* config/riscv/riscv-vector-builtins-shapes.h: Declare f8 narrow shapes.\n\t* config/riscv/riscv-vector-builtins.cc: Add bf16_to_f8 operand info.\n\t* config/riscv/vector-float8.md: Add f8 sat variants.\n---\n .../riscv/riscv-vector-builtins-bases.cc | 58 +++++++++-\n .../riscv/riscv-vector-builtins-bases.h | 3 +\n .../riscv/riscv-vector-builtins-functions.def | 9 ++\n .../riscv/riscv-vector-builtins-shapes.cc | 101 +++++++++++++++++-\n .../riscv/riscv-vector-builtins-shapes.h | 4 +\n gcc/config/riscv/riscv-vector-builtins.cc | 9 ++\n gcc/config/riscv/vector-float8.md | 38 ++++++-\n 7 files changed, 216 insertions(+), 6 deletions(-)", "diff": "diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc\nindex 58ab57db5d4..3fa3ebb5d14 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc\n@@ -1526,12 +1526,15 @@ enum altfmt\n static altfmt\n get_altfmt (const function_expander &e)\n {\n- if (e.shape == shapes::alu_f8e4m3)\n+ if (e.shape == shapes::alu_f8e4m3 || e.shape == shapes::narrow_alu_f8e4m3\n+ || e.shape == shapes::narrow_alu_frm_f8e4m3)\n return F8E4M3;\n- if (e.shape == shapes::alu_f8e5m2)\n+ if (e.shape == shapes::alu_f8e5m2 || e.shape == shapes::narrow_alu_f8e5m2\n+ || e.shape == shapes::narrow_alu_frm_f8e5m2)\n return F8E5M2;\n return F8NONE;\n }\n+\n class vfwcvt_f : public function_base\n {\n public:\n@@ -1604,7 +1607,19 @@ public:\n rtx expand (function_expander &e) const override\n {\n if (e.op_info->op == OP_TYPE_f_w)\n- return e.use_exact_insn (code_for_pred_trunc (e.vector_mode ()));\n+ {\n+\tswitch (get_altfmt (e))\n+\t {\n+\t case F8E4M3:\n+\t return e.use_exact_insn (\n+\t code_for_pred_trunc_to (e.vector_mode (), UNSPEC_F8E4M3));\n+\t case F8E5M2:\n+\t return e.use_exact_insn (\n+\t code_for_pred_trunc_to (e.vector_mode (), UNSPEC_F8E5M2));\n+\t default:\n+\t return e.use_exact_insn (code_for_pred_trunc (e.vector_mode ()));\n+\t }\n+ }\n if (e.op_info->op == OP_TYPE_x_w)\n return e.use_exact_insn (code_for_pred_narrow (FLOAT, e.arg_mode (0)));\n if (e.op_info->op == OP_TYPE_xu_w)\n@@ -1614,6 +1629,37 @@ public:\n }\n };\n \n+template <enum frm_op_type FRM_OP = NO_FRM>\n+class vfncvt_sat_f : public function_base\n+{\n+public:\n+ bool has_rounding_mode_operand_p () const override\n+ {\n+ return FRM_OP == HAS_FRM;\n+ }\n+\n+ bool may_require_frm_p () const override { return true; }\n+\n+ rtx expand (function_expander &e) const override\n+ {\n+ if (e.op_info->op == OP_TYPE_f_w)\n+ {\n+\tswitch (get_altfmt (e))\n+\t {\n+\t case F8E4M3:\n+\t return e.use_exact_insn (\n+\t code_for_pred_trunc_to (e.vector_mode (), UNSPEC_F8E4M3_SAT));\n+\t case F8E5M2:\n+\t return e.use_exact_insn (\n+\t code_for_pred_trunc_to (e.vector_mode (), UNSPEC_F8E5M2_SAT));\n+\t default:\n+\t break;\n+\t }\n+ }\n+ gcc_unreachable ();\n+ }\n+};\n+\n class vfncvt_rod_f : public function_base\n {\n public:\n@@ -2809,6 +2855,9 @@ static CONSTEXPR const vfwcvtbf16_f vfwcvtbf16_f_obj;\n /* Zvfbfwma; */\n static CONSTEXPR const vfwmaccbf16<NO_FRM> vfwmaccbf16_obj;\n static CONSTEXPR const vfwmaccbf16<HAS_FRM> vfwmaccbf16_frm_obj;\n+/* Zvfofp8min */\n+static CONSTEXPR const vfncvt_sat_f<NO_FRM> vfncvt_sat_f_obj;\n+static CONSTEXPR const vfncvt_sat_f<HAS_FRM> vfncvt_sat_f_frm_obj;\n \n /* Declare the function base NAME, pointing it to an instance\n of class <NAME>_obj. */\n@@ -3137,4 +3186,7 @@ BASE (vfwcvtbf16_f)\n /* Zvfbfwma */\n BASE (vfwmaccbf16)\n BASE (vfwmaccbf16_frm)\n+/* Zvfofp8min */\n+BASE (vfncvt_sat_f)\n+BASE (vfncvt_sat_f_frm)\n } // end namespace riscv_vector\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h\nindex 9261d353e22..0df8801b7cc 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-bases.h\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h\n@@ -352,6 +352,9 @@ extern const function_base *const vfwcvtbf16_f;\n /* Zvfbfwma */\n extern const function_base *const vfwmaccbf16;\n extern const function_base *const vfwmaccbf16_frm;\n+/* Zvfofp8min */\n+extern const function_base *const vfncvt_sat_f;\n+extern const function_base *const vfncvt_sat_f_frm;\n }\n \n } // end namespace riscv_vector\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def\nindex 185d811e2b7..49ad8585933 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-functions.def\n+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def\n@@ -773,6 +773,15 @@ DEF_RVV_FUNCTION (vfwcvtbf16_f, alu, full_preds, bf16_to_f32_f_v_ops)\n #define REQUIRED_EXTENSIONS ZVFOFP8MIN_EXT\n DEF_RVV_FUNCTION (vfwcvt_f, alu_f8e4m3, full_preds, f8_to_bf16_f_v_ops)\n DEF_RVV_FUNCTION (vfwcvt_f, alu_f8e5m2, full_preds, f8_to_bf16_f_v_ops)\n+DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e4m3, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_f, narrow_alu_f8e5m2, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e4m3, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_sat_f, narrow_alu_f8e5m2, full_preds, bf16_to_f8_f_w_ops)\n+\n+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e4m3, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm_f8e5m2, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e4m3, full_preds, bf16_to_f8_f_w_ops)\n+DEF_RVV_FUNCTION (vfncvt_sat_f_frm, narrow_alu_frm_f8e5m2, full_preds, bf16_to_f8_f_w_ops)\n #undef REQUIRED_EXTENSIONS\n \n /* Zvfbfwma */\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc\nindex 3533ef01714..8385a49f517 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc\n@@ -96,7 +96,11 @@ supports_vectype_p (const function_group_info &group, unsigned int vec_type_idx)\n || *group.shape == shapes::seg_indexed_loadstore\n || *group.shape == shapes::seg_fault_load\n || *group.shape == shapes::alu_f8e4m3\n- || *group.shape == shapes::alu_f8e5m2)\n+ || *group.shape == shapes::alu_f8e5m2\n+ || *group.shape == shapes::narrow_alu_f8e4m3\n+ || *group.shape == shapes::narrow_alu_f8e5m2\n+ || *group.shape == shapes::narrow_alu_frm_f8e4m3\n+ || *group.shape == shapes::narrow_alu_frm_f8e5m2)\n return true;\n return false;\n }\n@@ -797,6 +801,97 @@ struct narrow_alu_def : public build_base\n }\n };\n \n+static char *\n+build_f8_narrow_name (function_builder &b, const function_instance &instance,\n+\t\t bool overloaded_p, const char *altfmt, bool frm_p)\n+{\n+ if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))\n+ return nullptr;\n+\n+ const char *base_name = instance.base_name;\n+ char base_name_buf[BASE_NAME_MAX_LEN] = {};\n+ if (frm_p)\n+ {\n+ build_frm_base::normalize_base_name (base_name_buf, instance.base_name,\n+\t\t\t\t\t sizeof (base_name_buf));\n+ base_name = base_name_buf;\n+ }\n+\n+ b.append_base_name (base_name);\n+\n+ if (overloaded_p)\n+ {\n+ vector_type_index vti\n+\t= instance.op_info->args[0].get_function_type_index (\n+\t instance.type.index);\n+ const char *src_scalar\n+\t= vti == VECTOR_TYPE_INVALID ? nullptr : type_suffixes[vti].scalar;\n+ b.append_name (src_scalar ? src_scalar : \"_bf16\");\n+ b.append_name (\"_\");\n+ b.append_name (altfmt);\n+ }\n+ else\n+ {\n+ b.append_name (operand_suffixes[instance.op_info->op]);\n+ vector_type_index vti\n+\t= instance.op_info->args[0].get_function_type_index (\n+\t instance.type.index);\n+ if (vti != VECTOR_TYPE_INVALID)\n+\tb.append_name (type_suffixes[vti].vector);\n+ append_f8_suffix (b,\n+\t\t\tinstance.op_info->ret.get_function_type_index (\n+\t\t\t instance.type.index),\n+\t\t\taltfmt);\n+ if (frm_p)\n+\tb.append_name (\"_rm\");\n+ }\n+\n+ if (overloaded_p && instance.pred == PRED_TYPE_m)\n+ return b.finish_name ();\n+ b.append_name (predication_suffixes[instance.pred]);\n+ return b.finish_name ();\n+}\n+\n+/* narrow_alu_f8e4m3_def class. */\n+struct narrow_alu_f8e4m3_def : public narrow_alu_def\n+{\n+ char *get_name (function_builder &b, const function_instance &instance,\n+\t\t bool overloaded_p) const override\n+ {\n+ return build_f8_narrow_name (b, instance, overloaded_p, \"f8e4m3\", false);\n+ }\n+};\n+\n+/* narrow_alu_f8e5m2_def class. */\n+struct narrow_alu_f8e5m2_def : public narrow_alu_def\n+{\n+ char *get_name (function_builder &b, const function_instance &instance,\n+\t\t bool overloaded_p) const override\n+ {\n+ return build_f8_narrow_name (b, instance, overloaded_p, \"f8e5m2\", false);\n+ }\n+};\n+\n+/* narrow_alu_frm_f8e4m3_def class. */\n+struct narrow_alu_frm_f8e4m3_def : public narrow_alu_frm_def\n+{\n+ char *get_name (function_builder &b, const function_instance &instance,\n+\t\t bool overloaded_p) const override\n+ {\n+ return build_f8_narrow_name (b, instance, overloaded_p, \"f8e4m3\", true);\n+ }\n+};\n+\n+/* narrow_alu_frm_f8e5m2_def class. */\n+struct narrow_alu_frm_f8e5m2_def : public narrow_alu_frm_def\n+{\n+ char *get_name (function_builder &b, const function_instance &instance,\n+\t\t bool overloaded_p) const override\n+ {\n+ return build_f8_narrow_name (b, instance, overloaded_p, \"f8e5m2\", true);\n+ }\n+};\n+\n /* move_def class. Handle vmv.v.v/vmv.v.x. */\n struct move_def : public build_base\n {\n@@ -1505,4 +1600,8 @@ SHAPE(sf_vcix, sf_vcix)\n /* Zvfofp8min */\n SHAPE (alu_f8e4m3, alu_f8e4m3)\n SHAPE (alu_f8e5m2, alu_f8e5m2)\n+SHAPE (narrow_alu_f8e4m3, narrow_alu_f8e4m3)\n+SHAPE (narrow_alu_f8e5m2, narrow_alu_f8e5m2)\n+SHAPE (narrow_alu_frm_f8e4m3, narrow_alu_frm_f8e4m3)\n+SHAPE (narrow_alu_frm_f8e5m2, narrow_alu_frm_f8e5m2)\n } // end namespace riscv_vector\ndiff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h\nindex d700d76da30..0158c82bd3b 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-shapes.h\n+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h\n@@ -67,6 +67,10 @@ extern const function_shape *const sf_vcix;\n /* Zvfofp8min extension. */\n extern const function_shape *const alu_f8e4m3;\n extern const function_shape *const alu_f8e5m2;\n+extern const function_shape *const narrow_alu_f8e4m3;\n+extern const function_shape *const narrow_alu_f8e5m2;\n+extern const function_shape *const narrow_alu_frm_f8e4m3;\n+extern const function_shape *const narrow_alu_frm_f8e5m2;\n }\n \n } // end namespace riscv_vector\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc\nindex a7ad068b00a..c671b133c85 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins.cc\n@@ -2058,6 +2058,15 @@ static CONSTEXPR const rvv_op_info f_to_nf_f_w_ops\n rvv_arg_type_info (RVV_BASE_double_trunc_float_vector), /* Return type */\n v_args /* Args */};\n \n+/* A static operand information for vector_type func (vector_type)\n+ * function registration. */\n+static CONSTEXPR const rvv_op_info bf16_to_f8_f_w_ops\n+ = {bf_ops,\t /* Types */\n+ OP_TYPE_f_w, /* Suffix */\n+ rvv_arg_type_info (\n+ RVV_BASE_double_trunc_unsigned_vector), /* Return type */\n+ v_args /* Args */};\n+\n /* A static operand information for vector_type func (vector_type)\n * function registration. */\n static CONSTEXPR const rvv_op_info f8_to_bf16_f_v_ops\ndiff --git a/gcc/config/riscv/vector-float8.md b/gcc/config/riscv/vector-float8.md\nindex 2a3eeeaa1db..423b490b811 100644\n--- a/gcc/config/riscv/vector-float8.md\n+++ b/gcc/config/riscv/vector-float8.md\n@@ -35,10 +35,18 @@\n (RVVMF4BF \"RVVMF8QI\")\n ])\n \n-(define_int_iterator ALTFMT [UNSPEC_F8E4M3 UNSPEC_F8E5M2])\n+(define_int_iterator ALTFMT [UNSPEC_F8E4M3 UNSPEC_F8E5M2 UNSPEC_F8E4M3_SAT UNSPEC_F8E5M2_SAT])\n (define_int_attr altfmt\n [(UNSPEC_F8E4M3 \"f8e4m3\")\n- (UNSPEC_F8E5M2 \"f8e5m2\")])\n+ (UNSPEC_F8E5M2 \"f8e5m2\")\n+ (UNSPEC_F8E4M3_SAT \"f8e4m3_sat\")\n+ (UNSPEC_F8E5M2_SAT \"f8e5m2_sat\")])\n+\n+(define_int_attr sat\n+ [(UNSPEC_F8E4M3 \"\")\n+ (UNSPEC_F8E5M2 \"\")\n+ (UNSPEC_F8E4M3_SAT \".sat\")\n+ (UNSPEC_F8E5M2_SAT \".sat\")])\n \n ;; Zvfofp8min extension: FP8 to BF16 widening conversions.\n \n@@ -61,3 +69,29 @@\n \"vfwcvtbf16.f.f.v\\t%0,%3%p1\"\n [(set_attr \"type\" \"vfwcvtbf16\")\n (set_attr \"mode\" \"<VBF_DOUBLE_TRUNC>\")])\n+\n+;; Zvfofp8min extension: BF16 to FP8 narrowing conversions.\n+\n+(define_insn \"@pred_trunc_<mode>_to_<altfmt>\"\n+ [(set (match_operand:<VBF_DOUBLE_TRUNC> 0 \"register_operand\" \"=vd, vd, vr, vr, &vr, &vr\")\n+ (if_then_else:<VBF_DOUBLE_TRUNC>\n+ (unspec:<VM>\n+ [(match_operand:<VM> 1 \"vector_mask_operand\" \" vm, vm,Wc1,Wc1,vmWc1,vmWc1\")\n+ (match_operand 4 \"vector_length_operand\" \" rK, rK, rK, rK, rK, rK\")\n+ (match_operand 5 \"const_int_operand\" \" i, i, i, i, i, i\")\n+ (match_operand 6 \"const_int_operand\" \" i, i, i, i, i, i\")\n+ (match_operand 7 \"const_int_operand\" \" i, i, i, i, i, i\")\n+ (match_operand 8 \"const_int_operand\" \" i, i, i, i, i, i\")\n+ (reg:SI VL_REGNUM)\n+ (reg:SI VTYPE_REGNUM)\n+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)\n+\t (unspec:<VBF_DOUBLE_TRUNC>\n+ [(float_truncate:<VBF_DOUBLE_TRUNC>\n+\t (match_operand:VWEXTF_ZVFOFP8MIN 3 \"register_operand\" \" 0, 0, 0, 0, vr, vr\"))] ALTFMT)\n+ (match_operand:<VBF_DOUBLE_TRUNC> 2 \"vector_merge_operand\" \" vu, 0, vu, 0, vu, 0\")))]\n+ \"TARGET_VECTOR && TARGET_ZVFOFP8MIN && TARGET_ZVFBFMIN\"\n+ \"vfncvtbf16<sat>.f.f.w\\t%0,%3%p1\"\n+ [(set_attr \"type\" \"vfncvtbf16\")\n+ (set_attr \"mode\" \"<VBF_DOUBLE_TRUNC>\")\n+ (set (attr \"frm_mode\")\n+ (symbol_ref \"riscv_vector::get_frm_mode (operands[8])\"))])\n", "prefixes": [ "3/8" ] }