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GET /api/patches/2195892/?format=api
{ "id": 2195892, "url": "http://patchwork.ozlabs.org/api/patches/2195892/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-2-linopeng@andestech.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212091326.2240990-2-linopeng@andestech.com>", "list_archive_url": null, "date": "2026-02-12T09:13:19", "name": "[1/8] RISC-V: Add zvfofp8min ISA extension support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "311e8935f71d06448fadecfc42c3096a9947a296", "submitter": { "id": 92634, "url": "http://patchwork.ozlabs.org/api/people/92634/?format=api", "name": "Lino Hsing-Yu Peng", "email": "linopeng@andestech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260212091326.2240990-2-linopeng@andestech.com/mbox/", "series": [ { "id": 491947, "url": "http://patchwork.ozlabs.org/api/series/491947/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491947", "date": "2026-02-12T09:13:18", "name": "*** Add RISC-V zvfofp8min intrinsic ***", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491947/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195892/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195892/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n dmarc=permerror header.from=andestech.com", "sourceware.org; spf=pass smtp.mailfrom=andestech.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=60.248.187.195" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fBVGk5zyBz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 12 Feb 2026 20:23:42 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id D2B014B9DB4B\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 12 Feb 2026 09:23:40 +0000 (GMT)", "from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195])\n by sourceware.org (Postfix) with ESMTPS id 207B24BA23E1\n for <gcc-patches@gcc.gnu.org>; Thu, 12 Feb 2026 09:23:11 +0000 (GMT)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 61C9N3uH011462;\n Thu, 12 Feb 2026 17:23:03 +0800 (+08)\n (envelope-from linopeng@andestech.com)", "from atccpl01.andestech.com (10.0.15.149) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Feb\n 2026 17:23:03 +0800" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org D2B014B9DB4B", "OpenDKIM Filter v2.11.0 sourceware.org 207B24BA23E1" ], "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 207B24BA23E1", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1770888192; cv=none;\n b=tssOO4r0MZltEyYuHjFEOgdmhiK+9H8X4tzDYS40ek8uK24Ma1X3In1sSBzR+RCBD+DpUJaBa3tWt+GyQAzb97AbSyTJnwpVStk62GWvDEobdZ6LfcMeCYb9aVYn0CTJMQFJMELkJmow5zmd55IDgy8JuEJ6JTWOUPGDgdLHBWg=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1770888192; c=relaxed/simple;\n bh=J3pAZ5a+zTsBmsMn1xwc/7HMpnGblkBVWjcMtx4uy4U=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=rW2h5UYwj73Z/+yfbY3zpOybrDnQoTRktTXq7dpfKgQ2W46xjIiBT4AZJa5VicjCiC7izO5nZJsryPubOkmHmAGZwsDw3BHoG5cGpsLd17k/EMiK4GVz9oM5Viavq0Ymhi/OenQ5dqDjAjLoC/TQk2pbhg1oJmUS/4uXmqj+J5k=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Lino Hsing-Yu Peng <linopeng@andestech.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "Lino Hsing-Yu Peng <linopeng1019@gmail.com>", "Subject": "[PATCH 1/8] RISC-V: Add zvfofp8min ISA extension support", "Date": "Thu, 12 Feb 2026 17:13:19 +0800", "Message-ID": "<20260212091326.2240990-2-linopeng@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260212091326.2240990-1-linopeng@andestech.com>", "References": "<20260212091326.2240990-1-linopeng@andestech.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.149]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 61C9N3uH011462", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Lino Hsing-Yu Peng <linopeng1019@gmail.com>\n\nAdd initial ISA-level for Zvfofp8min extension.\n\ngcc/ChangeLog:\n\n\t* common/config/riscv/riscv-common.cc: Add zvfofp8min support.\n\t* config/riscv/riscv-ext.def: Add zvfofp8min entry.\n\t* config/riscv/riscv-ext.opt: Add zvfofp8min option.\n\t* config/riscv/riscv-vector-builtins.cc: Require zvfofp8min.\n\t* config/riscv/riscv-vector-builtins.h: Add zvfofp8min handling.\n\t* doc/riscv-ext.texi: Document the new extension.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/arch-61.c: New test.\n---\n gcc/common/config/riscv/riscv-common.cc | 2 ++\n gcc/config/riscv/riscv-ext.def | 13 +++++++++++++\n gcc/config/riscv/riscv-ext.opt | 3 ++-\n gcc/config/riscv/riscv-vector-builtins.cc | 2 ++\n gcc/config/riscv/riscv-vector-builtins.h | 7 +++++++\n gcc/doc/riscv-ext.texi | 4 ++++\n gcc/testsuite/gcc.target/riscv/arch-61.c | 5 +++++\n 7 files changed, 35 insertions(+), 1 deletion(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/arch-61.c", "diff": "diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc\nindex 5d3d37c7a7b..8c4b3c4dd4b 100644\n--- a/gcc/common/config/riscv/riscv-common.cc\n+++ b/gcc/common/config/riscv/riscv-common.cc\n@@ -1485,6 +1485,8 @@ static const riscv_extra_ext_flag_table_t riscv_extra_ext_flag_table[] =\n RISCV_EXT_FLAG_ENTRY (\"zvfbfwma\", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16),\n RISCV_EXT_FLAG_ENTRY (\"zvfhmin\", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16),\n RISCV_EXT_FLAG_ENTRY (\"zvfh\", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16),\n+ RISCV_EXT_FLAG_ENTRY (\"zvfofp8min\", x_riscv_vector_elen_flags,\n+\t\t\tMASK_VECTOR_ELEN_FP_32),\n \n RISCV_EXT_FLAG_ENTRY (\"xtheadvector\", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32),\n RISCV_EXT_FLAG_ENTRY (\"xtheadvector\", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64),\ndiff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def\nindex 1621e81b011..860ee34796b 100644\n--- a/gcc/config/riscv/riscv-ext.def\n+++ b/gcc/config/riscv/riscv-ext.def\n@@ -1156,6 +1156,19 @@ DEFINE_RISCV_EXT(\n /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,\n /* EXTRA_EXTENSION_FLAGS */ 0)\n \n+DEFINE_RISCV_EXT(\n+ /* NAME */ zvfofp8min,\n+ /* UPPERCASE_NAME */ ZVFOFP8MIN,\n+ /* FULL_NAME */ \"Vector FP8 minimum extension\",\n+ /* DESC */ \"\",\n+ /* URL */ ,\n+ /* DEP_EXTS */ ({\"zve32f\"}),\n+ /* SUPPORTED_VERSIONS */ ({{0, 2}}),\n+ /* FLAG_GROUP */ zvf,\n+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,\n+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,\n+ /* EXTRA_EXTENSION_FLAGS */ 0)\n+\n DEFINE_RISCV_EXT(\n /* NAME */ zvfbfwma,\n /* UPPERCASE_NAME */ ZVFBFWMA,\ndiff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt\nindex 18402ea97c7..6725175f903 100644\n--- a/gcc/config/riscv/riscv-ext.opt\n+++ b/gcc/config/riscv/riscv-ext.opt\n@@ -264,6 +264,8 @@ Mask(ZVE64X) Var(riscv_zve_subext)\n \n Mask(ZVFBFMIN) Var(riscv_zvf_subext)\n \n+Mask(ZVFOFP8MIN) Var(riscv_zvf_subext)\n+\n Mask(ZVFBFWMA) Var(riscv_zvf_subext)\n \n Mask(ZVFH) Var(riscv_zvf_subext)\n@@ -471,4 +473,3 @@ Mask(XANDESVPACKFPH) Var(riscv_xandes_subext)\n Mask(XANDESVDOT) Var(riscv_xandes_subext)\n \n Mask(XSMTVDOT) Var(riscv_xsmt_subext)\n-\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc\nindex 92f343c0044..5892ae5e466 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins.cc\n@@ -3654,6 +3654,8 @@ get_builtin_partition (required_ext ext, const function_instance &instance)\n return RVV_PARTITION_ZVFBFMIN;\n case ZVFBFWMA_EXT:\n return RVV_PARTITION_ZVFBFWMA;\n+ case ZVFOFP8MIN_EXT:\n+ return RVV_PARTITION_ZVFOFP8MIN;\n case XSFVQMACCQOQ_EXT:\n return RVV_PARTITION_XSFVQMACCQOQ;\n case XSFVQMACCDOD_EXT:\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h\nindex d5fe0cd7a22..224a90c0b26 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.h\n+++ b/gcc/config/riscv/riscv-vector-builtins.h\n@@ -110,6 +110,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5;\n #define RVV_REQUIRE_MIN_VLEN_64 (1 << 5)\t/* Require TARGET_MIN_VLEN >= 64. */\n #define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32. */\n #define RVV_REQUIRE_ELEN_BF_16 (1 << 7) /* Require BF16. */\n+#define RVV_REQUIRE_ZVFOFP8MIN (1 << 8) /* Require ZVFOFP8MIN extension. */\n \n /* Enumerates the required extensions. */\n enum required_ext\n@@ -129,6 +130,7 @@ enum required_ext\n ZVKSH_EXT,\t\t/* Crypto vector Zvksh sub-ext */\n ZVFBFMIN_EXT,\t\t/* Zvfbfmin extension */\n ZVFBFWMA_EXT,\t\t/* Zvfbfwma extension */\n+ ZVFOFP8MIN_EXT,\t/* Zvfofp8min extension */\n XSFVQMACCQOQ_EXT,\t/* XSFVQMACCQOQ extension */\n XSFVQMACCDOD_EXT,\t/* XSFVQMACCDOD extension */\n XSFVFNRCLIPXFQF_EXT,\t/* XSFVFNRCLIPXFQF extension */\n@@ -159,6 +161,7 @@ enum rvv_builtin_partition\n RVV_PARTITION_ZVFBFWMA,\n RVV_PARTITION_ZVFHMIN,\n RVV_PARTITION_ZVFH,\n+ RVV_PARTITION_ZVFOFP8MIN,\n RVV_PARTITION_XSFVQMACCQOQ,\n RVV_PARTITION_XSFVQMACCDOD,\n RVV_PARTITION_XSFVFNRCLIPXFQF,\n@@ -211,6 +214,8 @@ static inline const char * required_ext_to_isa_name (enum required_ext required)\n return \"zvfbfmin\";\n case ZVFBFWMA_EXT:\n return \"zvfbfwma\";\n+ case ZVFOFP8MIN_EXT:\n+ return \"zvfofp8min\";\n case XSFVQMACCQOQ_EXT:\n return \"xsfvqmaccqoq\";\n case XSFVQMACCDOD_EXT:\n@@ -266,6 +271,8 @@ static inline bool required_extensions_specified (enum required_ext required)\n return TARGET_ZVFBFMIN;\n case ZVFBFWMA_EXT:\n return TARGET_ZVFBFWMA;\n+ case ZVFOFP8MIN_EXT:\n+ return TARGET_ZVFOFP8MIN;\n case XSFVQMACCQOQ_EXT:\n return TARGET_XSFVQMACCQOQ;\n case XSFVQMACCDOD_EXT:\ndiff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi\nindex 36b4dff31ff..1511c8be993 100644\n--- a/gcc/doc/riscv-ext.texi\n+++ b/gcc/doc/riscv-ext.texi\n@@ -334,6 +334,10 @@\n @tab 1.0\n @tab Vector BF16 converts extension\n \n+@item @samp{zvfofp8min}\n+@tab 0.2\n+@tab Vector FP8 minimum extension\n+\n @item @samp{zvfbfwma}\n @tab 1.0\n @tab Vector BF16 widening multiply/add extension\ndiff --git a/gcc/testsuite/gcc.target/riscv/arch-61.c b/gcc/testsuite/gcc.target/riscv/arch-61.c\nnew file mode 100644\nindex 00000000000..921a43cebd6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/arch-61.c\n@@ -0,0 +1,5 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv64gc_zvfofp8min -mabi=lp64\" } */\n+int\n+foo ()\n+{}\n", "prefixes": [ "1/8" ] }