Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2195862/?format=api
{ "id": 2195862, "url": "http://patchwork.ozlabs.org/api/patches/2195862/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260212072229.3247604-2-shengjiu.wang@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20260212072229.3247604-2-shengjiu.wang@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20260212072229.3247604-2-shengjiu.wang@nxp.com/", "date": "2026-02-12T07:22:28", "name": "[v2,1/2] ASoC: fsl_sai: add bitcount and timestamp controls", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9d9592a514f4531ca14dfbcd0ac0a676bd19f9a1", "submitter": { "id": 75958, "url": "http://patchwork.ozlabs.org/api/people/75958/?format=api", "name": "Shengjiu Wang", "email": "shengjiu.wang@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260212072229.3247604-2-shengjiu.wang@nxp.com/mbox/", "series": [ { "id": 491938, "url": "http://patchwork.ozlabs.org/api/series/491938/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=491938", "date": "2026-02-12T07:22:27", "name": "ASoC: fsl: add bitcount and timestamp controls", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491938/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195862/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195862/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev+bounces-16828-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=Bm3cPhb+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=112.213.38.117; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-16828-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n arc=pass smtp.remote-ip=\"2a01:111:f403:c202::7\" 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envelope-from=shengjiu.wang@nxp.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=nxp.com", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=fmt6dOEJ2eJjHWDQwiZl8R52eiRqVhFjKRYWaP8Xvgg=;\n b=Bm3cPhb+atnKwBK6WPJMmZ/OLnZWNT3e8y6SzYFQaubs1jlB9h+zIBXGDDJhBbkWTaJMZ9XLAVy/N6CAuYl1dfDXrxVMHBN/1dVjijbyAFI4vEVNJShmR51+tgY6BvPn8YgNEyaWgjrU6u1aKMJg4uwLPGERnuwSsU1bb1P5rNjokhYxMfBpj6yOkhXP1w7/iqaa33lh66hx+FucDYBX2/MRPb8WXh0T+UMolnqGbR+Tli8+Zier2vSPumISrjC05mJJEtfBjkajxEtNaCn9KKwObnOPVHp4Iw/Pct2gHk0EsTHnu579is6cfNeNIhH3muQ8ndMvwi2cQ5VBRIoJXg==", "From": "Shengjiu Wang <shengjiu.wang@nxp.com>", "To": "shengjiu.wang@gmail.com,\n\tXiubo.Lee@gmail.com,\n\tfestevam@gmail.com,\n\tnicoleotsuka@gmail.com,\n\tlgirdwood@gmail.com,\n\tbroonie@kernel.org,\n\tperex@perex.cz,\n\ttiwai@suse.com,\n\tlinux-sound@vger.kernel.org,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2 1/2] ASoC: fsl_sai: add bitcount and timestamp controls", "Date": "Thu, 12 Feb 2026 15:22:28 +0800", "Message-Id": "<20260212072229.3247604-2-shengjiu.wang@nxp.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20260212072229.3247604-1-shengjiu.wang@nxp.com>", "References": "<20260212072229.3247604-1-shengjiu.wang@nxp.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SI2PR02CA0023.apcprd02.prod.outlook.com\n (2603:1096:4:195::11) To VI1PR04MB7055.eurprd04.prod.outlook.com\n (2603:10a6:800:123::21)", "X-Mailing-List": "linuxppc-dev@lists.ozlabs.org", "List-Id": "<linuxppc-dev.lists.ozlabs.org>", "List-Help": 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lists.ozlabs.org" }, "content": "The transmitter and receiver implement separate timestamp counters and\nbit counters. The bit counter increments at the end of each bit in a\nframe whenever the transmitter or receiver is enabled. The bit counter\ncan be reset by software. The timestamp counter increments on the bus\ninterface clock whenever it is enabled. The current value of the\ntimestamp counter is latched whenever the bit counter increments.\nReading the bit counter register will cause the latched timestamp\nvalue to be saved in the bit counter timestamp register. The timestamp\ncounter can be reset by software, this also resets the latched timestamp\nvalue and the bit counter timestamp register.\n\nThe timestamp counter and bit counter can be used by software to track\nthe progress of the transmitter and receiver. It can also be used to\ncalculate the relative frequency of the bit clock against the bus\ninterface clock.\n\nThese bitcount and timestamp registers are volatile, and supported when\nthe module has timestamp features.\n\nSigned-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>\n---\n sound/soc/fsl/fsl_sai.c | 50 +++++++++++++++++++++++++++++++++++++++++\n sound/soc/fsl/fsl_sai.h | 4 ++++\n 2 files changed, 54 insertions(+)", "diff": "diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c\nindex 148e09e58dfa..632be4d6ae69 100644\n--- a/sound/soc/fsl/fsl_sai.c\n+++ b/sound/soc/fsl/fsl_sai.c\n@@ -41,6 +41,36 @@ static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {\n \t.list = fsl_sai_rates,\n };\n \n+static const char * const inc_mode[] = {\n+\t\"On enabled and bitcount increment\", \"On enabled\"\n+};\n+\n+static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum,\n+\t\t\t FSL_SAI_TTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode);\n+static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum,\n+\t\t\t FSL_SAI_RTCTL, FSL_SAI_xTCTL_TSINC_SHIFT, inc_mode);\n+\n+static const struct snd_kcontrol_new fsl_sai_timestamp_ctrls[] = {\n+\tSOC_SINGLE(\"Transmit Timestamp Control Switch\", FSL_SAI_TTCTL,\n+\t\t FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0),\n+\tSOC_ENUM(\"Transmit Timestamp Increment\", transmit_tstmp_enum),\n+\tSOC_SINGLE(\"Transmit Timestamp Reset\", FSL_SAI_TTCTL, FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0),\n+\tSOC_SINGLE(\"Transmit Bit Counter Reset\", FSL_SAI_TTCTL, FSL_SAI_xTCTL_RBC_SHIFT, 1, 0),\n+\tSOC_SINGLE_XR_SX(\"Transmit Timestamp Counter\", FSL_SAI_TTCTN, 1, 32, 0, 0xffffffff, 0),\n+\tSOC_SINGLE_XR_SX(\"Transmit Bit Counter\", FSL_SAI_TBCTN, 1, 32, 0, 0xffffffff, 0),\n+\tSOC_SINGLE_XR_SX(\"Transmit Latched Timestamp Counter\", FSL_SAI_TTCAP,\n+\t\t\t 1, 32, 0, 0xffffffff, 0),\n+\tSOC_SINGLE(\"Receive Timestamp Control Switch\", FSL_SAI_RTCTL,\n+\t\t FSL_SAI_xTCTL_TSEN_SHIFT, 1, 0),\n+\tSOC_ENUM(\"Receive Timestamp Increment\", receive_tstmp_enum),\n+\tSOC_SINGLE(\"Receive Timestamp Reset\", FSL_SAI_RTCTL, FSL_SAI_xTCTL_RTSC_SHIFT, 1, 0),\n+\tSOC_SINGLE(\"Receive Bit Counter Reset\", FSL_SAI_RTCTL, FSL_SAI_xTCTL_RBC_SHIFT, 1, 0),\n+\tSOC_SINGLE_XR_SX(\"Receive Timestamp Counter\", FSL_SAI_RTCTN, 1, 32, 0, 0xffffffff, 0),\n+\tSOC_SINGLE_XR_SX(\"Receive Bit Counter\", FSL_SAI_RBCTN, 1, 32, 0, 0xffffffff, 0),\n+\tSOC_SINGLE_XR_SX(\"Receive Latched Timestamp Counter\", FSL_SAI_RTCAP,\n+\t\t\t 1, 32, 0, 0xffffffff, 0),\n+};\n+\n /**\n * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream\n *\n@@ -1010,6 +1040,17 @@ static int fsl_sai_dai_resume(struct snd_soc_component *component)\n \treturn 0;\n }\n \n+static int fsl_sai_component_probe(struct snd_soc_component *component)\n+{\n+\tstruct fsl_sai *sai = snd_soc_component_get_drvdata(component);\n+\n+\tif (sai->verid.feature & FSL_SAI_VERID_TSTMP_EN)\n+\t\tsnd_soc_add_component_controls(component, fsl_sai_timestamp_ctrls,\n+\t\t\t\t\t ARRAY_SIZE(fsl_sai_timestamp_ctrls));\n+\n+\treturn 0;\n+}\n+\n static struct snd_soc_dai_driver fsl_sai_dai_template[] = {\n \t{\n \t\t.name = \"sai-tx-rx\",\n@@ -1063,6 +1104,7 @@ static struct snd_soc_dai_driver fsl_sai_dai_template[] = {\n \n static const struct snd_soc_component_driver fsl_component = {\n \t.name\t\t\t= \"fsl-sai\",\n+\t.probe\t\t\t= fsl_sai_component_probe,\n \t.resume\t\t\t= fsl_sai_dai_resume,\n \t.legacy_dai_naming\t= 1,\n };\n@@ -1211,6 +1253,14 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)\n \tcase FSL_SAI_RDR5:\n \tcase FSL_SAI_RDR6:\n \tcase FSL_SAI_RDR7:\n+\tcase FSL_SAI_TTCTN:\n+\tcase FSL_SAI_RTCTN:\n+\tcase FSL_SAI_TTCTL:\n+\tcase FSL_SAI_TBCTN:\n+\tcase FSL_SAI_TTCAP:\n+\tcase FSL_SAI_RTCTL:\n+\tcase FSL_SAI_RBCTN:\n+\tcase FSL_SAI_RTCAP:\n \t\treturn true;\n \tdefault:\n \t\treturn false;\ndiff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h\nindex 7605cbaca3d8..af967833b6ed 100644\n--- a/sound/soc/fsl/fsl_sai.h\n+++ b/sound/soc/fsl/fsl_sai.h\n@@ -196,9 +196,13 @@\n #define FSL_SAI_MDIV_MASK\t 0xFFFFF\n \n /* SAI timestamp and bitcounter */\n+#define FSL_SAI_xTCTL_TSEN_SHIFT 0\n #define FSL_SAI_xTCTL_TSEN BIT(0)\n+#define FSL_SAI_xTCTL_TSINC_SHIFT 1\n #define FSL_SAI_xTCTL_TSINC BIT(1)\n+#define FSL_SAI_xTCTL_RTSC_SHIFT 8\n #define FSL_SAI_xTCTL_RTSC BIT(8)\n+#define FSL_SAI_xTCTL_RBC_SHIFT 9\n #define FSL_SAI_xTCTL_RBC BIT(9)\n \n /* SAI type */\n", "prefixes": [ "v2", "1/2" ] }