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GET /api/patches/2195823/?format=api
{ "id": 2195823, "url": "http://patchwork.ozlabs.org/api/patches/2195823/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260212-imx95_frdm-v2-1-9a535a506b95@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212-imx95_frdm-v2-1-9a535a506b95@nxp.com>", "list_archive_url": null, "date": "2026-02-12T02:40:50", "name": "[v2,1/2] arm64: dts: freescale: add basic dts for FRDM-IMX95 in u-boot", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "c510ba85ee5c12deb51e0c4f3f2b8761a370a947", "submitter": { "id": 91282, "url": "http://patchwork.ozlabs.org/api/people/91282/?format=api", "name": "Joseph Guo", "email": "qijian.guo@nxp.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260212-imx95_frdm-v2-1-9a535a506b95@nxp.com/mbox/", "series": [ { "id": 491933, "url": "http://patchwork.ozlabs.org/api/series/491933/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491933", "date": "2026-02-12T02:40:50", "name": "Add i.MX95 15x15 FRDM support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491933/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195823/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195823/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=nxp.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=nxp.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=qijian.guo@nxp.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fBNCj6spPz1xpY\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 12 Feb 2026 15:50:41 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id E739883DA7;\n\tThu, 12 Feb 2026 05:50:31 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 1ED0983CBD; Thu, 12 Feb 2026 03:41:02 +0100 (CET)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 38FAA83B64\n for <u-boot@lists.denx.de>; Thu, 12 Feb 2026 03:40:59 +0100 (CET)", "from inva020.nxp.com (localhost [127.0.0.1])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id F1D8E1A178A;\n Thu, 12 Feb 2026 03:40:58 +0100 (CET)", "from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5E7D31A100A;\n Thu, 12 Feb 2026 03:40:58 +0100 (CET)", "from lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com\n (lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com [10.52.9.99])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 840FC1800097;\n Thu, 12 Feb 2026 10:40:55 +0800 (+08)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.9 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "From": "Joseph Guo <qijian.guo@nxp.com>", "Date": "Thu, 12 Feb 2026 11:40:50 +0900", "Subject": "[PATCH v2 1/2] arm64: dts: freescale: add basic dts for FRDM-IMX95\n in u-boot", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260212-imx95_frdm-v2-1-9a535a506b95@nxp.com>", "References": "<20260212-imx95_frdm-v2-0-9a535a506b95@nxp.com>", "In-Reply-To": "<20260212-imx95_frdm-v2-0-9a535a506b95@nxp.com>", "To": "u-boot@lists.denx.de, \"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>", "Cc": "Tom Rini <trini@konsulko.com>, Sumit Garg <sumit.garg@kernel.org>,\n Lei Xu <lei.xu@nxp.com>, Stefano Babic <sbabic@nabladev.com>,\n Fabio Estevam <festevam@gmail.com>, Ye Li <ye.li@nxp.com>,\n Alice Guo <alice.guo@nxp.com>, Peng Fan <peng.fan@nxp.com>,\n Adam Ford <aford173@gmail.com>,\n Frieder Schrempf <frieder.schrempf@kontron.de>,\n Sam Protsenko <semen.protsenko@linaro.org>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>, Ji Luo <ji.luo@nxp.com>,\n Simon Glass <sjg@chromium.org>, Justin Jiang <justin.jiang@nxp.com>,\n qijian.guo@oss.nxp.com, xinyu.chen@nxp.com, Jacky Bai <ping.bai@nxp.com>,\n Tim Harvey <tharvey@gateworks.com>, Joseph Guo <qijian.guo@nxp.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1770864052; l=25347;\n i=qijian.guo@nxp.com; s=20250519; h=from:subject:message-id;\n bh=iAZyxbt401x7sqmSI827IdjV6Q6NQByZO9Vln+MjNi0=;\n b=SNHA2ncm18TISeTyp6NYaTesdCmH5xy2z739JeNuORxB38sQm5Ei86b+3Y5vFSgMoHtfjY+kI\n gX6OjVzMymvBKJYR0qMG1XhKEkkeZuCklGbcQBVuqf/yaIDNjAAeZXn", "X-Developer-Key": "i=qijian.guo@nxp.com; a=ed25519;\n pk=VRjOOFhVecTRwBzK4mt/k3JBnHoYfuXKCm9FM+hHQhs=", "X-Mailman-Approved-At": "Thu, 12 Feb 2026 05:50:31 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add the device tree files for the FRDM-IMX95 board\n\nFRDM-IMX95 dts already upstreamed:\nhttps://lore.kernel.org/all/20260116-127-v3-2-3dc49545a745@nxp.com/\n\nSigned-off-by: Lei Xu <lei.xu@nxp.com>\nSigned-off-by: Joseph Guo <qijian.guo@nxp.com>\n---\nChange in v2:\n- move dts file into arch/arm/dts\n---\n arch/arm/dts/imx95-15x15-frdm.dts | 964 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 964 insertions(+)", "diff": "diff --git a/arch/arm/dts/imx95-15x15-frdm.dts b/arch/arm/dts/imx95-15x15-frdm.dts\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ca1c4966c8670d4c76c0dd696452481375512e26\n--- /dev/null\n+++ b/arch/arm/dts/imx95-15x15-frdm.dts\n@@ -0,0 +1,964 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright 2025 NXP\n+ */\n+\n+/dts-v1/;\n+\n+#include <dt-bindings/leds/common.h>\n+#include <dt-bindings/phy/phy-imx8-pcie.h>\n+#include <dt-bindings/pwm/pwm.h>\n+#include <dt-bindings/usb/pd.h>\n+#include \"imx95.dtsi\"\n+\n+#define BRD_SM_CTRL_SD3_WAKE\t\t0x8000\t/*!< PCAL6408A-0 */\n+#define BRD_SM_CTRL_PCIE1_WAKE\t\t0x8001\t/*!< PCAL6408A-4 */\n+#define BRD_SM_CTRL_BT_WAKE\t\t0x8002\t/*!< PCAL6408A-5 */\n+#define BRD_SM_CTRL_PCIE2_WAKE\t\t0x8003\t/*!< PCAL6408A-6 */\n+#define BRD_SM_CTRL_BUTTON\t\t0x8004\t/*!< PCAL6408A-7 */\n+\n+/ {\n+\tcompatible = \"fsl,imx95-15x15-frdm\", \"fsl,imx95\";\n+\tmodel = \"NXP i.MX95 15X15 FRDM board\";\n+\n+\taliases {\n+\t\tethernet0 = &enetc_port0;\n+\t\tethernet1 = &enetc_port1;\n+\t\tgpio0 = &gpio1;\n+\t\tgpio1 = &gpio2;\n+\t\tgpio2 = &gpio3;\n+\t\tgpio3 = &gpio4;\n+\t\tgpio4 = &gpio5;\n+\t\ti2c0 = &lpi2c1;\n+\t\ti2c1 = &lpi2c2;\n+\t\ti2c2 = &lpi2c3;\n+\t\ti2c3 = &lpi2c4;\n+\t\ti2c4 = &lpi2c5;\n+\t\ti2c5 = &lpi2c6;\n+\t\ti2c6 = &lpi2c7;\n+\t\ti2c7 = &lpi2c8;\n+\t\tmmc0 = &usdhc1;\n+\t\tmmc1 = &usdhc2;\n+\t\tmmc2 = &usdhc3;\n+\t\tserial0 = &lpuart1;\n+\t\tserial4 = &lpuart5;\n+\t};\n+\n+\tchosen {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tstdout-path = &lpuart1;\n+\t};\n+\n+\tdmic: dmic {\n+\t\tcompatible = \"dmic-codec\";\n+\t\t#sound-dai-cells = <0>;\n+\t\tnum-channels = <2>;\n+\t};\n+\n+\tflexcan2_phy: can-phy {\n+\t\tcompatible = \"nxp,tja1051\";\n+\t\t#phy-cells = <0>;\n+\t\tmax-bitrate = <5000000>;\n+\t\t/*\n+\t\t * Shared SILENT GPIO: CAN PHYs enter silent mode\n+\t\t * together (hardware design).\n+\t\t */\n+\t\tsilent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tflexcan5_phy: can-phy {\n+\t\tcompatible = \"nxp,tja1051\";\n+\t\t#phy-cells = <0>;\n+\t\tmax-bitrate = <5000000>;\n+\t\tsilent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\treg_1p8v: regulator-1p8v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-name = \"+V1.8_SW\";\n+\t};\n+\n+\treg_3p3v: regulator-3p3v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"+V3.3_SW\";\n+\t};\n+\n+\treg_5p0v: regulator-5p0v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-name = \"+V5.0_SW\";\n+\t};\n+\n+\treg_ext_3v3: regulator-ext-3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"VCCEXT_3V3\";\n+\t};\n+\n+\treg_ext_5v: regulator-ext-5v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-always-on;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-name = \"VCCEXT_5V\";\n+\t\tgpio = <&pcal6524 12 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t};\n+\n+\treg_m2_ekey_pwr: regulator-m2-pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"M.2-power-ekey\";\n+\t\tgpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t};\n+\n+\treg_m2_mkey_pwr: regulator-m2-mkey-pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"M.2-mkey-power\";\n+\t\tgpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t};\n+\n+\treg_usdhc2_vmmc: regulator-usdhc2 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\toff-on-delay-us = <12000>;\n+\t\tpinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;\n+\t\tpinctrl-names = \"default\";\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"VDD_SD2_3V3\";\n+\t\tgpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t};\n+\n+\treg_usdhc3_vmmc: regulator-usdhc3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"WLAN_EN\";\n+\t\tvin-supply = <®_m2_ekey_pwr>;\n+\t\tgpio = <&pcal6524 9 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\t/*\n+\t\t * IW612 wifi chip needs more delay than other wifi chips to complete\n+\t\t * the host interface initialization after power up, otherwise the\n+\t\t * internal state of IW612 may be unstable, resulting in the failure of\n+\t\t * the SDIO3.0 switch voltage.\n+\t\t */\n+\t\tstartup-delay-us = <20000>;\n+\t};\n+\n+\treg_usb_vbus: regulator-vbus {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-name = \"USB_VBUS\";\n+\t\tgpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t};\n+\n+\treg_vref_1v8: regulator-adc-vref {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-name = \"vref_1v8\";\n+\t};\n+\n+\treserved-memory {\n+\t\tranges;\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\n+\t\tlinux_cma: linux,cma {\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\talloc-ranges = <0 0x80000000 0 0x7F000000>;\n+\t\t\treusable;\n+\t\t\tsize = <0 0x3c000000>;\n+\t\t\tlinux,cma-default;\n+\t\t};\n+\n+\t\tvdev0vring0: memory@88000000 {\n+\t\t\treg = <0 0x88000000 0 0x8000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdev0vring1: memory@88008000 {\n+\t\t\treg = <0 0x88008000 0 0x8000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdev1vring0: memory@88010000 {\n+\t\t\treg = <0 0x88010000 0 0x8000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdev1vring1: memory@88018000 {\n+\t\t\treg = <0 0x88018000 0 0x8000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvdevbuffer: memory@88020000 {\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treg = <0 0x88020000 0 0x100000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\trsc_table: memory@88220000 {\n+\t\t\treg = <0 0x88220000 0 0x1000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tvpu_boot: memory@a0000000 {\n+\t\t\treg = <0 0xa0000000 0 0x100000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+\n+\tsound-micfil {\n+\t\tcompatible = \"fsl,imx-audio-card\";\n+\t\tmodel = \"micfil-audio\";\n+\n+\t\tpri-dai-link {\n+\t\t\tlink-name = \"micfil hifi\";\n+\t\t\tformat = \"i2s\";\n+\n+\t\t\tcpu {\n+\t\t\t\tsound-dai = <&micfil>;\n+\t\t\t};\n+\n+\t\t\tcodec {\n+\t\t\t\tsound-dai = <&dmic>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tusdhc3_pwrseq: usdhc3-pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>;\n+\t};\n+\n+\tmemory@80000000 {\n+\t\treg = <0x0 0x80000000 0 0x80000000>;\n+\t\tdevice_type = \"memory\";\n+\t};\n+};\n+\n+&adc1 {\n+\tvref-supply = <®_vref_1v8>;\n+\tstatus = \"okay\";\n+};\n+\n+&enetc_port0 {\n+\tphy-handle = <ðphy0>;\n+\tphy-mode = \"rgmii-id\";\n+\tpinctrl-0 = <&pinctrl_enetc0>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\n+\n+&enetc_port1 {\n+\tphy-handle = <ðphy1>;\n+\tphy-mode = \"rgmii-id\";\n+\tpinctrl-0 = <&pinctrl_enetc1>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\n+\n+&flexcan2 {\n+\tpinctrl-0 = <&pinctrl_flexcan2>;\n+\tpinctrl-names = \"default\";\n+\tphys = <&flexcan2_phy>;\n+\tstatus = \"okay\";\n+};\n+\n+&flexcan5 {\n+\tpinctrl-0 = <&pinctrl_flexcan5>;\n+\tpinctrl-names = \"default\";\n+\tphys = <&flexcan5_phy>;\n+\tstatus = \"okay\";\n+};\n+\n+&lpi2c2 {\n+\tclock-frequency = <400000>;\n+\tpinctrl-0 = <&pinctrl_lpi2c2>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+\n+\tpcal6524: gpio@22 {\n+\t\tcompatible = \"nxp,pcal6524\";\n+\t\treg = <0x22>;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\tinterrupt-parent = <&gpio5>;\n+\t\tinterrupts = <14 IRQ_TYPE_LEVEL_LOW>;\n+\t\t#gpio-cells = <2>;\n+\t\tgpio-controller;\n+\t\tpinctrl-0 = <&pinctrl_pcal6524>;\n+\t\tpinctrl-names = \"default\";\n+\t\tgpio-line-names = \"ENET1 PHY reset\",\n+\t\t\t\t \"ENET2 PHY reset\",\n+\t\t\t\t \"SPI3/GPIO select\",\n+\t\t\t\t \"UART3/GPIO select\",\n+\t\t\t\t \"CAN2&5/GPIO select\",\n+\t\t\t\t \"PWM/GPIO select\",\n+\t\t\t\t \"Watch dog enable\",\n+\t\t\t\t \"CAN1&2&5 silent\",\n+\t\t\t\t \"SDIO_nRST\",\n+\t\t\t\t \"WL_nDISABLE1\",\n+\t\t\t\t \"WL_nDISABLE2\",\n+\t\t\t\t \"M.2 Mkey NC06\",\n+\t\t\t\t \"EXT_5V0_PWR_EN\",\n+\t\t\t\t \"EXT_3V3_PWR_EN\",\n+\t\t\t\t \"Mkey power control\",\n+\t\t\t\t \"USB2 power control\",\n+\t\t\t\t \"Ekey power control\",\n+\t\t\t\t \"MIPI-DSICSI reset\",\n+\t\t\t\t \"MIPI-DSI IO2\",\n+\t\t\t\t \"MIPI-CSI reset\",\n+\t\t\t\t \"LVDS TP reset\",\n+\t\t\t\t \"LVDS BL enable\",\n+\t\t\t\t \"LVDS BL power enable\",\n+\t\t\t\t \"IT6263 reset\";\n+\n+\t\tlpspi-gpio-sel-hog {\n+\t\t\tgpio-hog;\n+\t\t\tgpios = <2 GPIO_ACTIVE_HIGH>;\n+\t\t\toutput-low;\n+\t\t};\n+\n+\t\tlpuart-gpio-sel-hog {\n+\t\t\tgpio-hog;\n+\t\t\tgpios = <3 GPIO_ACTIVE_HIGH>;\n+\t\t\toutput-low;\n+\t\t};\n+\n+\t\tcan-gpio-sel-hog {\n+\t\t\tgpio-hog;\n+\t\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n+\t\t\toutput-low;\n+\t\t};\n+\n+\t\tpwm-gpio-sel-hog {\n+\t\t\tgpio-hog;\n+\t\t\tgpios = <5 GPIO_ACTIVE_HIGH>;\n+\t\t\toutput-high;\n+\t\t};\n+\t};\n+};\n+\n+&lpi2c3 {\n+\tclock-frequency = <400000>;\n+\tpinctrl-0 = <&pinctrl_lpi2c3>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+\n+\tptn5110: tcpc@50 {\n+\t\tcompatible = \"nxp,ptn5110\", \"tcpci\";\n+\t\treg = <0x50>;\n+\t\tinterrupt-parent = <&gpio5>;\n+\t\tinterrupts = <3 IRQ_TYPE_LEVEL_LOW>;\n+\t\tpinctrl-0 = <&pinctrl_ptn5110>;\n+\t\tpinctrl-names = \"default\";\n+\n+\t\ttypec_con: connector {\n+\t\t\tcompatible = \"usb-c-connector\";\n+\t\t\tdata-role = \"dual\";\n+\t\t\tlabel = \"USB-C\";\n+\t\t\top-sink-microwatt = <15000000>;\n+\t\t\tpower-role = \"dual\";\n+\t\t\tself-powered;\n+\t\t\tsink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)\n+\t\t\t\t PDO_VAR(5000, 20000, 3000)>;\n+\t\t\tsource-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;\n+\t\t\ttry-power-role = \"sink\";\n+\n+\t\t\tports {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tport@0 {\n+\t\t\t\t\treg = <0>;\n+\n+\t\t\t\t\ttypec_con_hs: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&usb3_data_hs>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tport@1 {\n+\t\t\t\t\treg = <1>;\n+\n+\t\t\t\t\ttypec_con_ss: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&usb3_data_ss>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&lpi2c4 {\n+\tclock-frequency = <400000>;\n+\tpinctrl-0 = <&pinctrl_lpi2c4>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+\n+\tpca9632: led-controller@62 {\n+\t\tcompatible = \"nxp,pca9632\";\n+\t\treg = <0x62>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tnxp,inverted-out;\n+\n+\t\tled_backlight0: led@0 {\n+\t\t\treg = <0>;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tfunction = LED_FUNCTION_BACKLIGHT;\n+\t\t\tfunction-enumerator = <0>;\n+\t\t};\n+\n+\t\tled_backlight1: led@1 {\n+\t\t\treg = <1>;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tfunction = LED_FUNCTION_BACKLIGHT;\n+\t\t\tfunction-enumerator = <1>;\n+\t\t};\n+\t};\n+};\n+\n+&lpuart1 {\n+\tpinctrl-0 = <&pinctrl_uart1>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\n+\n+&lpuart5 {\n+\tpinctrl-0 = <&pinctrl_uart5>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+\n+\tbluetooth {\n+\t\tcompatible = \"nxp,88w8987-bt\";\n+\t};\n+};\n+\n+&micfil {\n+\tassigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,\n+\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,\n+\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL1>,\n+\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL2>,\n+\t\t\t <&scmi_clk IMX95_CLK_PDM>;\n+\tassigned-clock-parents = <0>, <0>, <0>, <0>,\n+\t\t\t\t <&scmi_clk IMX95_CLK_AUDIOPLL1>;\n+\tassigned-clock-rates = <3932160000>,\n+\t\t\t <3612672000>, <393216000>,\n+\t\t\t <361267200>, <49152000>;\n+\t#sound-dai-cells = <0>;\n+\tpinctrl-0 = <&pinctrl_pdm>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\n+\n+&mu7 {\n+\tstatus = \"okay\";\n+};\n+\n+&netc_blk_ctrl {\n+\tstatus = \"okay\";\n+};\n+\n+/* Configure MSI and IOMMU mappings specific to the i.MX95 15x15 FRDM board. */\n+&netc_bus0 {\n+\tmsi-map = <0x0 &its 0x60 0x1>,\t//ENETC0 PF\n+\t\t <0x10 &its 0x61 0x1>, //ENETC0 VF0\n+\t\t <0x20 &its 0x62 0x1>, //ENETC0 VF1\n+\t\t <0x40 &its 0x63 0x1>, //ENETC1 PF\n+\t\t <0x50 &its 0x65 0x1>, //ENETC1 VF0\n+\t\t <0x60 &its 0x66 0x1>, //ENETC1 VF1\n+\t\t <0x80 &its 0x64 0x1>, //ENETC2 PF\n+\t\t <0xc0 &its 0x67 0x1>; //NETC Timer\n+\tiommu-map = <0x0 &smmu 0x20 0x1>,\n+\t\t <0x10 &smmu 0x21 0x1>,\n+\t\t <0x20 &smmu 0x22 0x1>,\n+\t\t <0x40 &smmu 0x23 0x1>,\n+\t\t <0x50 &smmu 0x25 0x1>,\n+\t\t <0x60 &smmu 0x26 0x1>,\n+\t\t <0x80 &smmu 0x24 0x1>,\n+\t\t <0xc0 &smmu 0x27 0x1>;\n+};\n+\n+&netc_emdio {\n+\tpinctrl-0 = <&pinctrl_emdio>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+\n+\tethphy0: ethernet-phy@1 {\n+\t\treg = <1>;\n+\t\treset-assert-us = <10000>;\n+\t\treset-deassert-us = <80000>;\n+\t\treset-gpios = <&pcal6524 0 GPIO_ACTIVE_LOW>;\n+\t};\n+\n+\tethphy1: ethernet-phy@2 {\n+\t\treg = <2>;\n+\t\treset-assert-us = <10000>;\n+\t\treset-deassert-us = <80000>;\n+\t\treset-gpios = <&pcal6524 1 GPIO_ACTIVE_LOW>;\n+\t};\n+};\n+\n+&netc_timer {\n+\tstatus = \"okay\";\n+};\n+\n+&netcmix_blk_ctrl {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie0 {\n+\tpinctrl-0 = <&pinctrl_pcie0>;\n+\tpinctrl-names = \"default\";\n+\treset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;\n+\tsupports-clkreq;\n+\tvpcie-supply = <®_m2_mkey_pwr>;\n+\tstatus = \"okay\";\n+};\n+\n+&scmi_iomuxc {\n+\tpinctrl_emdio: emdiogrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC\t\t0x50e\n+\t\t\tIMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO\t\t0x90e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_enetc0: enetc0grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3\t\t0x50e\n+\t\t\tIMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2\t\t0x50e\n+\t\t\tIMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1\t\t0x50e\n+\t\t\tIMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0\t\t0x50e\n+\t\t\tIMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL\t0x57e\n+\t\t\tIMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK\t0x58e\n+\t\t\tIMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL\t0x57e\n+\t\t\tIMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK\t0x58e\n+\t\t\tIMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0\t\t0x57e\n+\t\t\tIMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1\t\t0x57e\n+\t\t\tIMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2\t\t0x57e\n+\t\t\tIMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3\t\t0x57e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_enetc1: enetc1grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3\t\t0x50e\n+\t\t\tIMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2\t\t0x50e\n+\t\t\tIMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1\t\t0x50e\n+\t\t\tIMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0\t\t0x50e\n+\t\t\tIMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL\t0x57e\n+\t\t\tIMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK\t0x58e\n+\t\t\tIMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL\t0x57e\n+\t\t\tIMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK\t0x58e\n+\t\t\tIMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0\t\t0x57e\n+\t\t\tIMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1\t\t0x57e\n+\t\t\tIMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2\t\t0x57e\n+\t\t\tIMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3\t\t0x57e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_flexcan2: flexcan2grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_GPIO_IO25__CAN2_TX\t\t\t\t0x39e\n+\t\t\tIMX95_PAD_GPIO_IO27__CAN2_RX\t\t\t\t0x39e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_flexcan5: flexcan5grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_GPIO_IO22__CAN5_TX\t\t\t\t0x39e\n+\t\t\tIMX95_PAD_GPIO_IO23__CAN5_RX\t\t\t\t0x39e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_lpi2c1: lpi2c1grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL\t\t0x40000b9e\n+\t\t\tIMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA\t\t0x40000b9e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_lpi2c2: lpi2c2grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL\t\t0x40000b9e\n+\t\t\tIMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA\t\t0x40000b9e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_lpi2c3: lpi2c3grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_GPIO_IO28__LPI2C3_SDA\t\t\t\t0x40000b9e\n+\t\t\tIMX95_PAD_GPIO_IO29__LPI2C3_SCL\t\t\t\t0x40000b9e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_lpi2c4: lpi2c4grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_GPIO_IO30__LPI2C4_SDA\t\t\t\t0x40000b9e\n+\t\t\tIMX95_PAD_GPIO_IO31__LPI2C4_SCL\t\t\t\t0x40000b9e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_pcal6524: pcal6524grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14\t\t\t0x31e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_pcie0: pcie0grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B\t\t0x40000b1e\n+\t\t\tIMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13\t\t\t0x31e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_pdm: pdmgrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK\t\t\t\t0x31e\n+\t\t\tIMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0\t0x31e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_ptn5110: ptn5110grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3\t\t\t0x31e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7\t\t\t0x31e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX\t\t0x31e\n+\t\t\tIMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX\t\t0x31e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart5: uart5grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX\t\t\t0x31e\n+\t\t\tIMX95_PAD_DAP_TDI__LPUART5_RX\t\t\t\t0x31e\n+\t\t\tIMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B\t\t\t0x31e\n+\t\t\tIMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B\t\t\t0x31e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc1: usdhc1grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD1_CLK__USDHC1_CLK\t\t\t\t0x158e\n+\t\t\tIMX95_PAD_SD1_CMD__USDHC1_CMD\t\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA0__USDHC1_DATA0\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA1__USDHC1_DATA1\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA2__USDHC1_DATA2\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA3__USDHC1_DATA3\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA4__USDHC1_DATA4\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA5__USDHC1_DATA5\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA6__USDHC1_DATA6\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA7__USDHC1_DATA7\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_STROBE__USDHC1_STROBE\t\t\t0x158e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD1_CLK__USDHC1_CLK\t\t\t\t0x158e\n+\t\t\tIMX95_PAD_SD1_CMD__USDHC1_CMD\t\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA0__USDHC1_DATA0\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA1__USDHC1_DATA1\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA2__USDHC1_DATA2\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA3__USDHC1_DATA3\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA4__USDHC1_DATA4\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA5__USDHC1_DATA5\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA6__USDHC1_DATA6\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_DATA7__USDHC1_DATA7\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD1_STROBE__USDHC1_STROBE\t\t\t0x158e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD1_CLK__USDHC1_CLK\t\t\t\t0x15fe\n+\t\t\tIMX95_PAD_SD1_CMD__USDHC1_CMD\t\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_DATA0__USDHC1_DATA0\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_DATA1__USDHC1_DATA1\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_DATA2__USDHC1_DATA2\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_DATA3__USDHC1_DATA3\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_DATA4__USDHC1_DATA4\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_DATA5__USDHC1_DATA5\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_DATA6__USDHC1_DATA6\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_DATA7__USDHC1_DATA7\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD1_STROBE__USDHC1_STROBE\t\t\t0x15fe\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc2_gpio: usdhc2gpiogrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0\t\t\t0x31e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc2: usdhc2grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD2_CLK__USDHC2_CLK\t\t\t\t0x158e\n+\t\t\tIMX95_PAD_SD2_CMD__USDHC2_CMD\t\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA0__USDHC2_DATA0\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA1__USDHC2_DATA1\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA2__USDHC2_DATA2\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA3__USDHC2_DATA3\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_VSELECT__USDHC2_VSELECT\t\t\t0x51e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD2_CLK__USDHC2_CLK\t\t\t\t0x158e\n+\t\t\tIMX95_PAD_SD2_CMD__USDHC2_CMD\t\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA0__USDHC2_DATA0\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA1__USDHC2_DATA1\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA2__USDHC2_DATA2\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA3__USDHC2_DATA3\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_VSELECT__USDHC2_VSELECT\t\t\t0x51e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD2_CLK__USDHC2_CLK\t\t\t\t0x158e\n+\t\t\tIMX95_PAD_SD2_CMD__USDHC2_CMD\t\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA0__USDHC2_DATA0\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA1__USDHC2_DATA1\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA2__USDHC2_DATA2\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_DATA3__USDHC2_DATA3\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD2_VSELECT__USDHC2_VSELECT\t\t\t0x51e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc3: usdhc3grp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD3_CLK__USDHC3_CLK\t\t\t\t0x158e\n+\t\t\tIMX95_PAD_SD3_CMD__USDHC3_CMD\t\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD3_DATA0__USDHC3_DATA0\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD3_DATA1__USDHC3_DATA1\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD3_DATA2__USDHC3_DATA2\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD3_DATA3__USDHC3_DATA3\t\t\t0x138e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD3_CLK__USDHC3_CLK\t\t\t\t0x158e\n+\t\t\tIMX95_PAD_SD3_CMD__USDHC3_CMD\t\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD3_DATA0__USDHC3_DATA0\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD3_DATA1__USDHC3_DATA1\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD3_DATA2__USDHC3_DATA2\t\t\t0x138e\n+\t\t\tIMX95_PAD_SD3_DATA3__USDHC3_DATA3\t\t\t0x138e\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {\n+\t\tfsl,pins = <\n+\t\t\tIMX95_PAD_SD3_CLK__USDHC3_CLK\t\t\t\t0x15fe\n+\t\t\tIMX95_PAD_SD3_CMD__USDHC3_CMD\t\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD3_DATA0__USDHC3_DATA0\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD3_DATA1__USDHC3_DATA1\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD3_DATA2__USDHC3_DATA2\t\t\t0x13fe\n+\t\t\tIMX95_PAD_SD3_DATA3__USDHC3_DATA3\t\t\t0x13fe\n+\t\t>;\n+\t};\n+};\n+\n+&scmi_misc {\n+\tnxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE\t\t1\n+\t\t\tBRD_SM_CTRL_PCIE1_WAKE\t\t1\n+\t\t\tBRD_SM_CTRL_BT_WAKE\t\t1\n+\t\t\tBRD_SM_CTRL_PCIE2_WAKE\t\t1\n+\t\t\tBRD_SM_CTRL_BUTTON\t\t1>;\n+};\n+\n+&thermal_zones {\n+\tpf09-thermal {\n+\t\tpolling-delay = <2000>;\n+\t\tpolling-delay-passive = <250>;\n+\t\tthermal-sensors = <&scmi_sensor 2>;\n+\n+\t\ttrips {\n+\t\t\tpf09_alert: trip0 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <140000>;\n+\t\t\t\ttype = \"passive\";\n+\t\t\t};\n+\n+\t\t\tpf09_crit: trip1 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <155000>;\n+\t\t\t\ttype = \"critical\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tpf53arm-thermal {\n+\t\tpolling-delay = <2000>;\n+\t\tpolling-delay-passive = <250>;\n+\t\tthermal-sensors = <&scmi_sensor 4>;\n+\n+\t\tcooling-maps {\n+\t\t\tmap0 {\n+\t\t\t\tcooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t<&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t<&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t<&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t<&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\ttrip = <&pf5301_alert>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ttrips {\n+\t\t\tpf5301_alert: trip0 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <140000>;\n+\t\t\t\ttype = \"passive\";\n+\t\t\t};\n+\n+\t\t\tpf5301_crit: trip1 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <155000>;\n+\t\t\t\ttype = \"critical\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tpf53soc-thermal {\n+\t\tpolling-delay = <2000>;\n+\t\tpolling-delay-passive = <250>;\n+\t\tthermal-sensors = <&scmi_sensor 3>;\n+\n+\t\ttrips {\n+\t\t\tpf5302_alert: trip0 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <140000>;\n+\t\t\t\ttype = \"passive\";\n+\t\t\t};\n+\n+\t\t\tpf5302_crit: trip1 {\n+\t\t\t\thysteresis = <2000>;\n+\t\t\t\ttemperature = <155000>;\n+\t\t\t\ttype = \"critical\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&usb2 {\n+\tdisable-over-current;\n+\tdr_mode = \"host\";\n+\tvbus-supply = <®_usb_vbus>;\n+\tstatus = \"okay\";\n+};\n+\n+&usb3 {\n+\tstatus = \"okay\";\n+};\n+\n+&usb3_dwc3 {\n+\tadp-disable;\n+\tdr_mode = \"otg\";\n+\thnp-disable;\n+\trole-switch-default-mode = \"peripheral\";\n+\tsrp-disable;\n+\tusb-role-switch;\n+\tsnps,dis-u1-entry-quirk;\n+\tsnps,dis-u2-entry-quirk;\n+\tstatus = \"okay\";\n+\n+\tport {\n+\t\tusb3_data_hs: endpoint {\n+\t\t\tremote-endpoint = <&typec_con_hs>;\n+\t\t};\n+\t};\n+};\n+\n+&usb3_phy {\n+\torientation-switch;\n+\tfsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>;\n+\tfsl,phy-pcs-tx-swing-full-percent = <100>;\n+\tfsl,phy-tx-preemp-amp-tune-microamp = <600>;\n+\tfsl,phy-tx-vboost-level-microvolt = <1156>;\n+\tfsl,phy-tx-vref-tune-percent = <100>;\n+\tstatus = \"okay\";\n+\n+\tport {\n+\t\tusb3_data_ss: endpoint {\n+\t\t\tremote-endpoint = <&typec_con_ss>;\n+\t\t};\n+\t};\n+};\n+\n+&usdhc1 {\n+\tbus-width = <8>;\n+\tnon-removable;\n+\tno-sd;\n+\tno-sdio;\n+\tpinctrl-0 = <&pinctrl_usdhc1>;\n+\tpinctrl-1 = <&pinctrl_usdhc1_100mhz>;\n+\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n+\tpinctrl-3 = <&pinctrl_usdhc1>;\n+\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\", \"sleep\";\n+\tfsl,tuning-step = <1>;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc2 {\n+\tbus-width = <4>;\n+\tcd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;\n+\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n+\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;\n+\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;\n+\tpinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n+\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\", \"sleep\";\n+\tvmmc-supply = <®_usdhc2_vmmc>;\n+\tfsl,tuning-step = <1>;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc3 {\n+\tbus-width = <4>;\n+\tkeep-power-in-suspend;\n+\tmmc-pwrseq = <&usdhc3_pwrseq>;\n+\tnon-removable;\n+\tpinctrl-0 = <&pinctrl_usdhc3>;\n+\tpinctrl-1 = <&pinctrl_usdhc3_100mhz>;\n+\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n+\tpinctrl-3 = <&pinctrl_usdhc3>;\n+\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\", \"sleep\";\n+\tvmmc-supply = <®_usdhc3_vmmc>;\n+\twakeup-source;\n+\tstatus = \"okay\";\n+};\n+\n+&wdog3 {\n+\tstatus = \"okay\";\n+};\n", "prefixes": [ "v2", "1/2" ] }