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GET /api/patches/2195816/?format=api
{ "id": 2195816, "url": "http://patchwork.ozlabs.org/api/patches/2195816/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260212033435.3598-9-ltaylorsimpson@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212033435.3598-9-ltaylorsimpson@gmail.com>", "list_archive_url": null, "date": "2026-02-12T03:34:35", "name": "[8/8] tests/tcg/hexagon: Add test for revision-gated instruction decoding", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f906c5e91e3ca8ed805d794735d0788f71491533", "submitter": { "id": 86757, "url": "http://patchwork.ozlabs.org/api/people/86757/?format=api", "name": "Taylor Simpson", "email": "ltaylorsimpson@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260212033435.3598-9-ltaylorsimpson@gmail.com/mbox/", "series": [ { "id": 491930, "url": "http://patchwork.ozlabs.org/api/series/491930/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491930", "date": "2026-02-12T03:34:34", "name": "Hexagon (target/hexagon) Check opcodes versions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491930/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195816/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195816/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=bzW0Dghs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fBLYC2p98z1xpY\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 12 Feb 2026 14:35:43 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vqNTg-0007mN-47; Wed, 11 Feb 2026 22:34:52 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <ltaylorsimpson@gmail.com>)\n id 1vqNTe-0007m5-RS\n for qemu-devel@nongnu.org; Wed, 11 Feb 2026 22:34:50 -0500", "from mail-ot1-x332.google.com ([2607:f8b0:4864:20::332])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <ltaylorsimpson@gmail.com>)\n id 1vqNTd-0008IN-1s\n for qemu-devel@nongnu.org; Wed, 11 Feb 2026 22:34:50 -0500", "by mail-ot1-x332.google.com with SMTP id\n 46e09a7af769-7d18d9503eeso2291312a34.1\n for <qemu-devel@nongnu.org>; Wed, 11 Feb 2026 19:34:48 -0800 (PST)", "from taylor-ubuntu.. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::332;\n envelope-from=ltaylorsimpson@gmail.com; helo=mail-ot1-x332.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <brian.cain@oss.qualcomm.com>\n\nAdd check_rev_gating, a linux-user test that verifies the decoder\nrejects instructions from a newer CPU revision than the one selected\nby the ELF binary's e_flags.\n\nCo-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nCo-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n tests/tcg/hexagon/check_rev_gating.c | 141 +++++++++++++++++++++++++++\n tests/tcg/hexagon/Makefile.target | 6 ++\n 2 files changed, 147 insertions(+)\n create mode 100644 tests/tcg/hexagon/check_rev_gating.c", "diff": "diff --git a/tests/tcg/hexagon/check_rev_gating.c b/tests/tcg/hexagon/check_rev_gating.c\nnew file mode 100644\nindex 0000000000..26b66f5455\n--- /dev/null\n+++ b/tests/tcg/hexagon/check_rev_gating.c\n@@ -0,0 +1,141 @@\n+/*\n+ * Test that instructions from a newer revision than the running CPU\n+ * are rejected with SIGILL.\n+ *\n+ * Compiled with -mv66 so that e_flags selects CPU v66. The test embeds\n+ * a v68 instruction (L2_loadw_aq: \"r0 = memw_aq(r0)\") via .word\n+ * encoding. The revision-gated decoder must reject it, and linux-user\n+ * must deliver SIGILL.\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include <assert.h>\n+#include <signal.h>\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include <unistd.h>\n+\n+static void *resume_pc;\n+static int signals_handled;\n+static int expected_signals;\n+\n+static void handle_sigill(int sig, siginfo_t *info, void *puc)\n+{\n+ ucontext_t *uc = (ucontext_t *)puc;\n+\n+ if (sig != SIGILL) {\n+ _exit(EXIT_FAILURE);\n+ }\n+\n+ uc->uc_mcontext.r0 = SIGILL;\n+ uc->uc_mcontext.pc = (unsigned long)resume_pc;\n+ signals_handled++;\n+}\n+\n+/*\n+ * Try to execute an instruction introduced after v66\n+ * On a v66 CPU this must raise SIGILL.\n+ *\n+ * Since we are building for v66, the assembler will reject\n+ * the instructions, so introduce them with .word.\n+ */\n+#define TRY_FUNC(NAME, WORD) \\\n+static int try_##NAME(void) \\\n+{ \\\n+ int sig; \\\n+ expected_signals++; \\\n+ asm volatile( \\\n+ \"r0 = #0\\n\" \\\n+ \"r1 = ##1f\\n\" \\\n+ \"memw(%1) = r1\\n\" \\\n+ WORD \\\n+ \"1:\\n\" \\\n+ \"%0 = r0\\n\" \\\n+ : \"=r\"(sig) \\\n+ : \"r\"(&resume_pc) \\\n+ : \"r0\", \"r1\", \"memory\"); \\\n+ return sig; \\\n+}\n+\n+TRY_FUNC(v68_loadw_aq,\n+ \".word 0x9200c800 /* { r0 = memw_aq(r0) } */\\n\")\n+TRY_FUNC(v68_loadd_aq,\n+ \".word 0x9201d800 /* r1:0 = memd_aq(r1) */\\n\")\n+TRY_FUNC(v68_release_at,\n+ \".word 0xa0e0c00c /* release(r0):at */\\n\")\n+TRY_FUNC(v68_release_st,\n+ \".word 0xa0e0c02c /* release(r0):st */\\n\")\n+TRY_FUNC(v68_storew_rl_at,\n+ \".word 0xa0a0c108 /* memw_rl(r0):at = r1 */\\n\")\n+TRY_FUNC(v68_stored_rl_at,\n+ \".word 0xa0e2c008 /* memd_rl(r2):at = r1:0 */\\n\")\n+TRY_FUNC(v68_storew_rl_st,\n+ \".word 0xa0a0c128 /* memw_rl(r0):st = r1 */\\n\")\n+TRY_FUNC(v68_stored_rl_st,\n+ \".word 0xa0e2c028 /* memd_rl(r2):st = r1:0 */\\n\")\n+\n+TRY_FUNC(v68hvx_v6mpy,\n+ \".word 0x1f42e424 /* v5:4.w = v6mpy(v5:4.ub, v3:2.b, #1):v */\\n\")\n+\n+TRY_FUNC(v69hvx_vasrvuhubrndsat,\n+ \".word 0x1d06c465 /* v5.ub = vasr(v5:4.uh, v6.ub):rnd:sat */\\n\")\n+TRY_FUNC(v69hvx_vasrvuhubsat,\n+ \".word 0x1d06c445 /* v5.ub = vasr(v5:4.uh, v6.ub):sat */\\n\")\n+TRY_FUNC(v69hvx_vasrvwuhrndsat,\n+ \".word 0x1d06c425 /* v5.uh = vasr(v5:4.w, v6.uh):rnd:sat */\\n\")\n+TRY_FUNC(v69hvx_vasrvwuhsat,\n+ \".word 0x1d06c405 /* v5.uh = vasr(v5:4.w, v6.uh):sat */\\n\")\n+TRY_FUNC(v69hvx_vassign_tmp,\n+ \".word 0x1e014dcc /* { v12.tmp = v13 */\\n\"\n+ \".word 0x1c43cc04 /* v4.w = vadd(v12.w, v3.w) } */\\n\")\n+TRY_FUNC(v69hvx_vcombine_tmp,\n+ \".word 0x1eae4fec /* { v13:12.tmp = vcombine(v15, v14) */\\n\"\n+ \".word 0x1c434c04 /* v4.w = vadd(v12.w, v3.w) */\\n\"\n+ \".word 0x1e03edf0 /* v16 = v13 } */\\n\")\n+TRY_FUNC(v69hvx_vmpyuhvs,\n+ \".word 0x1fc5e4e4 /* v4.uh = vmpy(V4.uh, v5.uh):>>16 */\\n\")\n+\n+TRY_FUNC(v73_callrh,\n+ \".word 0x50c5c000 /* callrh r5 */\\n\")\n+TRY_FUNC(v73_jumprh,\n+ \".word 0x52c0c000 /* jumprh r0 */\\n\")\n+\n+int main(void)\n+{\n+ struct sigaction act;\n+\n+ memset(&act, 0, sizeof(act));\n+ act.sa_sigaction = handle_sigill;\n+ act.sa_flags = SA_SIGINFO;\n+ assert(sigaction(SIGILL, &act, NULL) == 0);\n+\n+ assert(try_v68_loadw_aq() == SIGILL);\n+ assert(try_v68_loadd_aq() == SIGILL);\n+ assert(try_v68_release_at() == SIGILL);\n+ assert(try_v68_release_st() == SIGILL);\n+ assert(try_v68_storew_rl_at() == SIGILL);\n+ assert(try_v68_stored_rl_at() == SIGILL);\n+ assert(try_v68_storew_rl_st() == SIGILL);\n+ assert(try_v68_stored_rl_st() == SIGILL);\n+\n+ assert(try_v68hvx_v6mpy() == SIGILL);\n+\n+ assert(try_v69hvx_vasrvuhubrndsat() == SIGILL);\n+ assert(try_v69hvx_vasrvuhubsat() == SIGILL);\n+ assert(try_v69hvx_vasrvwuhrndsat() == SIGILL);\n+ assert(try_v69hvx_vasrvwuhsat() == SIGILL);\n+ assert(try_v69hvx_vassign_tmp() == SIGILL);\n+ assert(try_v69hvx_vcombine_tmp() == SIGILL);\n+ assert(try_v69hvx_vmpyuhvs() == SIGILL);\n+\n+ assert(try_v73_callrh() == SIGILL);\n+ assert(try_v73_jumprh() == SIGILL);\n+\n+ assert(signals_handled == expected_signals);\n+\n+ puts(\"PASS\");\n+ return EXIT_SUCCESS;\n+}\ndiff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target\nindex 8c9d48fc4d..c768ba1a4f 100644\n--- a/tests/tcg/hexagon/Makefile.target\n+++ b/tests/tcg/hexagon/Makefile.target\n@@ -79,6 +79,7 @@ HEX_TESTS += test_vminh\n HEX_TESTS += test_vpmpyh\n HEX_TESTS += test_vspliceb\n \n+HEX_TESTS += check_rev_gating\n HEX_TESTS += v68_scalar\n HEX_TESTS += v68_hvx\n HEX_TESTS += v69_hvx\n@@ -104,6 +105,11 @@ read_write_overlap: read_write_overlap.c hex_test.h\n reg_mut: reg_mut.c hex_test.h\n unaligned_pc: unaligned_pc.c\n \n+# Compile for v66 so that the ELF selects a v66 CPU; the test then\n+# exercises revision gating by executing a v68 .word instruction.\n+check_rev_gating: check_rev_gating.c\n+\t$(CC) $(CFLAGS) -mv66 -O2 $< -o $@ $(LDFLAGS)\n+\n # This test has to be compiled for the -mv67t target\n usr: usr.c hex_test.h\n \t$(CC) $(CFLAGS) -mv67t -O2 -Wno-inline-asm -Wno-expansion-to-defined $< -o $@ $(LDFLAGS)\n", "prefixes": [ "8/8" ] }