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GET /api/patches/2195790/?format=api
{ "id": 2195790, "url": "http://patchwork.ozlabs.org/api/patches/2195790/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260211222025.2463312-3-raymondmaoca@gmail.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260211222025.2463312-3-raymondmaoca@gmail.com>", "list_archive_url": null, "date": "2026-02-11T22:20:24", "name": "[2/3] lib: utils: irqchip: implement APLIC hwirq operation hooks", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c65e4c20aea1a77db23952323a073467253cc8fc", "submitter": { "id": 91989, "url": "http://patchwork.ozlabs.org/api/people/91989/?format=api", "name": "Raymond Mao", "email": "raymondmaoca@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260211222025.2463312-3-raymondmaoca@gmail.com/mbox/", "series": [ { "id": 491914, "url": "http://patchwork.ozlabs.org/api/series/491914/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=491914", "date": "2026-02-11T22:20:24", "name": "APLIC hwirq implementation for irqchip", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491914/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195790/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195790/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=1A9P4Ibh;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=dWFX2raj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Raymond Mao Add all APLIC reqiured operation hooks,\n includeing mask / unmask / eoi / setup / process and register them during\n cold init. During setup, program a minimal APLIC direct-mode configuration\n and enable [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:832 listed in]\n [list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n provider\n [raymondmaoca(at)gmail.com]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "From: Raymond Mao <raymond.mao@riscstar.com>\n\nAdd all APLIC reqiured operation hooks, includeing mask / unmask /\neoi / setup / process and register them during cold init.\nDuring setup, program a minimal APLIC direct-mode configuration and\nenable MEIE, confirm external interrupts are claimed via IDC.CLAIMI.\nAdd function to fetch the TOPI value and extract the source ID (hwirq)\nfrom CLAIMI, which is used by APLIC process hook.\n\nSigned-off-by: Raymond Mao <raymond.mao@riscstar.com>\n---\n lib/utils/irqchip/aplic.c | 191 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 191 insertions(+)", "diff": "diff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c\nindex ec69c82b..f0ecef42 100644\n--- a/lib/utils/irqchip/aplic.c\n+++ b/lib/utils/irqchip/aplic.c\n@@ -245,6 +245,178 @@ static int aplic_check_msicfg(struct aplic_msicfg_data *msicfg)\n \treturn 0;\n }\n \n+static int aplic_hwirq_handler(u32 hwirq, void *opaque)\n+{\n+\t(void)opaque;\n+\n+\tsbi_printf(\"[APLIC] Enter registered hwirq %u raw handler callback\\n\",\n+\t\t hwirq);\n+\n+\treturn SBI_OK;\n+}\n+\n+static inline void *aplic_idc_base(unsigned long aplic_addr, u32 idc_index)\n+{\n+\treturn (void *)(aplic_addr + APLIC_IDC_BASE +\n+\t\t\t(unsigned long)idc_index * APLIC_IDC_SIZE);\n+}\n+\n+static void aplic_hwirq_mask(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tstruct aplic_data *w = chip->chip_priv;\n+\n+\tif (!w || !hwirq)\n+\t\treturn;\n+\n+\tif (!w->addr || hwirq > w->num_source)\n+\t\treturn;\n+\n+\t/* Disable source */\n+\twritel(hwirq, (void *)(w->addr + APLIC_CLRIENUM));\n+}\n+\n+static void aplic_hwirq_unmask(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tstruct aplic_data *w = chip->chip_priv;\n+\n+\tif (!w || !hwirq)\n+\t\treturn;\n+\n+\tif (!w->addr || hwirq > w->num_source)\n+\t\treturn;\n+\n+\t/* Enable source */\n+\twritel(hwirq, (void *)(w->addr + APLIC_SETIENUM));\n+}\n+\n+static int aplic_hwirq_claim(struct sbi_irqchip_device *chip, u32 *hwirq)\n+{\n+\tstruct aplic_data *w = chip->chip_priv;\n+\tu32 hartid = current_hartid();\n+\tint hidx = sbi_hartid_to_hartindex(hartid);\n+\tvoid *idc;\n+\tu32 v, id;\n+\n+\tif (!w || !hwirq)\n+\t\treturn SBI_EINVAL;\n+\n+\tif (!w->addr || hidx < 0 || (u32)hidx >= w->num_idc)\n+\t\treturn SBI_ENODEV;\n+\n+\tidc = aplic_idc_base(w->addr, (u32)hidx);\n+\n+\t/*\n+\t * Read CLAIMI: returns TOPI value.\n+\t * ID==0 means spurious interrupt (spec-defined).\n+\t */\n+\tv = readl(idc + APLIC_IDC_CLAIMI); /* dequeue */\n+\t/*\n+\t * QEMU workaround: Read CLAIMI a second time since QEMU's APLIC model\n+\t * currently has a bug and may not clear pending on deassert after the\n+\t * first reading.\n+\t */\n+\tif (readl(idc + APLIC_IDC_CLAIMI) != v)\n+\t\treturn SBI_ENOENT;\n+\n+\tid = (v >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK;\n+\n+\t/* ID==0 means spurious / no pending wired interrupt */\n+\tif (!id)\n+\t\treturn SBI_ENOENT;\n+\n+\t/* Bound check against DT-discovered num_src */\n+\tif (id > w->num_source)\n+\t\treturn SBI_EINVAL;\n+\n+\t*hwirq = id;\n+\n+\treturn SBI_OK;\n+}\n+\n+static void aplic_hwirq_eoi(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tstruct aplic_data *w = chip->chip_priv;\n+\tu32 hartid = current_hartid();\n+\tint hidx = sbi_hartid_to_hartindex(hartid);\n+\tvoid *idc;\n+\n+\tsbi_printf(\"[APLIC] Enter regitered EOI of hwirq %u\\n\", hwirq);\n+\n+\tif (!w || !w->addr)\n+\t\treturn;\n+\tif (hidx < 0 || (u32)hidx >= w->num_idc)\n+\t\treturn;\n+\n+\tidc = aplic_idc_base(w->addr, (u32)hidx);\n+\n+\t/* QEMU workaround: clear pending after source deassert for level IRQ */\n+\twritel(hwirq, idc + APLIC_CLRIPNUM);\n+}\n+\n+static int aplic_hwirq_setup(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tconst u32 hart_idx = 0;\n+\tunsigned long idc;\n+\tstruct aplic_data *w = chip->chip_priv;\n+\n+\tidc = w->addr + APLIC_IDC_BASE + hart_idx * APLIC_IDC_SIZE;\n+\n+\t/* APLIC: sourcecfg/target/enable */\n+\twritel(APLIC_SOURCECFG_SM_LEVEL_HIGH,\n+\t (void *)(w->addr + APLIC_SOURCECFG_BASE + (hwirq - 1) * 4));\n+\n+\twritel((hart_idx << APLIC_TARGET_HART_IDX_SHIFT) | APLIC_DEFAULT_PRIORITY,\n+\t (void *)(w->addr + APLIC_TARGET_BASE + (hwirq - 1) * 4));\n+\n+\twritel(hwirq, (void *)(w->addr + APLIC_SETIENUM));\n+\n+\t/* Direct mode for aia=aplic: DM=0 => don't set DM bit */\n+\twritel(APLIC_DOMAINCFG_IE | APLIC_DOMAINCFG_BE,\n+\t (void *)(w->addr + APLIC_DOMAINCFG));\n+\n+\t/* IDC delivery */\n+\twritel(APLIC_ENABLE_IDELIVERY, (void *)(idc + APLIC_IDC_IDELIVERY));\n+\twritel(APLIC_ENABLE_ITHRESHOLD, (void *)(idc + APLIC_IDC_ITHRESHOLD));\n+\n+\t/* Enable MEIE + global MIE */\n+\tcsr_set(CSR_MIE, (1UL << 11)); /* MEIE */\n+\tcsr_set(CSR_MSTATUS, MSTATUS_MIE);\n+\n+\treturn SBI_OK;\n+}\n+\n+static int aplic_process_hwirqs(struct sbi_irqchip_device *chip)\n+{\n+\tif (!chip)\n+\t\treturn SBI_ENODEV;\n+\n+\tfor (;;) {\n+\t\tu32 hwirq = 0;\n+\t\tint rc = aplic_hwirq_claim(chip, &hwirq);\n+\n+\t\tif (rc == SBI_ENOENT)\n+\t\t\tbreak;\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tif (!hwirq)\n+\t\t\tbreak;\n+\n+\t\tsbi_printf(\"[APLIC] IDC_TOPI_ID from CLAIMI (hwirq) %u\\n\",\n+\t\t\t hwirq);\n+\n+\t\tif (hwirq > chip->num_hwirq) {\n+\t\t\tsbi_printf(\"[APLIC] hwirq %u > max (num_hwirq) %u)\\n\",\n+\t\t\t\t hwirq, chip->num_hwirq);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tsbi_irqchip_process_hwirq(chip, hwirq);\n+\t}\n+\n+\treturn SBI_OK;\n+}\n+\n int aplic_cold_irqchip_init(struct aplic_data *aplic)\n {\n \tint rc;\n@@ -308,12 +480,31 @@ int aplic_cold_irqchip_init(struct aplic_data *aplic)\n \t/* Register irqchip device */\n \taplic->irqchip.id = aplic->unique_id;\n \taplic->irqchip.num_hwirq = aplic->num_source + 1;\n+\taplic->irqchip.chip_priv = aplic;\n+\taplic->irqchip.hwirq_mask = aplic_hwirq_mask;\n+\taplic->irqchip.hwirq_unmask = aplic_hwirq_unmask;\n+\taplic->irqchip.hwirq_eoi = aplic_hwirq_eoi;\n+\t/*\n+\t * Only the domain that directly injects interrupts into M-mode external\n+\t * interrupt line should provide process_hwirqs().\n+\t *\n+\t * The other domain (e.g. S-mode) may still be registered so that its\n+\t * other ops (mask/unmask/config/etc.) can be used, but it must not\n+\t * claim to be the external interrupt line provider.\n+\t */\n+\tif (aplic->targets_mmode)\n+\t\taplic->irqchip.process_hwirqs = aplic_process_hwirqs;\n+\taplic->irqchip.hwirq_setup = aplic_hwirq_setup;\n \trc = sbi_irqchip_add_device(&aplic->irqchip);\n \tif (rc)\n \t\treturn rc;\n \n \t/* Attach to the aplic list */\n \tsbi_list_add_tail(&aplic->node, &aplic_list);\n+\trc = sbi_irqchip_register_handler(&aplic->irqchip, 1, aplic->num_source,\n+\t\t\t\t\t aplic_hwirq_handler, NULL);\n+\tif (rc)\n+\t\treturn rc;\n \n \treturn 0;\n }\n", "prefixes": [ "2/3" ] }