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{
    "id": 2195778,
    "url": "http://patchwork.ozlabs.org/api/patches/2195778/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260211-imx2_iomux_warning-v1-4-1c5233771b32@nxp.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260211-imx2_iomux_warning-v1-4-1c5233771b32@nxp.com>",
    "list_archive_url": null,
    "date": "2026-02-11T21:00:03",
    "name": "[4/4] ARM: dts: imx: remove redundant intermediate node in pinmux hierarchy",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "bf18bc734df2511d530374e6b26114aa2eaa31a0",
    "submitter": {
        "id": 68011,
        "url": "http://patchwork.ozlabs.org/api/people/68011/?format=api",
        "name": "Frank Li",
        "email": "Frank.Li@nxp.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260211-imx2_iomux_warning-v1-4-1c5233771b32@nxp.com/mbox/",
    "series": [
        {
            "id": 491907,
            "url": "http://patchwork.ozlabs.org/api/series/491907/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=491907",
            "date": "2026-02-11T20:59:59",
            "name": "ARM: dts: imx: cleanup iomux related CHECK_DTBS warnings for imx1, imx25 and imx27",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/491907/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2195778/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2195778/checks/",
    "tags": {},
    "related": [],
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        "From": "Frank Li <Frank.Li@nxp.com>",
        "Date": "Wed, 11 Feb 2026 16:00:03 -0500",
        "Subject": "[PATCH 4/4] ARM: dts: imx: remove redundant intermediate node in\n pinmux hierarchy",
        "Content-Type": "text/plain; charset=\"utf-8\"",
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        "Message-Id": "<20260211-imx2_iomux_warning-v1-4-1c5233771b32@nxp.com>",
        "References": "<20260211-imx2_iomux_warning-v1-0-1c5233771b32@nxp.com>",
        "In-Reply-To": "<20260211-imx2_iomux_warning-v1-0-1c5233771b32@nxp.com>",
        "To": "Dong Aisheng <aisheng.dong@nxp.com>, Fabio Estevam <festevam@gmail.com>,\n Jacky Bai <ping.bai@nxp.com>,\n Pengutronix Kernel Team <kernel@pengutronix.de>,\n NXP S32 Linux Team <s32@nxp.com>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>",
        "Cc": "linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,\n imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,\n linux-kernel@vger.kernel.org, Frank Li <Frank.Li@nxp.com>",
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    "content": "Remove the redundant intermediate node between the pinmux and group nodes,\nand add the missing \"grp\" suffix to the group node names.\n\nFix below CHECK_DTBS warnings:\narm/boot/dts/nxp/imx/imx27-apf27dev.dtb: iomuxc@10015000 (fsl,imx27-iomuxc): Unevaluated properties are not allowed ('imx27-apf27', 'imx27-apf27dev' were unexpected)\n        from schema $id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml\n\nSigned-off-by: Frank Li <Frank.Li@nxp.com>\n---\n arch/arm/boot/dts/nxp/imx/imx1-ads.dts             | 108 +++++-----\n arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts         |  92 ++++-----\n .../boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi    |  38 ++--\n .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts  |   6 +-\n .../nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts   | 134 ++++++------\n arch/arm/boot/dts/nxp/imx/imx25-pdk.dts            | 190 +++++++++--------\n arch/arm/boot/dts/nxp/imx/imx27-apf27.dts          |  58 +++---\n arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts       | 194 +++++++++---------\n .../boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi    | 228 ++++++++++-----------\n .../nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts   | 194 +++++++++---------\n arch/arm/boot/dts/nxp/imx/imx27-pdk.dts            | 132 ++++++------\n .../dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts     |  92 ++++-----\n .../dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi    | 174 ++++++++--------\n .../boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts  | 206 +++++++++----------\n .../boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi | 154 +++++++-------\n 15 files changed, 985 insertions(+), 1015 deletions(-)",
    "diff": "diff --git a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts\nindex 2c817c4a4c68f8ec9e100db747762067c7a4b483..823e7c42910b8c21c12159ca12f9c1e7f5e4c770 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts\n@@ -76,60 +76,58 @@ nor: flash@0,0 {\n };\n \n &iomuxc {\n-\timx1-ads {\n-\t\tpinctrl_cspi1: cspi1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_SPI1_MISO__SPI1_MISO\t0x0\n-\t\t\t\tMX1_PAD_SPI1_MOSI__SPI1_MOSI\t0x0\n-\t\t\t\tMX1_PAD_SPI1_RDY__SPI1_RDY\t0x0\n-\t\t\t\tMX1_PAD_SPI1_SCLK__SPI1_SCLK\t0x0\n-\t\t\t\tMX1_PAD_SPI1_SS__GPIO3_15\t0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_i2c: i2cgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_I2C_SCL__I2C_SCL\t0x0\n-\t\t\t\tMX1_PAD_I2C_SDA__I2C_SDA\t0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_UART1_TXD__UART1_TXD\t0x0\n-\t\t\t\tMX1_PAD_UART1_RXD__UART1_RXD\t0x0\n-\t\t\t\tMX1_PAD_UART1_CTS__UART1_CTS\t0x0\n-\t\t\t\tMX1_PAD_UART1_RTS__UART1_RTS\t0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_uart2: uart2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_UART2_TXD__UART2_TXD\t0x0\n-\t\t\t\tMX1_PAD_UART2_RXD__UART2_RXD\t0x0\n-\t\t\t\tMX1_PAD_UART2_CTS__UART2_CTS\t0x0\n-\t\t\t\tMX1_PAD_UART2_RTS__UART2_RTS\t0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_weim: weimgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_A0__A0\t\t\t0x0\n-\t\t\t\tMX1_PAD_A16__A16\t\t0x0\n-\t\t\t\tMX1_PAD_A17__A17\t\t0x0\n-\t\t\t\tMX1_PAD_A18__A18\t\t0x0\n-\t\t\t\tMX1_PAD_A19__A19\t\t0x0\n-\t\t\t\tMX1_PAD_A20__A20\t\t0x0\n-\t\t\t\tMX1_PAD_A21__A21\t\t0x0\n-\t\t\t\tMX1_PAD_A22__A22\t\t0x0\n-\t\t\t\tMX1_PAD_A23__A23\t\t0x0\n-\t\t\t\tMX1_PAD_A24__A24\t\t0x0\n-\t\t\t\tMX1_PAD_BCLK__BCLK\t\t0x0\n-\t\t\t\tMX1_PAD_CS4__CS4\t\t0x0\n-\t\t\t\tMX1_PAD_DTACK__DTACK\t\t0x0\n-\t\t\t\tMX1_PAD_ECB__ECB\t\t0x0\n-\t\t\t\tMX1_PAD_LBA__LBA\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_cspi1: cspi1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_SPI1_MISO__SPI1_MISO\t0x0\n+\t\t\tMX1_PAD_SPI1_MOSI__SPI1_MOSI\t0x0\n+\t\t\tMX1_PAD_SPI1_RDY__SPI1_RDY\t0x0\n+\t\t\tMX1_PAD_SPI1_SCLK__SPI1_SCLK\t0x0\n+\t\t\tMX1_PAD_SPI1_SS__GPIO3_15\t0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_i2c: i2cgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_I2C_SCL__I2C_SCL\t0x0\n+\t\t\tMX1_PAD_I2C_SDA__I2C_SDA\t0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_UART1_TXD__UART1_TXD\t0x0\n+\t\t\tMX1_PAD_UART1_RXD__UART1_RXD\t0x0\n+\t\t\tMX1_PAD_UART1_CTS__UART1_CTS\t0x0\n+\t\t\tMX1_PAD_UART1_RTS__UART1_RTS\t0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart2: uart2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_UART2_TXD__UART2_TXD\t0x0\n+\t\t\tMX1_PAD_UART2_RXD__UART2_RXD\t0x0\n+\t\t\tMX1_PAD_UART2_CTS__UART2_CTS\t0x0\n+\t\t\tMX1_PAD_UART2_RTS__UART2_RTS\t0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_weim: weimgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_A0__A0\t\t\t0x0\n+\t\t\tMX1_PAD_A16__A16\t\t0x0\n+\t\t\tMX1_PAD_A17__A17\t\t0x0\n+\t\t\tMX1_PAD_A18__A18\t\t0x0\n+\t\t\tMX1_PAD_A19__A19\t\t0x0\n+\t\t\tMX1_PAD_A20__A20\t\t0x0\n+\t\t\tMX1_PAD_A21__A21\t\t0x0\n+\t\t\tMX1_PAD_A22__A22\t\t0x0\n+\t\t\tMX1_PAD_A23__A23\t\t0x0\n+\t\t\tMX1_PAD_A24__A24\t\t0x0\n+\t\t\tMX1_PAD_BCLK__BCLK\t\t0x0\n+\t\t\tMX1_PAD_CS4__CS4\t\t0x0\n+\t\t\tMX1_PAD_DTACK__DTACK\t\t0x0\n+\t\t\tMX1_PAD_ECB__ECB\t\t0x0\n+\t\t\tMX1_PAD_LBA__LBA\t\t0x0\n+\t\t>;\n \t};\n };\ndiff --git a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts\nindex 058e9435524fe1d12a95e7dba36ec92a073403b3..794e5bfee36706e64f0f23850a9307d04f4747f3 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts\n@@ -67,56 +67,54 @@ eth: ethernet@4,c00000 {\n };\n \n &iomuxc {\n-\timx1-apf9328 {\n-\t\tpinctrl_eth: ethgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_SIM_SVEN__GPIO2_14\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_eth: ethgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_SIM_SVEN__GPIO2_14\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_i2c: i2cgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_I2C_SCL__I2C_SCL\t0x0\n-\t\t\t\tMX1_PAD_I2C_SDA__I2C_SDA\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c: i2cgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_I2C_SCL__I2C_SCL\t0x0\n+\t\t\tMX1_PAD_I2C_SDA__I2C_SDA\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_UART1_TXD__UART1_TXD\t0x0\n-\t\t\t\tMX1_PAD_UART1_RXD__UART1_RXD\t0x0\n-\t\t\t\tMX1_PAD_UART1_CTS__UART1_CTS\t0x0\n-\t\t\t\tMX1_PAD_UART1_RTS__UART1_RTS\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_UART1_TXD__UART1_TXD\t0x0\n+\t\t\tMX1_PAD_UART1_RXD__UART1_RXD\t0x0\n+\t\t\tMX1_PAD_UART1_CTS__UART1_CTS\t0x0\n+\t\t\tMX1_PAD_UART1_RTS__UART1_RTS\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart2: uart2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_UART2_TXD__UART2_TXD\t0x0\n-\t\t\t\tMX1_PAD_UART2_RXD__UART2_RXD\t0x0\n-\t\t\t\tMX1_PAD_UART2_CTS__UART2_CTS\t0x0\n-\t\t\t\tMX1_PAD_UART2_RTS__UART2_RTS\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart2: uart2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_UART2_TXD__UART2_TXD\t0x0\n+\t\t\tMX1_PAD_UART2_RXD__UART2_RXD\t0x0\n+\t\t\tMX1_PAD_UART2_CTS__UART2_CTS\t0x0\n+\t\t\tMX1_PAD_UART2_RTS__UART2_RTS\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_weim: weimgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX1_PAD_A0__A0\t\t\t0x0\n-\t\t\t\tMX1_PAD_A16__A16\t\t0x0\n-\t\t\t\tMX1_PAD_A17__A17\t\t0x0\n-\t\t\t\tMX1_PAD_A18__A18\t\t0x0\n-\t\t\t\tMX1_PAD_A19__A19\t\t0x0\n-\t\t\t\tMX1_PAD_A20__A20\t\t0x0\n-\t\t\t\tMX1_PAD_A21__A21\t\t0x0\n-\t\t\t\tMX1_PAD_A22__A22\t\t0x0\n-\t\t\t\tMX1_PAD_A23__A23\t\t0x0\n-\t\t\t\tMX1_PAD_A24__A24\t\t0x0\n-\t\t\t\tMX1_PAD_BCLK__BCLK\t\t0x0\n-\t\t\t\tMX1_PAD_CS4__CS4\t\t0x0\n-\t\t\t\tMX1_PAD_DTACK__DTACK\t\t0x0\n-\t\t\t\tMX1_PAD_ECB__ECB\t\t0x0\n-\t\t\t\tMX1_PAD_LBA__LBA\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_weim: weimgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX1_PAD_A0__A0\t\t\t0x0\n+\t\t\tMX1_PAD_A16__A16\t\t0x0\n+\t\t\tMX1_PAD_A17__A17\t\t0x0\n+\t\t\tMX1_PAD_A18__A18\t\t0x0\n+\t\t\tMX1_PAD_A19__A19\t\t0x0\n+\t\t\tMX1_PAD_A20__A20\t\t0x0\n+\t\t\tMX1_PAD_A21__A21\t\t0x0\n+\t\t\tMX1_PAD_A22__A22\t\t0x0\n+\t\t\tMX1_PAD_A23__A23\t\t0x0\n+\t\t\tMX1_PAD_A24__A24\t\t0x0\n+\t\t\tMX1_PAD_BCLK__BCLK\t\t0x0\n+\t\t\tMX1_PAD_CS4__CS4\t\t0x0\n+\t\t\tMX1_PAD_DTACK__DTACK\t\t0x0\n+\t\t\tMX1_PAD_ECB__ECB\t\t0x0\n+\t\t\tMX1_PAD_LBA__LBA\t\t0x0\n+\t\t>;\n \t};\n };\ndiff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi\nindex 93a6e4e680b45133885a7c04693ae2e49dd1db85..31dc2a6403628db1527a1707460afbf9de893abd 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi\n+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi\n@@ -34,27 +34,25 @@ rtc@51 {\n };\n \n &iomuxc {\n-\timx25-eukrea-cpuimx25 {\n-\t\tpinctrl_fec: fecgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_FEC_MDC__FEC_MDC\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_MDIO__FEC_MDIO\t\t0x400001e0\n-\t\t\t\tMX25_PAD_FEC_TDATA0__FEC_TDATA0\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_TDATA1__FEC_TDATA1\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_TX_EN__FEC_TX_EN\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_RDATA0__FEC_RDATA0\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_RDATA1__FEC_RDATA1\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_RX_DV__FEC_RX_DV\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_TX_CLK__FEC_TX_CLK\t\t0x1c0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_fec: fecgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_FEC_MDC__FEC_MDC\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_MDIO__FEC_MDIO\t\t0x400001e0\n+\t\t\tMX25_PAD_FEC_TDATA0__FEC_TDATA0\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_TDATA1__FEC_TDATA1\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_TX_EN__FEC_TX_EN\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_RDATA0__FEC_RDATA0\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_RDATA1__FEC_RDATA1\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_RX_DV__FEC_RX_DV\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_TX_CLK__FEC_TX_CLK\t\t0x1c0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_i2c1: i2c1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_I2C1_CLK__I2C1_CLK\t\t0x80000000\n-\t\t\t\tMX25_PAD_I2C1_DAT__I2C1_DAT\t\t0x80000000\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c1: i2c1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_I2C1_CLK__I2C1_CLK\t\t0x80000000\n+\t\t\tMX25_PAD_I2C1_DAT__I2C1_DAT\t\t0x80000000\n+\t\t>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts\nindex 6cddb2cc36fe2aa4a07cad18c0fc9f2014314c1f..e08fcbfef4d5d97897943f64b9ce9c8d91104d05 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts\n@@ -43,10 +43,8 @@ reg_lcd_3v3: regulator-0 {\n };\n \n &iomuxc {\n-\timx25-eukrea-mbimxsd25-baseboard-cmo-qvga {\n-\t\tpinctrl_reg_lcd_3v3: reg_lcd_3v3 {\n-\t\t\tfsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;\n-\t\t};\n+\tpinctrl_reg_lcd_3v3: reg_lcd_3v3grp {\n+\t\tfsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts\nindex c7207ea437c404399213b2f4939af22159e1ea68..cf127e00793effbd7231972f464b0dc03dfa6bfe 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts\n@@ -68,80 +68,78 @@ tlv320aic23: codec@1a {\n };\n \n &iomuxc {\n-\timx25-eukrea-mbimxsd25-baseboard {\n-\t\tpinctrl_audmux: audmuxgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_KPP_COL3__AUD5_TXFS\t\t0xe0\n-\t\t\t\tMX25_PAD_KPP_COL2__AUD5_TXC\t\t0xe0\n-\t\t\t\tMX25_PAD_KPP_COL1__AUD5_RXD\t\t0xe0\n-\t\t\t\tMX25_PAD_KPP_COL0__AUD5_TXD\t\t0xe0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_audmux: audmuxgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_KPP_COL3__AUD5_TXFS\t\t0xe0\n+\t\t\tMX25_PAD_KPP_COL2__AUD5_TXC\t\t0xe0\n+\t\t\tMX25_PAD_KPP_COL1__AUD5_RXD\t\t0xe0\n+\t\t\tMX25_PAD_KPP_COL0__AUD5_TXD\t\t0xe0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_esdhc1: esdhc1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_SD1_CMD__ESDHC1_CMD\t\t0x400000c0\n-\t\t\t\tMX25_PAD_SD1_CLK__ESDHC1_CLK\t\t0x400000c0\n-\t\t\t\tMX25_PAD_SD1_DATA0__ESDHC1_DAT0\t\t0x400000c0\n-\t\t\t\tMX25_PAD_SD1_DATA1__ESDHC1_DAT1\t\t0x400000c0\n-\t\t\t\tMX25_PAD_SD1_DATA2__ESDHC1_DAT2\t\t0x400000c0\n-\t\t\t\tMX25_PAD_SD1_DATA3__ESDHC1_DAT3\t\t0x400000c0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_esdhc1: esdhc1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_SD1_CMD__ESDHC1_CMD\t\t0x400000c0\n+\t\t\tMX25_PAD_SD1_CLK__ESDHC1_CLK\t\t0x400000c0\n+\t\t\tMX25_PAD_SD1_DATA0__ESDHC1_DAT0\t\t0x400000c0\n+\t\t\tMX25_PAD_SD1_DATA1__ESDHC1_DAT1\t\t0x400000c0\n+\t\t\tMX25_PAD_SD1_DATA2__ESDHC1_DAT2\t\t0x400000c0\n+\t\t\tMX25_PAD_SD1_DATA3__ESDHC1_DAT3\t\t0x400000c0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_gpiokeys: gpiokeysgrp {\n-\t\t\tfsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;\n-\t\t};\n+\tpinctrl_gpiokeys: gpiokeysgrp {\n+\t\tfsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;\n+\t};\n \n-\t\tpinctrl_gpioled: gpioledgrp {\n-\t\t\tfsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;\n-\t\t};\n+\tpinctrl_gpioled: gpioledgrp {\n+\t\tfsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;\n+\t};\n \n-\t\tpinctrl_lcdc: lcdcgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_LD0__LD0\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD1__LD1\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD2__LD2\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD3__LD3\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD4__LD4\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD5__LD5\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD6__LD6\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD7__LD7\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD8__LD8\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD9__LD9\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD10__LD10\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD11__LD11\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD12__LD12\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD13__LD13\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD14__LD14\t\t\t0x1\n-\t\t\t\tMX25_PAD_LD15__LD15\t\t\t0x1\n-\t\t\t\tMX25_PAD_GPIO_E__LD16\t\t\t0x1\n-\t\t\t\tMX25_PAD_GPIO_F__LD17\t\t\t0x1\n-\t\t\t\tMX25_PAD_HSYNC__HSYNC\t\t\t0x80000000\n-\t\t\t\tMX25_PAD_VSYNC__VSYNC\t\t\t0x80000000\n-\t\t\t\tMX25_PAD_LSCLK__LSCLK\t\t\t0x80000000\n-\t\t\t\tMX25_PAD_OE_ACD__OE_ACD\t\t\t0x80000000\n-\t\t\t\tMX25_PAD_CONTRAST__CONTRAST\t\t0x80000000\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_lcdc: lcdcgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_LD0__LD0\t\t\t0x1\n+\t\t\tMX25_PAD_LD1__LD1\t\t\t0x1\n+\t\t\tMX25_PAD_LD2__LD2\t\t\t0x1\n+\t\t\tMX25_PAD_LD3__LD3\t\t\t0x1\n+\t\t\tMX25_PAD_LD4__LD4\t\t\t0x1\n+\t\t\tMX25_PAD_LD5__LD5\t\t\t0x1\n+\t\t\tMX25_PAD_LD6__LD6\t\t\t0x1\n+\t\t\tMX25_PAD_LD7__LD7\t\t\t0x1\n+\t\t\tMX25_PAD_LD8__LD8\t\t\t0x1\n+\t\t\tMX25_PAD_LD9__LD9\t\t\t0x1\n+\t\t\tMX25_PAD_LD10__LD10\t\t\t0x1\n+\t\t\tMX25_PAD_LD11__LD11\t\t\t0x1\n+\t\t\tMX25_PAD_LD12__LD12\t\t\t0x1\n+\t\t\tMX25_PAD_LD13__LD13\t\t\t0x1\n+\t\t\tMX25_PAD_LD14__LD14\t\t\t0x1\n+\t\t\tMX25_PAD_LD15__LD15\t\t\t0x1\n+\t\t\tMX25_PAD_GPIO_E__LD16\t\t\t0x1\n+\t\t\tMX25_PAD_GPIO_F__LD17\t\t\t0x1\n+\t\t\tMX25_PAD_HSYNC__HSYNC\t\t\t0x80000000\n+\t\t\tMX25_PAD_VSYNC__VSYNC\t\t\t0x80000000\n+\t\t\tMX25_PAD_LSCLK__LSCLK\t\t\t0x80000000\n+\t\t\tMX25_PAD_OE_ACD__OE_ACD\t\t\t0x80000000\n+\t\t\tMX25_PAD_CONTRAST__CONTRAST\t\t0x80000000\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_UART1_RTS__UART1_RTS\t\t0xe0\n-\t\t\t\tMX25_PAD_UART1_CTS__UART1_CTS\t\t0xe0\n-\t\t\t\tMX25_PAD_UART1_TXD__UART1_TXD\t\t0x80000000\n-\t\t\t\tMX25_PAD_UART1_RXD__UART1_RXD\t\t0xc0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_UART1_RTS__UART1_RTS\t\t0xe0\n+\t\t\tMX25_PAD_UART1_CTS__UART1_CTS\t\t0xe0\n+\t\t\tMX25_PAD_UART1_TXD__UART1_TXD\t\t0x80000000\n+\t\t\tMX25_PAD_UART1_RXD__UART1_RXD\t\t0xc0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart2: uart2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_UART2_RXD__UART2_RXD\t\t0x80000000\n-\t\t\t\tMX25_PAD_UART2_TXD__UART2_TXD\t\t0x80000000\n-\t\t\t\tMX25_PAD_UART2_RTS__UART2_RTS\t\t0x80000000\n-\t\t\t\tMX25_PAD_UART2_CTS__UART2_CTS\t\t0x80000000\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart2: uart2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_UART2_RXD__UART2_RXD\t\t0x80000000\n+\t\t\tMX25_PAD_UART2_TXD__UART2_TXD\t\t0x80000000\n+\t\t\tMX25_PAD_UART2_RTS__UART2_RTS\t\t0x80000000\n+\t\t\tMX25_PAD_UART2_CTS__UART2_CTS\t\t0x80000000\n+\t\t>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts\nindex dd176fb54e58595b34a8cd2c35769f341729895a..a35778ba6ffa0474d67f77005dfa4299b27d947c 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts\n@@ -130,109 +130,107 @@ codec: sgtl5000@a {\n };\n \n &iomuxc {\n-\timx25-pdk {\n-\t\tpinctrl_audmux: audmuxgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_RW__AUD4_TXFS\t\t\t0xe0\n-\t\t\t\tMX25_PAD_OE__AUD4_TXC\t\t\t0xe0\n-\t\t\t\tMX25_PAD_EB0__AUD4_TXD\t\t\t0xe0\n-\t\t\t\tMX25_PAD_EB1__AUD4_RXD\t\t\t0xe0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_audmux: audmuxgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_RW__AUD4_TXFS\t\t\t0xe0\n+\t\t\tMX25_PAD_OE__AUD4_TXC\t\t\t0xe0\n+\t\t\tMX25_PAD_EB0__AUD4_TXD\t\t\t0xe0\n+\t\t\tMX25_PAD_EB1__AUD4_RXD\t\t\t0xe0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_can1: can1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_GPIO_A__CAN1_TX\t\t0x0\n-\t\t\t\tMX25_PAD_GPIO_B__CAN1_RX\t\t0x0\n-\t\t\t\tMX25_PAD_D14__GPIO_4_6 \t\t\t0x80000000\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_can1: can1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_GPIO_A__CAN1_TX\t\t0x0\n+\t\t\tMX25_PAD_GPIO_B__CAN1_RX\t\t0x0\n+\t\t\tMX25_PAD_D14__GPIO_4_6\t\t\t0x80000000\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_esdhc1: esdhc1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_SD1_CMD__ESDHC1_CMD\t\t0x80000000\n-\t\t\t\tMX25_PAD_SD1_CLK__ESDHC1_CLK\t\t0x80000000\n-\t\t\t\tMX25_PAD_SD1_DATA0__ESDHC1_DAT0\t\t0x80000000\n-\t\t\t\tMX25_PAD_SD1_DATA1__ESDHC1_DAT1\t\t0x80000000\n-\t\t\t\tMX25_PAD_SD1_DATA2__ESDHC1_DAT2\t\t0x80000000\n-\t\t\t\tMX25_PAD_SD1_DATA3__ESDHC1_DAT3\t\t0x80000000\n-\t\t\t\tMX25_PAD_A14__GPIO_2_0\t\t\t0x80000000\n-\t\t\t\tMX25_PAD_A15__GPIO_2_1\t\t\t0x80000000\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_esdhc1: esdhc1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_SD1_CMD__ESDHC1_CMD\t\t0x80000000\n+\t\t\tMX25_PAD_SD1_CLK__ESDHC1_CLK\t\t0x80000000\n+\t\t\tMX25_PAD_SD1_DATA0__ESDHC1_DAT0\t\t0x80000000\n+\t\t\tMX25_PAD_SD1_DATA1__ESDHC1_DAT1\t\t0x80000000\n+\t\t\tMX25_PAD_SD1_DATA2__ESDHC1_DAT2\t\t0x80000000\n+\t\t\tMX25_PAD_SD1_DATA3__ESDHC1_DAT3\t\t0x80000000\n+\t\t\tMX25_PAD_A14__GPIO_2_0\t\t\t0x80000000\n+\t\t\tMX25_PAD_A15__GPIO_2_1\t\t\t0x80000000\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_fec: fecgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_FEC_MDC__FEC_MDC\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_MDIO__FEC_MDIO\t\t0x400001e0\n-\t\t\t\tMX25_PAD_FEC_TDATA0__FEC_TDATA0\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_TDATA1__FEC_TDATA1\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_TX_EN__FEC_TX_EN\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_RDATA0__FEC_RDATA0\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_RDATA1__FEC_RDATA1\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_RX_DV__FEC_RX_DV\t\t0x80000000\n-\t\t\t\tMX25_PAD_FEC_TX_CLK__FEC_TX_CLK\t\t0x1c0\n-\t\t\t\tMX25_PAD_A17__GPIO_2_3\t\t\t0x80000000\n-\t\t\t\tMX25_PAD_D12__GPIO_4_8\t\t\t0x80000000\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_fec: fecgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_FEC_MDC__FEC_MDC\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_MDIO__FEC_MDIO\t\t0x400001e0\n+\t\t\tMX25_PAD_FEC_TDATA0__FEC_TDATA0\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_TDATA1__FEC_TDATA1\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_TX_EN__FEC_TX_EN\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_RDATA0__FEC_RDATA0\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_RDATA1__FEC_RDATA1\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_RX_DV__FEC_RX_DV\t\t0x80000000\n+\t\t\tMX25_PAD_FEC_TX_CLK__FEC_TX_CLK\t\t0x1c0\n+\t\t\tMX25_PAD_A17__GPIO_2_3\t\t\t0x80000000\n+\t\t\tMX25_PAD_D12__GPIO_4_8\t\t\t0x80000000\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_i2c1: i2c1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_I2C1_CLK__I2C1_CLK\t\t0x80000000\n-\t\t\t\tMX25_PAD_I2C1_DAT__I2C1_DAT\t\t0x80000000\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c1: i2c1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_I2C1_CLK__I2C1_CLK\t\t0x80000000\n+\t\t\tMX25_PAD_I2C1_DAT__I2C1_DAT\t\t0x80000000\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_kpp: kppgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_KPP_ROW0__KPP_ROW0\t0x80000000\n-\t\t\t\tMX25_PAD_KPP_ROW1__KPP_ROW1\t0x80000000\n-\t\t\t\tMX25_PAD_KPP_ROW2__KPP_ROW2\t0x80000000\n-\t\t\t\tMX25_PAD_KPP_ROW3__KPP_ROW3\t0x80000000\n-\t\t\t\tMX25_PAD_KPP_COL0__KPP_COL0\t0x80000000\n-\t\t\t\tMX25_PAD_KPP_COL1__KPP_COL1\t0x80000000\n-\t\t\t\tMX25_PAD_KPP_COL2__KPP_COL2\t0x80000000\n-\t\t\t\tMX25_PAD_KPP_COL3__KPP_COL3\t0x80000000\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_kpp: kppgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_KPP_ROW0__KPP_ROW0\t0x80000000\n+\t\t\tMX25_PAD_KPP_ROW1__KPP_ROW1\t0x80000000\n+\t\t\tMX25_PAD_KPP_ROW2__KPP_ROW2\t0x80000000\n+\t\t\tMX25_PAD_KPP_ROW3__KPP_ROW3\t0x80000000\n+\t\t\tMX25_PAD_KPP_COL0__KPP_COL0\t0x80000000\n+\t\t\tMX25_PAD_KPP_COL1__KPP_COL1\t0x80000000\n+\t\t\tMX25_PAD_KPP_COL2__KPP_COL2\t0x80000000\n+\t\t\tMX25_PAD_KPP_COL3__KPP_COL3\t0x80000000\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_lcd: lcdgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_LD0__LD0\t\t0xe0\n-\t\t\t\tMX25_PAD_LD1__LD1\t\t0xe0\n-\t\t\t\tMX25_PAD_LD2__LD2\t\t0xe0\n-\t\t\t\tMX25_PAD_LD3__LD3\t\t0xe0\n-\t\t\t\tMX25_PAD_LD4__LD4\t\t0xe0\n-\t\t\t\tMX25_PAD_LD5__LD5\t\t0xe0\n-\t\t\t\tMX25_PAD_LD6__LD6\t\t0xe0\n-\t\t\t\tMX25_PAD_LD7__LD7\t\t0xe0\n-\t\t\t\tMX25_PAD_LD8__LD8\t\t0xe0\n-\t\t\t\tMX25_PAD_LD9__LD9\t\t0xe0\n-\t\t\t\tMX25_PAD_LD10__LD10\t\t0xe0\n-\t\t\t\tMX25_PAD_LD11__LD11\t\t0xe0\n-\t\t\t\tMX25_PAD_LD12__LD12\t\t0xe0\n-\t\t\t\tMX25_PAD_LD13__LD13\t\t0xe0\n-\t\t\t\tMX25_PAD_LD14__LD14\t\t0xe0\n-\t\t\t\tMX25_PAD_LD15__LD15\t\t0xe0\n-\t\t\t\tMX25_PAD_GPIO_E__LD16\t\t0xe0\n-\t\t\t\tMX25_PAD_GPIO_F__LD17\t\t0xe0\n-\t\t\t\tMX25_PAD_HSYNC__HSYNC\t\t0xe0\n-\t\t\t\tMX25_PAD_VSYNC__VSYNC\t\t0xe0\n-\t\t\t\tMX25_PAD_LSCLK__LSCLK\t\t0xe0\n-\t\t\t\tMX25_PAD_OE_ACD__OE_ACD\t\t0xe0\n-\t\t\t\tMX25_PAD_CONTRAST__CONTRAST\t0xe0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_lcd: lcdgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_LD0__LD0\t\t0xe0\n+\t\t\tMX25_PAD_LD1__LD1\t\t0xe0\n+\t\t\tMX25_PAD_LD2__LD2\t\t0xe0\n+\t\t\tMX25_PAD_LD3__LD3\t\t0xe0\n+\t\t\tMX25_PAD_LD4__LD4\t\t0xe0\n+\t\t\tMX25_PAD_LD5__LD5\t\t0xe0\n+\t\t\tMX25_PAD_LD6__LD6\t\t0xe0\n+\t\t\tMX25_PAD_LD7__LD7\t\t0xe0\n+\t\t\tMX25_PAD_LD8__LD8\t\t0xe0\n+\t\t\tMX25_PAD_LD9__LD9\t\t0xe0\n+\t\t\tMX25_PAD_LD10__LD10\t\t0xe0\n+\t\t\tMX25_PAD_LD11__LD11\t\t0xe0\n+\t\t\tMX25_PAD_LD12__LD12\t\t0xe0\n+\t\t\tMX25_PAD_LD13__LD13\t\t0xe0\n+\t\t\tMX25_PAD_LD14__LD14\t\t0xe0\n+\t\t\tMX25_PAD_LD15__LD15\t\t0xe0\n+\t\t\tMX25_PAD_GPIO_E__LD16\t\t0xe0\n+\t\t\tMX25_PAD_GPIO_F__LD17\t\t0xe0\n+\t\t\tMX25_PAD_HSYNC__HSYNC\t\t0xe0\n+\t\t\tMX25_PAD_VSYNC__VSYNC\t\t0xe0\n+\t\t\tMX25_PAD_LSCLK__LSCLK\t\t0xe0\n+\t\t\tMX25_PAD_OE_ACD__OE_ACD\t\t0xe0\n+\t\t\tMX25_PAD_CONTRAST__CONTRAST\t0xe0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX25_PAD_UART1_RTS__UART1_RTS\t\t0xe0\n-\t\t\t\tMX25_PAD_UART1_CTS__UART1_CTS\t\t0xe0\n-\t\t\t\tMX25_PAD_UART1_TXD__UART1_TXD\t\t0x80000000\n-\t\t\t\tMX25_PAD_UART1_RXD__UART1_RXD\t\t0xc0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX25_PAD_UART1_RTS__UART1_RTS\t\t0xe0\n+\t\t\tMX25_PAD_UART1_CTS__UART1_CTS\t\t0xe0\n+\t\t\tMX25_PAD_UART1_TXD__UART1_TXD\t\t0x80000000\n+\t\t\tMX25_PAD_UART1_RXD__UART1_RXD\t\t0xc0\n+\t\t>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts\nindex 745d5d40995251ddb3ed33ddc41686ed27db00a8..b67bb21af3dedf1124ccdff6a1ac3ef703a6e22d 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts\n@@ -24,36 +24,34 @@ &clk_osc26m {\n };\n \n &iomuxc {\n-\timx27-apf27 {\n-\t\tpinctrl_fec1: fec1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0 0x0\n-\t\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA13__FEC_COL 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN 0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART1_TXD__UART1_TXD 0x0\n-\t\t\t\tMX27_PAD_UART1_RXD__UART1_RXD 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_fec1: fec1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0 0x0\n+\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1 0x0\n+\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2 0x0\n+\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3 0x0\n+\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER 0x0\n+\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1 0x0\n+\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2 0x0\n+\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3 0x0\n+\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO 0x0\n+\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC 0x0\n+\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS 0x0\n+\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0\n+\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0 0x0\n+\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV 0x0\n+\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0\n+\t\t\tMX27_PAD_ATA_DATA13__FEC_COL 0x0\n+\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER 0x0\n+\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN 0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART1_TXD__UART1_TXD 0x0\n+\t\t\tMX27_PAD_UART1_RXD__UART1_RXD 0x0\n+\t\t>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts\nindex 849306cb4532dbdeb5302ee1c66256247eda645f..dba97912cfd75964ee4a2966fae897e7f0b037e7 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts\n@@ -122,116 +122,114 @@ &i2c2 {\n };\n \n &iomuxc {\n-\timx27-apf27dev {\n-\t\tpinctrl_cspi1: cspi1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0\n-\t\t\t\tMX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0\n-\t\t\t\tMX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_cspi1: cspi1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0\n+\t\t\tMX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0\n+\t\t\tMX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_cspi1_cs: cspi1csgrp {\n-\t\t\tfsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;\n-\t\t};\n+\tpinctrl_cspi1_cs: cspi1csgrp {\n+\t\tfsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;\n+\t};\n \n-\t\tpinctrl_cspi2: cspi2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0\n-\t\t\t\tMX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0\n-\t\t\t\tMX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_cspi2: cspi2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0\n+\t\t\tMX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0\n+\t\t\tMX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_cspi2_cs: cspi2csgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CSI_D5__GPIO2_17 0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS0__GPIO4_21 0x0\n-\t\t\t\tMX27_PAD_CSPI1_SS1__GPIO4_27 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_cspi2_cs: cspi2csgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CSI_D5__GPIO2_17 0x0\n+\t\t\tMX27_PAD_CSPI2_SS0__GPIO4_21 0x0\n+\t\t\tMX27_PAD_CSPI1_SS1__GPIO4_27 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_gpio_leds: gpioledsgrp {\n-\t\t\tfsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;\n-\t\t};\n+\tpinctrl_gpio_leds: gpioledsgrp {\n+\t\tfsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;\n+\t};\n \n-\t\tpinctrl_gpio_keys: gpiokeysgrp {\n-\t\t\tfsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;\n-\t\t};\n+\tpinctrl_gpio_keys: gpiokeysgrp {\n+\t\tfsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;\n+\t};\n \n-\t\tpinctrl_imxfb1: imxfbgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CLS__CLS 0x0\n-\t\t\t\tMX27_PAD_CONTRAST__CONTRAST 0x0\n-\t\t\t\tMX27_PAD_LD0__LD0 0x0\n-\t\t\t\tMX27_PAD_LD1__LD1 0x0\n-\t\t\t\tMX27_PAD_LD2__LD2 0x0\n-\t\t\t\tMX27_PAD_LD3__LD3 0x0\n-\t\t\t\tMX27_PAD_LD4__LD4 0x0\n-\t\t\t\tMX27_PAD_LD5__LD5 0x0\n-\t\t\t\tMX27_PAD_LD6__LD6 0x0\n-\t\t\t\tMX27_PAD_LD7__LD7 0x0\n-\t\t\t\tMX27_PAD_LD8__LD8 0x0\n-\t\t\t\tMX27_PAD_LD9__LD9 0x0\n-\t\t\t\tMX27_PAD_LD10__LD10 0x0\n-\t\t\t\tMX27_PAD_LD11__LD11 0x0\n-\t\t\t\tMX27_PAD_LD12__LD12 0x0\n-\t\t\t\tMX27_PAD_LD13__LD13 0x0\n-\t\t\t\tMX27_PAD_LD14__LD14 0x0\n-\t\t\t\tMX27_PAD_LD15__LD15 0x0\n-\t\t\t\tMX27_PAD_LD16__LD16 0x0\n-\t\t\t\tMX27_PAD_LD17__LD17 0x0\n-\t\t\t\tMX27_PAD_LSCLK__LSCLK 0x0\n-\t\t\t\tMX27_PAD_OE_ACD__OE_ACD 0x0\n-\t\t\t\tMX27_PAD_PS__PS 0x0\n-\t\t\t\tMX27_PAD_REV__REV 0x0\n-\t\t\t\tMX27_PAD_SPL_SPR__SPL_SPR 0x0\n-\t\t\t\tMX27_PAD_HSYNC__HSYNC 0x0\n-\t\t\t\tMX27_PAD_VSYNC__VSYNC 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_imxfb1: imxfbgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CLS__CLS 0x0\n+\t\t\tMX27_PAD_CONTRAST__CONTRAST 0x0\n+\t\t\tMX27_PAD_LD0__LD0 0x0\n+\t\t\tMX27_PAD_LD1__LD1 0x0\n+\t\t\tMX27_PAD_LD2__LD2 0x0\n+\t\t\tMX27_PAD_LD3__LD3 0x0\n+\t\t\tMX27_PAD_LD4__LD4 0x0\n+\t\t\tMX27_PAD_LD5__LD5 0x0\n+\t\t\tMX27_PAD_LD6__LD6 0x0\n+\t\t\tMX27_PAD_LD7__LD7 0x0\n+\t\t\tMX27_PAD_LD8__LD8 0x0\n+\t\t\tMX27_PAD_LD9__LD9 0x0\n+\t\t\tMX27_PAD_LD10__LD10 0x0\n+\t\t\tMX27_PAD_LD11__LD11 0x0\n+\t\t\tMX27_PAD_LD12__LD12 0x0\n+\t\t\tMX27_PAD_LD13__LD13 0x0\n+\t\t\tMX27_PAD_LD14__LD14 0x0\n+\t\t\tMX27_PAD_LD15__LD15 0x0\n+\t\t\tMX27_PAD_LD16__LD16 0x0\n+\t\t\tMX27_PAD_LD17__LD17 0x0\n+\t\t\tMX27_PAD_LSCLK__LSCLK 0x0\n+\t\t\tMX27_PAD_OE_ACD__OE_ACD 0x0\n+\t\t\tMX27_PAD_PS__PS 0x0\n+\t\t\tMX27_PAD_REV__REV 0x0\n+\t\t\tMX27_PAD_SPL_SPR__SPL_SPR 0x0\n+\t\t\tMX27_PAD_HSYNC__HSYNC 0x0\n+\t\t\tMX27_PAD_VSYNC__VSYNC 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_i2c1: i2c1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_I2C_DATA__I2C_DATA 0x0\n-\t\t\t\tMX27_PAD_I2C_CLK__I2C_CLK 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c1: i2c1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_I2C_DATA__I2C_DATA 0x0\n+\t\t\tMX27_PAD_I2C_CLK__I2C_CLK 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_i2c2: i2c2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_I2C2_SDA__I2C2_SDA 0x0\n-\t\t\t\tMX27_PAD_I2C2_SCL__I2C2_SCL 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c2: i2c2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_I2C2_SDA__I2C2_SDA 0x0\n+\t\t\tMX27_PAD_I2C2_SCL__I2C2_SCL 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_max1027: max1027 {\n-\t\t\t fsl,pins = <\n-\t\t\t\t MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */\n-\t\t\t\t MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_max1027: max1027grp {\n+\t\t fsl,pins = <\n+\t\t\t MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */\n+\t\t\t MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_pwm: pwmgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_PWMO__PWMO 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_pwm: pwmgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_PWMO__PWMO 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_sdhc2: sdhc2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD2_CLK__SD2_CLK 0x0\n-\t\t\t\tMX27_PAD_SD2_CMD__SD2_CMD 0x0\n-\t\t\t\tMX27_PAD_SD2_D0__SD2_D0 0x0\n-\t\t\t\tMX27_PAD_SD2_D1__SD2_D1 0x0\n-\t\t\t\tMX27_PAD_SD2_D2__SD2_D2 0x0\n-\t\t\t\tMX27_PAD_SD2_D3__SD2_D3 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_sdhc2: sdhc2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD2_CLK__SD2_CLK 0x0\n+\t\t\tMX27_PAD_SD2_CMD__SD2_CMD 0x0\n+\t\t\tMX27_PAD_SD2_D0__SD2_D0 0x0\n+\t\t\tMX27_PAD_SD2_D1__SD2_D1 0x0\n+\t\t\tMX27_PAD_SD2_D2__SD2_D2 0x0\n+\t\t\tMX27_PAD_SD2_D3__SD2_D3 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_sdhc2_cd: sdhc2cdgrp {\n-\t\t\tfsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;\n-\t\t};\n+\tpinctrl_sdhc2_cd: sdhc2cdgrp {\n+\t\tfsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi\nindex c7e92358487826874e74d819af17764311016d4a..3df70ed6056c4d122c83f9d6dd1ec1af3c64ff0b 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi\n@@ -154,131 +154,129 @@ uart8250@3,1000000 {\n };\n \n &iomuxc {\n-\timx27-eukrea-cpuimx27 {\n-\t\tpinctrl_fec: fecgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0\t\t0x0\n-\t\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA13__FEC_COL\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER\t\t0x0\n-\t\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_fec: fecgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0\t\t0x0\n+\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA13__FEC_COL\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER\t\t0x0\n+\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_i2c1: i2c1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_I2C_DATA__I2C_DATA\t\t0x0\n-\t\t\t\tMX27_PAD_I2C_CLK__I2C_CLK\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c1: i2c1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_I2C_DATA__I2C_DATA\t\t0x0\n+\t\t\tMX27_PAD_I2C_CLK__I2C_CLK\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_nfc: nfcgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_NFRB__NFRB\t\t\t0x0\n-\t\t\t\tMX27_PAD_NFCLE__NFCLE\t\t\t0x0\n-\t\t\t\tMX27_PAD_NFWP_B__NFWP_B\t\t\t0x0\n-\t\t\t\tMX27_PAD_NFCE_B__NFCE_B\t\t\t0x0\n-\t\t\t\tMX27_PAD_NFALE__NFALE\t\t\t0x0\n-\t\t\t\tMX27_PAD_NFRE_B__NFRE_B\t\t\t0x0\n-\t\t\t\tMX27_PAD_NFWE_B__NFWE_B\t\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_nfc: nfcgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_NFRB__NFRB\t\t\t0x0\n+\t\t\tMX27_PAD_NFCLE__NFCLE\t\t\t0x0\n+\t\t\tMX27_PAD_NFWP_B__NFWP_B\t\t\t0x0\n+\t\t\tMX27_PAD_NFCE_B__NFCE_B\t\t\t0x0\n+\t\t\tMX27_PAD_NFALE__NFALE\t\t\t0x0\n+\t\t\tMX27_PAD_NFRE_B__NFRE_B\t\t\t0x0\n+\t\t\tMX27_PAD_NFWE_B__NFWE_B\t\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_owire: owiregrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_RTCK__OWIRE\t\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_owire: owiregrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_RTCK__OWIRE\t\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_sdhc2: sdhc2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD2_CLK__SD2_CLK\t\t0x0\n-\t\t\t\tMX27_PAD_SD2_CMD__SD2_CMD\t\t0x0\n-\t\t\t\tMX27_PAD_SD2_D0__SD2_D0\t\t\t0x0\n-\t\t\t\tMX27_PAD_SD2_D1__SD2_D1\t\t\t0x0\n-\t\t\t\tMX27_PAD_SD2_D2__SD2_D2\t\t\t0x0\n-\t\t\t\tMX27_PAD_SD2_D3__SD2_D3\t\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_sdhc2: sdhc2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD2_CLK__SD2_CLK\t\t0x0\n+\t\t\tMX27_PAD_SD2_CMD__SD2_CMD\t\t0x0\n+\t\t\tMX27_PAD_SD2_D0__SD2_D0\t\t\t0x0\n+\t\t\tMX27_PAD_SD2_D1__SD2_D1\t\t\t0x0\n+\t\t\tMX27_PAD_SD2_D2__SD2_D2\t\t\t0x0\n+\t\t\tMX27_PAD_SD2_D3__SD2_D3\t\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart4: uart4grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH1_TXDM__UART4_TXD\t\t0x0\n-\t\t\t\tMX27_PAD_USBH1_RXDP__UART4_RXD\t\t0x0\n-\t\t\t\tMX27_PAD_USBH1_TXDP__UART4_CTS\t\t0x0\n-\t\t\t\tMX27_PAD_USBH1_FS__UART4_RTS\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart4: uart4grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH1_TXDM__UART4_TXD\t\t0x0\n+\t\t\tMX27_PAD_USBH1_RXDP__UART4_RXD\t\t0x0\n+\t\t\tMX27_PAD_USBH1_TXDP__UART4_CTS\t\t0x0\n+\t\t\tMX27_PAD_USBH1_FS__UART4_RTS\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart8250_1: uart82501grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USB_PWR__GPIO2_23\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart8250_1: uart82501grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USB_PWR__GPIO2_23\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart8250_2: uart82502grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH1_SUSP__GPIO2_22\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart8250_2: uart82502grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH1_SUSP__GPIO2_22\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart8250_3: uart82503grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH1_OE_B__GPIO2_27\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart8250_3: uart82503grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH1_OE_B__GPIO2_27\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart8250_4: uart82504grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH1_RXDM__GPIO2_30\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart8250_4: uart82504grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH1_RXDM__GPIO2_30\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_usbh2: usbh2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH2_CLK__USBH2_CLK\t\t0x0\n-\t\t\t\tMX27_PAD_USBH2_DIR__USBH2_DIR\t\t0x0\n-\t\t\t\tMX27_PAD_USBH2_NXT__USBH2_NXT\t\t0x0\n-\t\t\t\tMX27_PAD_USBH2_STP__USBH2_STP\t\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_SCLK__USBH2_DATA0\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_MOSI__USBH2_DATA1\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_MISO__USBH2_DATA2\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS1__USBH2_DATA3\t\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS2__USBH2_DATA4\t\t0x0\n-\t\t\t\tMX27_PAD_CSPI1_SS2__USBH2_DATA5\t\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS0__USBH2_DATA6\t\t0x0\n-\t\t\t\tMX27_PAD_USBH2_DATA7__USBH2_DATA7\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_usbh2: usbh2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH2_CLK__USBH2_CLK\t\t0x0\n+\t\t\tMX27_PAD_USBH2_DIR__USBH2_DIR\t\t0x0\n+\t\t\tMX27_PAD_USBH2_NXT__USBH2_NXT\t\t0x0\n+\t\t\tMX27_PAD_USBH2_STP__USBH2_STP\t\t0x0\n+\t\t\tMX27_PAD_CSPI2_SCLK__USBH2_DATA0\t0x0\n+\t\t\tMX27_PAD_CSPI2_MOSI__USBH2_DATA1\t0x0\n+\t\t\tMX27_PAD_CSPI2_MISO__USBH2_DATA2\t0x0\n+\t\t\tMX27_PAD_CSPI2_SS1__USBH2_DATA3\t\t0x0\n+\t\t\tMX27_PAD_CSPI2_SS2__USBH2_DATA4\t\t0x0\n+\t\t\tMX27_PAD_CSPI1_SS2__USBH2_DATA5\t\t0x0\n+\t\t\tMX27_PAD_CSPI2_SS0__USBH2_DATA6\t\t0x0\n+\t\t\tMX27_PAD_USBH2_DATA7__USBH2_DATA7\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_usbotg: usbotggrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBOTG_CLK__USBOTG_CLK\t\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DIR__USBOTG_DIR\t\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_NXT__USBOTG_NXT\t\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_STP__USBOTG_STP\t\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA0__USBOTG_DATA0\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA1__USBOTG_DATA1\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA2__USBOTG_DATA2\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA3__USBOTG_DATA3\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA4__USBOTG_DATA4\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA5__USBOTG_DATA5\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA6__USBOTG_DATA6\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA7__USBOTG_DATA7\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_usbotg: usbotggrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBOTG_CLK__USBOTG_CLK\t\t0x0\n+\t\t\tMX27_PAD_USBOTG_DIR__USBOTG_DIR\t\t0x0\n+\t\t\tMX27_PAD_USBOTG_NXT__USBOTG_NXT\t\t0x0\n+\t\t\tMX27_PAD_USBOTG_STP__USBOTG_STP\t\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA0__USBOTG_DATA0\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA1__USBOTG_DATA1\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA2__USBOTG_DATA2\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA3__USBOTG_DATA3\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA4__USBOTG_DATA4\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA5__USBOTG_DATA5\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA6__USBOTG_DATA6\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA7__USBOTG_DATA7\t0x0\n+\t\t>;\n \t};\n };\ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts\nindex d78793601306cff9f353fa8814a645e5305dd4c4..1c834f2f5068d16174c086c1fe540ff371444675 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts\n@@ -147,113 +147,111 @@ &uart3 {\n };\n \n &iomuxc {\n-\timx27-eukrea-cpuimx27-baseboard {\n-\t\tpinctrl_cspi1: cspi1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CSPI1_MISO__CSPI1_MISO\t0x0\n-\t\t\t\tMX27_PAD_CSPI1_MOSI__CSPI1_MOSI\t0x0\n-\t\t\t\tMX27_PAD_CSPI1_SCLK__CSPI1_SCLK\t0x0\n-\t\t\t\tMX27_PAD_CSPI1_SS0__GPIO4_28\t0x0 /* CS0 */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_cspi1: cspi1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CSPI1_MISO__CSPI1_MISO\t0x0\n+\t\t\tMX27_PAD_CSPI1_MOSI__CSPI1_MOSI\t0x0\n+\t\t\tMX27_PAD_CSPI1_SCLK__CSPI1_SCLK\t0x0\n+\t\t\tMX27_PAD_CSPI1_SS0__GPIO4_28\t0x0 /* CS0 */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_backlight: backlightgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_PWMO__GPIO5_5\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_backlight: backlightgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_PWMO__GPIO5_5\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_gpioleds: gpioledsgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_PC_PWRON__GPIO6_16\t0x0\n-\t\t\t\tMX27_PAD_PC_CD2_B__GPIO6_19\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_gpioleds: gpioledsgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_PC_PWRON__GPIO6_16\t0x0\n+\t\t\tMX27_PAD_PC_CD2_B__GPIO6_19\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_imxfb: imxfbgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_LD0__LD0\t\t0x0\n-\t\t\t\tMX27_PAD_LD1__LD1\t\t0x0\n-\t\t\t\tMX27_PAD_LD2__LD2\t\t0x0\n-\t\t\t\tMX27_PAD_LD3__LD3\t\t0x0\n-\t\t\t\tMX27_PAD_LD4__LD4\t\t0x0\n-\t\t\t\tMX27_PAD_LD5__LD5\t\t0x0\n-\t\t\t\tMX27_PAD_LD6__LD6\t\t0x0\n-\t\t\t\tMX27_PAD_LD7__LD7\t\t0x0\n-\t\t\t\tMX27_PAD_LD8__LD8\t\t0x0\n-\t\t\t\tMX27_PAD_LD9__LD9\t\t0x0\n-\t\t\t\tMX27_PAD_LD10__LD10\t\t0x0\n-\t\t\t\tMX27_PAD_LD11__LD11\t\t0x0\n-\t\t\t\tMX27_PAD_LD12__LD12\t\t0x0\n-\t\t\t\tMX27_PAD_LD13__LD13\t\t0x0\n-\t\t\t\tMX27_PAD_LD14__LD14\t\t0x0\n-\t\t\t\tMX27_PAD_LD15__LD15\t\t0x0\n-\t\t\t\tMX27_PAD_LD16__LD16\t\t0x0\n-\t\t\t\tMX27_PAD_LD17__LD17\t\t0x0\n-\t\t\t\tMX27_PAD_CONTRAST__CONTRAST\t0x0\n-\t\t\t\tMX27_PAD_OE_ACD__OE_ACD\t\t0x0\n-\t\t\t\tMX27_PAD_HSYNC__HSYNC\t\t0x0\n-\t\t\t\tMX27_PAD_VSYNC__VSYNC\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_imxfb: imxfbgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_LD0__LD0\t\t0x0\n+\t\t\tMX27_PAD_LD1__LD1\t\t0x0\n+\t\t\tMX27_PAD_LD2__LD2\t\t0x0\n+\t\t\tMX27_PAD_LD3__LD3\t\t0x0\n+\t\t\tMX27_PAD_LD4__LD4\t\t0x0\n+\t\t\tMX27_PAD_LD5__LD5\t\t0x0\n+\t\t\tMX27_PAD_LD6__LD6\t\t0x0\n+\t\t\tMX27_PAD_LD7__LD7\t\t0x0\n+\t\t\tMX27_PAD_LD8__LD8\t\t0x0\n+\t\t\tMX27_PAD_LD9__LD9\t\t0x0\n+\t\t\tMX27_PAD_LD10__LD10\t\t0x0\n+\t\t\tMX27_PAD_LD11__LD11\t\t0x0\n+\t\t\tMX27_PAD_LD12__LD12\t\t0x0\n+\t\t\tMX27_PAD_LD13__LD13\t\t0x0\n+\t\t\tMX27_PAD_LD14__LD14\t\t0x0\n+\t\t\tMX27_PAD_LD15__LD15\t\t0x0\n+\t\t\tMX27_PAD_LD16__LD16\t\t0x0\n+\t\t\tMX27_PAD_LD17__LD17\t\t0x0\n+\t\t\tMX27_PAD_CONTRAST__CONTRAST\t0x0\n+\t\t\tMX27_PAD_OE_ACD__OE_ACD\t\t0x0\n+\t\t\tMX27_PAD_HSYNC__HSYNC\t\t0x0\n+\t\t\tMX27_PAD_VSYNC__VSYNC\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_lcdreg: lcdreggrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CLS__GPIO1_25\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_lcdreg: lcdreggrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CLS__GPIO1_25\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_sdhc1: sdhc1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD1_CLK__SD1_CLK\t0x0\n-\t\t\t\tMX27_PAD_SD1_CMD__SD1_CMD\t0x0\n-\t\t\t\tMX27_PAD_SD1_D0__SD1_D0\t\t0x0\n-\t\t\t\tMX27_PAD_SD1_D1__SD1_D1\t\t0x0\n-\t\t\t\tMX27_PAD_SD1_D2__SD1_D2\t\t0x0\n-\t\t\t\tMX27_PAD_SD1_D3__SD1_D3\t\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_sdhc1: sdhc1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD1_CLK__SD1_CLK\t0x0\n+\t\t\tMX27_PAD_SD1_CMD__SD1_CMD\t0x0\n+\t\t\tMX27_PAD_SD1_D0__SD1_D0\t\t0x0\n+\t\t\tMX27_PAD_SD1_D1__SD1_D1\t\t0x0\n+\t\t\tMX27_PAD_SD1_D2__SD1_D2\t\t0x0\n+\t\t\tMX27_PAD_SD1_D3__SD1_D3\t\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_ssi1: ssi1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SSI4_CLK__SSI4_CLK\t0x0\n-\t\t\t\tMX27_PAD_SSI4_FS__SSI4_FS\t0x0\n-\t\t\t\tMX27_PAD_SSI4_RXDAT__SSI4_RXDAT\t0x1\n-\t\t\t\tMX27_PAD_SSI4_TXDAT__SSI4_TXDAT\t0x1\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_ssi1: ssi1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SSI4_CLK__SSI4_CLK\t0x0\n+\t\t\tMX27_PAD_SSI4_FS__SSI4_FS\t0x0\n+\t\t\tMX27_PAD_SSI4_RXDAT__SSI4_RXDAT\t0x1\n+\t\t\tMX27_PAD_SSI4_TXDAT__SSI4_TXDAT\t0x1\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_touch: touchgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CSPI1_RDY__GPIO4_25\t0x0 /* IRQ */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_touch: touchgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CSPI1_RDY__GPIO4_25\t0x0 /* IRQ */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART1_TXD__UART1_TXD\t0x0\n-\t\t\t\tMX27_PAD_UART1_RXD__UART1_RXD\t0x0\n-\t\t\t\tMX27_PAD_UART1_CTS__UART1_CTS\t0x0\n-\t\t\t\tMX27_PAD_UART1_RTS__UART1_RTS\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART1_TXD__UART1_TXD\t0x0\n+\t\t\tMX27_PAD_UART1_RXD__UART1_RXD\t0x0\n+\t\t\tMX27_PAD_UART1_CTS__UART1_CTS\t0x0\n+\t\t\tMX27_PAD_UART1_RTS__UART1_RTS\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart2: uart2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART2_TXD__UART2_TXD\t0x0\n-\t\t\t\tMX27_PAD_UART2_RXD__UART2_RXD\t0x0\n-\t\t\t\tMX27_PAD_UART2_CTS__UART2_CTS\t0x0\n-\t\t\t\tMX27_PAD_UART2_RTS__UART2_RTS\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart2: uart2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART2_TXD__UART2_TXD\t0x0\n+\t\t\tMX27_PAD_UART2_RXD__UART2_RXD\t0x0\n+\t\t\tMX27_PAD_UART2_CTS__UART2_CTS\t0x0\n+\t\t\tMX27_PAD_UART2_RTS__UART2_RTS\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart3: uart3grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART3_TXD__UART3_TXD\t0x0\n-\t\t\t\tMX27_PAD_UART3_RXD__UART3_RXD\t0x0\n-\t\t\t\tMX27_PAD_UART3_CTS__UART3_CTS\t0x0\n-\t\t\t\tMX27_PAD_UART3_RTS__UART3_RTS\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart3: uart3grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART3_TXD__UART3_TXD\t0x0\n+\t\t\tMX27_PAD_UART3_RXD__UART3_RXD\t0x0\n+\t\t\tMX27_PAD_UART3_CTS__UART3_CTS\t0x0\n+\t\t\tMX27_PAD_UART3_RTS__UART3_RTS\t0x0\n+\t\t>;\n \t};\n };\ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts\nindex 21d436972aa47c57f50db2636b23b45b41c02f05..2fc4ea5b9501f4765624b42f8badf013fbcdad6f 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts\n@@ -110,76 +110,74 @@ &usbotg {\n };\n \n &iomuxc {\n-\timx27-pdk {\n-\t\tpinctrl_cspi2: cspi2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0\n-\t\t\t\tMX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0\n-\t\t\t\tMX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS0__GPIO4_21\t0x0 /* SPI2 CS0 */\n-\t\t\t\tMX27_PAD_TOUT__GPIO3_14\t\t0x0 /* PMIC IRQ */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_cspi2: cspi2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0\n+\t\t\tMX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0\n+\t\t\tMX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0\n+\t\t\tMX27_PAD_CSPI2_SS0__GPIO4_21\t0x0 /* SPI2 CS0 */\n+\t\t\tMX27_PAD_TOUT__GPIO3_14\t\t0x0 /* PMIC IRQ */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_fec: fecgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0 0x0\n-\t\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA13__FEC_COL 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_fec: fecgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0 0x0\n+\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1 0x0\n+\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2 0x0\n+\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3 0x0\n+\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER 0x0\n+\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1 0x0\n+\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2 0x0\n+\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3 0x0\n+\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO 0x0\n+\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC 0x0\n+\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS 0x0\n+\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0\n+\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0 0x0\n+\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV 0x0\n+\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0\n+\t\t\tMX27_PAD_ATA_DATA13__FEC_COL 0x0\n+\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER 0x0\n+\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_nand: nandgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_NFRB__NFRB\t0x0\n-\t\t\t\tMX27_PAD_NFCLE__NFCLE\t0x0\n-\t\t\t\tMX27_PAD_NFWP_B__NFWP_B\t0x0\n-\t\t\t\tMX27_PAD_NFCE_B__NFCE_B\t0x0\n-\t\t\t\tMX27_PAD_NFALE__NFALE\t0x0\n-\t\t\t\tMX27_PAD_NFRE_B__NFRE_B\t0x0\n-\t\t\t\tMX27_PAD_NFWE_B__NFWE_B\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_nand: nandgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_NFRB__NFRB\t0x0\n+\t\t\tMX27_PAD_NFCLE__NFCLE\t0x0\n+\t\t\tMX27_PAD_NFWP_B__NFWP_B\t0x0\n+\t\t\tMX27_PAD_NFCE_B__NFCE_B\t0x0\n+\t\t\tMX27_PAD_NFALE__NFALE\t0x0\n+\t\t\tMX27_PAD_NFRE_B__NFRE_B\t0x0\n+\t\t\tMX27_PAD_NFWE_B__NFWE_B\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART1_TXD__UART1_TXD 0x0\n-\t\t\t\tMX27_PAD_UART1_RXD__UART1_RXD 0x0\n-\t\t\t\tMX27_PAD_UART1_CTS__UART1_CTS 0x0\n-\t\t\t\tMX27_PAD_UART1_RTS__UART1_RTS 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART1_TXD__UART1_TXD 0x0\n+\t\t\tMX27_PAD_UART1_RXD__UART1_RXD 0x0\n+\t\t\tMX27_PAD_UART1_CTS__UART1_CTS 0x0\n+\t\t\tMX27_PAD_UART1_RTS__UART1_RTS 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_usbotg: usbotggrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0\n-\t\t\t\tMX27_PAD_USBOTG_STP__USBOTG_STP 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0\n-\t\t\t\tMX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_usbotg: usbotggrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0\n+\t\t\tMX27_PAD_USBOTG_STP__USBOTG_STP 0x0\n+\t\t\tMX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0\n+\t\t\tMX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0\n+\t\t>;\n \t};\n };\ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts\nindex 27c93b9fe0499fc9438b713086391adf375c04dc..2b884cb3e38184d4524a95419a2bb8d36739dc0e 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts\n@@ -65,58 +65,56 @@ adc@64 {\n };\n \n &iomuxc {\n-\timx27-phycard-s-rdk {\n-\t\tpinctrl_i2c1: i2c1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_I2C_DATA__I2C_DATA 0x0\n-\t\t\t\tMX27_PAD_I2C_CLK__I2C_CLK 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c1: i2c1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_I2C_DATA__I2C_DATA 0x0\n+\t\t\tMX27_PAD_I2C_CLK__I2C_CLK 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_owire1: owire1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_RTCK__OWIRE 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_owire1: owire1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_RTCK__OWIRE 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_sdhc2: sdhc2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD2_CLK__SD2_CLK 0x0\n-\t\t\t\tMX27_PAD_SD2_CMD__SD2_CMD 0x0\n-\t\t\t\tMX27_PAD_SD2_D0__SD2_D0 0x0\n-\t\t\t\tMX27_PAD_SD2_D1__SD2_D1 0x0\n-\t\t\t\tMX27_PAD_SD2_D2__SD2_D2 0x0\n-\t\t\t\tMX27_PAD_SD2_D3__SD2_D3 0x0\n-\t\t\t\tMX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_sdhc2: sdhc2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD2_CLK__SD2_CLK 0x0\n+\t\t\tMX27_PAD_SD2_CMD__SD2_CMD 0x0\n+\t\t\tMX27_PAD_SD2_D0__SD2_D0 0x0\n+\t\t\tMX27_PAD_SD2_D1__SD2_D1 0x0\n+\t\t\tMX27_PAD_SD2_D2__SD2_D2 0x0\n+\t\t\tMX27_PAD_SD2_D3__SD2_D3 0x0\n+\t\t\tMX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART1_TXD__UART1_TXD 0x0\n-\t\t\t\tMX27_PAD_UART1_RXD__UART1_RXD 0x0\n-\t\t\t\tMX27_PAD_UART1_CTS__UART1_CTS 0x0\n-\t\t\t\tMX27_PAD_UART1_RTS__UART1_RTS 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART1_TXD__UART1_TXD 0x0\n+\t\t\tMX27_PAD_UART1_RXD__UART1_RXD 0x0\n+\t\t\tMX27_PAD_UART1_CTS__UART1_CTS 0x0\n+\t\t\tMX27_PAD_UART1_RTS__UART1_RTS 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart2: uart2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART2_TXD__UART2_TXD 0x0\n-\t\t\t\tMX27_PAD_UART2_RXD__UART2_RXD 0x0\n-\t\t\t\tMX27_PAD_UART2_CTS__UART2_CTS 0x0\n-\t\t\t\tMX27_PAD_UART2_RTS__UART2_RTS 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart2: uart2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART2_TXD__UART2_TXD 0x0\n+\t\t\tMX27_PAD_UART2_RXD__UART2_RXD 0x0\n+\t\t\tMX27_PAD_UART2_CTS__UART2_CTS 0x0\n+\t\t\tMX27_PAD_UART2_RTS__UART2_RTS 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart3: uart3grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART3_TXD__UART3_TXD 0x0\n-\t\t\t\tMX27_PAD_UART3_RXD__UART3_RXD 0x0\n-\t\t\t\tMX27_PAD_UART3_CTS__UART3_CTS 0x0\n-\t\t\t\tMX27_PAD_UART3_RTS__UART3_RTS 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart3: uart3grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART3_TXD__UART3_TXD 0x0\n+\t\t\tMX27_PAD_UART3_RXD__UART3_RXD 0x0\n+\t\t\tMX27_PAD_UART3_CTS__UART3_CTS 0x0\n+\t\t\tMX27_PAD_UART3_RTS__UART3_RTS 0x0\n+\t\t>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi\nindex 31b3fc972abbfc585c1c65eb10e006c89561dce2..2f60b3809f39b2f2c92cdb6a61664103380e3478 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi\n@@ -58,94 +58,92 @@ eeprom@52 {\n };\n \n &iomuxc {\n-\timx27-phycard-s-som {\n-\t\tpinctrl_fec1: fec1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0 0x0\n-\t\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA13__FEC_COL 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN 0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_i2c2: i2c2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_I2C2_SDA__I2C2_SDA 0x0\n-\t\t\t\tMX27_PAD_I2C2_SCL__I2C2_SCL 0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_nfc: nfcgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_NFRB__NFRB 0x0\n-\t\t\t\tMX27_PAD_NFCLE__NFCLE 0x0\n-\t\t\t\tMX27_PAD_NFWP_B__NFWP_B 0x0\n-\t\t\t\tMX27_PAD_NFCE_B__NFCE_B 0x0\n-\t\t\t\tMX27_PAD_NFALE__NFALE 0x0\n-\t\t\t\tMX27_PAD_NFRE_B__NFRE_B 0x0\n-\t\t\t\tMX27_PAD_NFWE_B__NFWE_B 0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_usbotgphy: usbotgphygrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH1_RCV__GPIO2_25\t\t0x1 /* reset gpio */\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_usbotg: usbotggrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBOTG_CLK__USBOTG_CLK\t\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DIR__USBOTG_DIR\t\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_NXT__USBOTG_NXT\t\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_STP__USBOTG_STP\t\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA0__USBOTG_DATA0\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA1__USBOTG_DATA1\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA2__USBOTG_DATA2\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA3__USBOTG_DATA3\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA4__USBOTG_DATA4\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA5__USBOTG_DATA5\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA6__USBOTG_DATA6\t0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA7__USBOTG_DATA7\t0x0\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_usbh2phy: usbh2phygrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH1_SUSP__GPIO2_22\t\t0x0 /* reset gpio */\n-\t\t\t>;\n-\t\t};\n-\n-\t\tpinctrl_usbh2: usbh2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH2_CLK__USBH2_CLK\t\t0x0\n-\t\t\t\tMX27_PAD_USBH2_DIR__USBH2_DIR\t\t0x0\n-\t\t\t\tMX27_PAD_USBH2_NXT__USBH2_NXT\t\t0x0\n-\t\t\t\tMX27_PAD_USBH2_STP__USBH2_STP\t\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_SCLK__USBH2_DATA0\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_MOSI__USBH2_DATA1\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_MISO__USBH2_DATA2\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS1__USBH2_DATA3\t\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS2__USBH2_DATA4\t\t0x0\n-\t\t\t\tMX27_PAD_CSPI1_SS2__USBH2_DATA5\t\t0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS0__USBH2_DATA6\t\t0x0\n-\t\t\t\tMX27_PAD_USBH2_DATA7__USBH2_DATA7\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_fec1: fec1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0 0x0\n+\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1 0x0\n+\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2 0x0\n+\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3 0x0\n+\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER 0x0\n+\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1 0x0\n+\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2 0x0\n+\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3 0x0\n+\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO 0x0\n+\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC 0x0\n+\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS 0x0\n+\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0\n+\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0 0x0\n+\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV 0x0\n+\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0\n+\t\t\tMX27_PAD_ATA_DATA13__FEC_COL 0x0\n+\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER 0x0\n+\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN 0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_i2c2: i2c2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_I2C2_SDA__I2C2_SDA 0x0\n+\t\t\tMX27_PAD_I2C2_SCL__I2C2_SCL 0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_nfc: nfcgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_NFRB__NFRB 0x0\n+\t\t\tMX27_PAD_NFCLE__NFCLE 0x0\n+\t\t\tMX27_PAD_NFWP_B__NFWP_B 0x0\n+\t\t\tMX27_PAD_NFCE_B__NFCE_B 0x0\n+\t\t\tMX27_PAD_NFALE__NFALE 0x0\n+\t\t\tMX27_PAD_NFRE_B__NFRE_B 0x0\n+\t\t\tMX27_PAD_NFWE_B__NFWE_B 0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usbotgphy: usbotgphygrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH1_RCV__GPIO2_25\t\t0x1 /* reset gpio */\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usbotg: usbotggrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBOTG_CLK__USBOTG_CLK\t\t0x0\n+\t\t\tMX27_PAD_USBOTG_DIR__USBOTG_DIR\t\t0x0\n+\t\t\tMX27_PAD_USBOTG_NXT__USBOTG_NXT\t\t0x0\n+\t\t\tMX27_PAD_USBOTG_STP__USBOTG_STP\t\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA0__USBOTG_DATA0\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA1__USBOTG_DATA1\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA2__USBOTG_DATA2\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA3__USBOTG_DATA3\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA4__USBOTG_DATA4\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA5__USBOTG_DATA5\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA6__USBOTG_DATA6\t0x0\n+\t\t\tMX27_PAD_USBOTG_DATA7__USBOTG_DATA7\t0x0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usbh2phy: usbh2phygrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH1_SUSP__GPIO2_22\t\t0x0 /* reset gpio */\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usbh2: usbh2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH2_CLK__USBH2_CLK\t\t0x0\n+\t\t\tMX27_PAD_USBH2_DIR__USBH2_DIR\t\t0x0\n+\t\t\tMX27_PAD_USBH2_NXT__USBH2_NXT\t\t0x0\n+\t\t\tMX27_PAD_USBH2_STP__USBH2_STP\t\t0x0\n+\t\t\tMX27_PAD_CSPI2_SCLK__USBH2_DATA0\t0x0\n+\t\t\tMX27_PAD_CSPI2_MOSI__USBH2_DATA1\t0x0\n+\t\t\tMX27_PAD_CSPI2_MISO__USBH2_DATA2\t0x0\n+\t\t\tMX27_PAD_CSPI2_SS1__USBH2_DATA3\t\t0x0\n+\t\t\tMX27_PAD_CSPI2_SS2__USBH2_DATA4\t\t0x0\n+\t\t\tMX27_PAD_CSPI1_SS2__USBH2_DATA5\t\t0x0\n+\t\t\tMX27_PAD_CSPI2_SS0__USBH2_DATA6\t\t0x0\n+\t\t\tMX27_PAD_USBH2_DATA7__USBH2_DATA7\t0x0\n+\t\t>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts\nindex 5398e9067e60f98663bec70519d719f859d6e2fa..d7136c399ae29e87a6b13d19ae6d7b9b42a28b48 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts\n@@ -89,119 +89,117 @@ camgpio: pca9536@41 {\n };\n \n &iomuxc {\n-\timx27_phycore_rdk {\n-\t\tpinctrl_csien: csiengrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USB_OC_B__GPIO2_24 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_csien: csiengrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USB_OC_B__GPIO2_24 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_cspi1cs1: cspi1cs1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CSPI1_SS1__GPIO4_27 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_cspi1cs1: cspi1cs1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CSPI1_SS1__GPIO4_27 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_imxfb1: imxfbgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_LD0__LD0 0x0\n-\t\t\t\tMX27_PAD_LD1__LD1 0x0\n-\t\t\t\tMX27_PAD_LD2__LD2 0x0\n-\t\t\t\tMX27_PAD_LD3__LD3 0x0\n-\t\t\t\tMX27_PAD_LD4__LD4 0x0\n-\t\t\t\tMX27_PAD_LD5__LD5 0x0\n-\t\t\t\tMX27_PAD_LD6__LD6 0x0\n-\t\t\t\tMX27_PAD_LD7__LD7 0x0\n-\t\t\t\tMX27_PAD_LD8__LD8 0x0\n-\t\t\t\tMX27_PAD_LD9__LD9 0x0\n-\t\t\t\tMX27_PAD_LD10__LD10 0x0\n-\t\t\t\tMX27_PAD_LD11__LD11 0x0\n-\t\t\t\tMX27_PAD_LD12__LD12 0x0\n-\t\t\t\tMX27_PAD_LD13__LD13 0x0\n-\t\t\t\tMX27_PAD_LD14__LD14 0x0\n-\t\t\t\tMX27_PAD_LD15__LD15 0x0\n-\t\t\t\tMX27_PAD_LD16__LD16 0x0\n-\t\t\t\tMX27_PAD_LD17__LD17 0x0\n-\t\t\t\tMX27_PAD_CLS__CLS 0x0\n-\t\t\t\tMX27_PAD_CONTRAST__CONTRAST 0x0\n-\t\t\t\tMX27_PAD_LSCLK__LSCLK 0x0\n-\t\t\t\tMX27_PAD_OE_ACD__OE_ACD 0x0\n-\t\t\t\tMX27_PAD_PS__PS 0x0\n-\t\t\t\tMX27_PAD_REV__REV 0x0\n-\t\t\t\tMX27_PAD_SPL_SPR__SPL_SPR 0x0\n-\t\t\t\tMX27_PAD_HSYNC__HSYNC 0x0\n-\t\t\t\tMX27_PAD_VSYNC__VSYNC 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_imxfb1: imxfbgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_LD0__LD0 0x0\n+\t\t\tMX27_PAD_LD1__LD1 0x0\n+\t\t\tMX27_PAD_LD2__LD2 0x0\n+\t\t\tMX27_PAD_LD3__LD3 0x0\n+\t\t\tMX27_PAD_LD4__LD4 0x0\n+\t\t\tMX27_PAD_LD5__LD5 0x0\n+\t\t\tMX27_PAD_LD6__LD6 0x0\n+\t\t\tMX27_PAD_LD7__LD7 0x0\n+\t\t\tMX27_PAD_LD8__LD8 0x0\n+\t\t\tMX27_PAD_LD9__LD9 0x0\n+\t\t\tMX27_PAD_LD10__LD10 0x0\n+\t\t\tMX27_PAD_LD11__LD11 0x0\n+\t\t\tMX27_PAD_LD12__LD12 0x0\n+\t\t\tMX27_PAD_LD13__LD13 0x0\n+\t\t\tMX27_PAD_LD14__LD14 0x0\n+\t\t\tMX27_PAD_LD15__LD15 0x0\n+\t\t\tMX27_PAD_LD16__LD16 0x0\n+\t\t\tMX27_PAD_LD17__LD17 0x0\n+\t\t\tMX27_PAD_CLS__CLS 0x0\n+\t\t\tMX27_PAD_CONTRAST__CONTRAST 0x0\n+\t\t\tMX27_PAD_LSCLK__LSCLK 0x0\n+\t\t\tMX27_PAD_OE_ACD__OE_ACD 0x0\n+\t\t\tMX27_PAD_PS__PS 0x0\n+\t\t\tMX27_PAD_REV__REV 0x0\n+\t\t\tMX27_PAD_SPL_SPR__SPL_SPR 0x0\n+\t\t\tMX27_PAD_HSYNC__HSYNC 0x0\n+\t\t\tMX27_PAD_VSYNC__VSYNC 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_i2c1: i2c1grp {\n-\t\t\t/* Add pullup to DATA line */\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_I2C_DATA__I2C_DATA\t0x1\n-\t\t\t\tMX27_PAD_I2C_CLK__I2C_CLK\t0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c1: i2c1grp {\n+\t\t/* Add pullup to DATA line */\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_I2C_DATA__I2C_DATA\t0x1\n+\t\t\tMX27_PAD_I2C_CLK__I2C_CLK\t0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_owire1: owire1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_RTCK__OWIRE 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_owire1: owire1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_RTCK__OWIRE 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_sdhc2: sdhc2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD2_CLK__SD2_CLK 0x0\n-\t\t\t\tMX27_PAD_SD2_CMD__SD2_CMD 0x0\n-\t\t\t\tMX27_PAD_SD2_D0__SD2_D0 0x0\n-\t\t\t\tMX27_PAD_SD2_D1__SD2_D1 0x0\n-\t\t\t\tMX27_PAD_SD2_D2__SD2_D2 0x0\n-\t\t\t\tMX27_PAD_SD2_D3__SD2_D3 0x0\n-\t\t\t\tMX27_PAD_SSI3_FS__GPIO3_28\t0x0 /* WP */\n-\t\t\t\tMX27_PAD_SSI3_RXDAT__GPIO3_29\t0x0 /* CD */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_sdhc2: sdhc2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD2_CLK__SD2_CLK 0x0\n+\t\t\tMX27_PAD_SD2_CMD__SD2_CMD 0x0\n+\t\t\tMX27_PAD_SD2_D0__SD2_D0 0x0\n+\t\t\tMX27_PAD_SD2_D1__SD2_D1 0x0\n+\t\t\tMX27_PAD_SD2_D2__SD2_D2 0x0\n+\t\t\tMX27_PAD_SD2_D3__SD2_D3 0x0\n+\t\t\tMX27_PAD_SSI3_FS__GPIO3_28\t0x0 /* WP */\n+\t\t\tMX27_PAD_SSI3_RXDAT__GPIO3_29\t0x0 /* CD */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart1: uart1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART1_TXD__UART1_TXD 0x0\n-\t\t\t\tMX27_PAD_UART1_RXD__UART1_RXD 0x0\n-\t\t\t\tMX27_PAD_UART1_CTS__UART1_CTS 0x0\n-\t\t\t\tMX27_PAD_UART1_RTS__UART1_RTS 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART1_TXD__UART1_TXD 0x0\n+\t\t\tMX27_PAD_UART1_RXD__UART1_RXD 0x0\n+\t\t\tMX27_PAD_UART1_CTS__UART1_CTS 0x0\n+\t\t\tMX27_PAD_UART1_RTS__UART1_RTS 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_uart2: uart2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_UART2_TXD__UART2_TXD 0x0\n-\t\t\t\tMX27_PAD_UART2_RXD__UART2_RXD 0x0\n-\t\t\t\tMX27_PAD_UART2_CTS__UART2_CTS 0x0\n-\t\t\t\tMX27_PAD_UART2_RTS__UART2_RTS 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_uart2: uart2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_UART2_TXD__UART2_TXD 0x0\n+\t\t\tMX27_PAD_UART2_RXD__UART2_RXD 0x0\n+\t\t\tMX27_PAD_UART2_CTS__UART2_CTS 0x0\n+\t\t\tMX27_PAD_UART2_RTS__UART2_RTS 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_usbh2: usbh2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBH2_CLK__USBH2_CLK 0x0\n-\t\t\t\tMX27_PAD_USBH2_DIR__USBH2_DIR 0x0\n-\t\t\t\tMX27_PAD_USBH2_NXT__USBH2_NXT 0x0\n-\t\t\t\tMX27_PAD_USBH2_STP__USBH2_STP 0x0\n-\t\t\t\tMX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0\n-\t\t\t\tMX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0\n-\t\t\t\tMX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0\n-\t\t\t\tMX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0\n-\t\t\t\tMX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0\n-\t\t\t\tMX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_usbh2: usbh2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBH2_CLK__USBH2_CLK 0x0\n+\t\t\tMX27_PAD_USBH2_DIR__USBH2_DIR 0x0\n+\t\t\tMX27_PAD_USBH2_NXT__USBH2_NXT 0x0\n+\t\t\tMX27_PAD_USBH2_STP__USBH2_STP 0x0\n+\t\t\tMX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0\n+\t\t\tMX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0\n+\t\t\tMX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0\n+\t\t\tMX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0\n+\t\t\tMX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0\n+\t\t\tMX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0\n+\t\t\tMX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0\n+\t\t\tMX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_weim: weimgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CS4_B__CS4_B\t\t0x0 /* CS4 */\n-\t\t\t\tMX27_PAD_SD1_D1__GPIO5_19\t0x0 /* CAN IRQ */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_weim: weimgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CS4_B__CS4_B\t\t0x0 /* CS4 */\n+\t\t\tMX27_PAD_SD1_D1__GPIO5_19\t0x0 /* CAN IRQ */\n+\t\t>;\n \t};\n };\n \ndiff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi\nindex e958d7286ae9d397161b2e7404617bf6f75c0182..7d5d24c781b9834dbf8834c798b923829fd98444 100644\n--- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi\n+++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi\n@@ -192,90 +192,88 @@ lm75@4a {\n };\n \n &iomuxc {\n-\timx27_phycore_som {\n-\t\tpinctrl_cspi1: cspi1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0\n-\t\t\t\tMX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0\n-\t\t\t\tMX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0\n-\t\t\t\tMX27_PAD_CSPI1_SS0__GPIO4_28\t0x0 /* SPI1 CS0 */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_cspi1: cspi1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0\n+\t\t\tMX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0\n+\t\t\tMX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0\n+\t\t\tMX27_PAD_CSPI1_SS0__GPIO4_28\t0x0 /* SPI1 CS0 */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_fec1: fec1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0 0x0\n-\t\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA13__FEC_COL 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER 0x0\n-\t\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN 0x0\n-\t\t\t\tMX27_PAD_SSI3_TXDAT__GPIO3_30\t0x0 /* FEC RST */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_fec1: fec1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SD3_CMD__FEC_TXD0 0x0\n+\t\t\tMX27_PAD_SD3_CLK__FEC_TXD1 0x0\n+\t\t\tMX27_PAD_ATA_DATA0__FEC_TXD2 0x0\n+\t\t\tMX27_PAD_ATA_DATA1__FEC_TXD3 0x0\n+\t\t\tMX27_PAD_ATA_DATA2__FEC_RX_ER 0x0\n+\t\t\tMX27_PAD_ATA_DATA3__FEC_RXD1 0x0\n+\t\t\tMX27_PAD_ATA_DATA4__FEC_RXD2 0x0\n+\t\t\tMX27_PAD_ATA_DATA5__FEC_RXD3 0x0\n+\t\t\tMX27_PAD_ATA_DATA6__FEC_MDIO 0x0\n+\t\t\tMX27_PAD_ATA_DATA7__FEC_MDC 0x0\n+\t\t\tMX27_PAD_ATA_DATA8__FEC_CRS 0x0\n+\t\t\tMX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0\n+\t\t\tMX27_PAD_ATA_DATA10__FEC_RXD0 0x0\n+\t\t\tMX27_PAD_ATA_DATA11__FEC_RX_DV 0x0\n+\t\t\tMX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0\n+\t\t\tMX27_PAD_ATA_DATA13__FEC_COL 0x0\n+\t\t\tMX27_PAD_ATA_DATA14__FEC_TX_ER 0x0\n+\t\t\tMX27_PAD_ATA_DATA15__FEC_TX_EN 0x0\n+\t\t\tMX27_PAD_SSI3_TXDAT__GPIO3_30\t0x0 /* FEC RST */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_i2c2: i2c2grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_I2C2_SDA__I2C2_SDA 0x0\n-\t\t\t\tMX27_PAD_I2C2_SCL__I2C2_SCL 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_i2c2: i2c2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_I2C2_SDA__I2C2_SDA 0x0\n+\t\t\tMX27_PAD_I2C2_SCL__I2C2_SCL 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_nfc: nfcgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_NFRB__NFRB 0x0\n-\t\t\t\tMX27_PAD_NFCLE__NFCLE 0x0\n-\t\t\t\tMX27_PAD_NFWP_B__NFWP_B 0x0\n-\t\t\t\tMX27_PAD_NFCE_B__NFCE_B 0x0\n-\t\t\t\tMX27_PAD_NFALE__NFALE 0x0\n-\t\t\t\tMX27_PAD_NFRE_B__NFRE_B 0x0\n-\t\t\t\tMX27_PAD_NFWE_B__NFWE_B 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_nfc: nfcgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_NFRB__NFRB 0x0\n+\t\t\tMX27_PAD_NFCLE__NFCLE 0x0\n+\t\t\tMX27_PAD_NFWP_B__NFWP_B 0x0\n+\t\t\tMX27_PAD_NFCE_B__NFCE_B 0x0\n+\t\t\tMX27_PAD_NFALE__NFALE 0x0\n+\t\t\tMX27_PAD_NFRE_B__NFRE_B 0x0\n+\t\t\tMX27_PAD_NFWE_B__NFWE_B 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_pmic: pmicgrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USB_PWR__GPIO2_23\t0x0 /* PMIC IRQ */\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_pmic: pmicgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USB_PWR__GPIO2_23\t0x0 /* PMIC IRQ */\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_ssi1: ssi1grp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_SSI1_FS__SSI1_FS 0x0\n-\t\t\t\tMX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0\n-\t\t\t\tMX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0\n-\t\t\t\tMX27_PAD_SSI1_CLK__SSI1_CLK 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_ssi1: ssi1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_SSI1_FS__SSI1_FS 0x0\n+\t\t\tMX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0\n+\t\t\tMX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0\n+\t\t\tMX27_PAD_SSI1_CLK__SSI1_CLK 0x0\n+\t\t>;\n+\t};\n \n-\t\tpinctrl_usbotg: usbotggrp {\n-\t\t\tfsl,pins = <\n-\t\t\t\tMX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0\n-\t\t\t\tMX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0\n-\t\t\t\tMX27_PAD_USBOTG_STP__USBOTG_STP 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0\n-\t\t\t\tMX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0\n-\t\t\t>;\n-\t\t};\n+\tpinctrl_usbotg: usbotggrp {\n+\t\tfsl,pins = <\n+\t\t\tMX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0\n+\t\t\tMX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0\n+\t\t\tMX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0\n+\t\t\tMX27_PAD_USBOTG_STP__USBOTG_STP 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0\n+\t\t\tMX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0\n+\t\t>;\n \t};\n };\n \n",
    "prefixes": [
        "4/4"
    ]
}