Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2195739,
    "url": "http://patchwork.ozlabs.org/api/patches/2195739/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260211182230.968921-8-mikhail.kshevetskiy@iopsys.eu/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260211182230.968921-8-mikhail.kshevetskiy@iopsys.eu>",
    "list_archive_url": null,
    "date": "2026-02-11T18:22:21",
    "name": "[v2,07/16] net: airoha: add support for Airoha PCS driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "1a35e0b95dcaa698abce69088198e0dcf6807eae",
    "submitter": {
        "id": 84987,
        "url": "http://patchwork.ozlabs.org/api/people/84987/?format=api",
        "name": "Mikhail Kshevetskiy",
        "email": "mikhail.kshevetskiy@iopsys.eu"
    },
    "delegate": {
        "id": 157425,
        "url": "http://patchwork.ozlabs.org/api/users/157425/?format=api",
        "username": "jforissier",
        "first_name": "Jerome",
        "last_name": "Forissier",
        "email": "jerome.forissier@linaro.org"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260211182230.968921-8-mikhail.kshevetskiy@iopsys.eu/mbox/",
    "series": [
        {
            "id": 491892,
            "url": "http://patchwork.ozlabs.org/api/series/491892/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491892",
            "date": "2026-02-11T18:22:15",
            "name": "net: airoha: PCS and MDIO support for Airoha AN7581 SoC",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/491892/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2195739/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2195739/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@legolas.ozlabs.org",
        "Authentication-Results": [
            "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=iopsys.eu header.i=@iopsys.eu header.a=rsa-sha256\n header.s=selector1 header.b=jS0Qee5r;\n\tdkim-atps=neutral",
            "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)",
            "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=iopsys.eu",
            "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de",
            "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=iopsys.eu header.i=@iopsys.eu header.b=\"jS0Qee5r\";\n\tdkim-atps=neutral",
            "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=iopsys.eu",
            "phobos.denx.de;\n spf=pass smtp.mailfrom=mikhail.kshevetskiy@genexis.eu",
            "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=iopsys.eu;"
        ],
        "Received": [
            "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fB6Jn4MRCz1xtV\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 12 Feb 2026 05:24:09 +1100 (AEDT)",
            "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id C027E8367F;\n\tWed, 11 Feb 2026 19:23:19 +0100 (CET)",
            "by phobos.denx.de (Postfix, from userid 109)\n id 6AEFB8367F; Wed, 11 Feb 2026 19:23:18 +0100 (CET)",
            "from AS8PR04CU009.outbound.protection.outlook.com\n (mail-westeuropeazlp170110003.outbound.protection.outlook.com\n [IPv6:2a01:111:f403:c201::3])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 60C9A83E13\n for <u-boot@lists.denx.de>; Wed, 11 Feb 2026 19:23:13 +0100 (CET)",
            "from DU2PR08MB10037.eurprd08.prod.outlook.com (2603:10a6:10:49a::20)\n by GV1PR08MB8572.eurprd08.prod.outlook.com (2603:10a6:150:84::10)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9611.10; Wed, 11 Feb\n 2026 18:23:10 +0000",
            "from DU2PR08MB10037.eurprd08.prod.outlook.com\n ([fe80::3c7:6d2e:8afe:e4dc]) by DU2PR08MB10037.eurprd08.prod.outlook.com\n ([fe80::3c7:6d2e:8afe:e4dc%4]) with mapi id 15.20.9587.010; Wed, 11 Feb 2026\n 18:23:10 +0000"
        ],
        "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de",
        "X-Spam-Level": "",
        "X-Spam-Status": "No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,\n RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,UPPERCASE_50_75\n autolearn=no autolearn_force=no version=3.4.2",
        "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=hYh/zjFIq9F4w11SEvwJUWL6oYFrjEw1w7/+awpzrDlhfnZXf1MCg5xe+v1xVI4xj2hHdEfSy8vV6Fomv9yb6fWZ6wlE1BPl+X16it1VD0M/JD5HSwKWk05iCp+xjxLNqfX84Twu0OlRIaxOnavXspYehJuGPyajvlDR28y+cxOCOK13dKnM6if3WjDptrYjkzOEwSDKMShZnsQ9QtJlU/cMOaG4g9nOiyslaiSwqoEx4KU5yqI36rYgT7RjR5lx5nrGcTFi+hQqUdugQKqJwH3iO9fNsaQ5Wt+vKMr0er1cRFsE5Bs1osRahS9oLGjgWxQYnptFfClrHNmJxwFGRw==",
        "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=cDYITf06ZTyVDJ3101+2IV7z/ANl0/R3jI8hwu73Zd0=;\n b=sGf8Dk1CbEKW7MhDRFgtbejFY/YFqgahqrFBSUPnijyMTrw8DNwsh33kZ0i7QnufGXIxCUd+U4ir2LXTbyUWnTaI9BQcLNtTTCzi1wAumNFpNcFmbaJdwGR9aP7OddrSMWUPyryLvh3yIb9SXc5+aReZ59ds5S3XvzU99F3dRxU9z4tUITYW9wsPbujq4umuVBVhIyVshttgsF2nBU4CZEZNcvB9On/kICj/oJMmnF2TBUKUyKp6/F46GYddpsK2s5mkMBtdvRv8InwSlj1YXqAkTdPW7FF04KJ1KDabOzMwFM9GSNIpSoRFRV1P9BSDZQj2RwNOn7PUpYZtuVfcbg==",
        "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=genexis.eu; dmarc=pass action=none header.from=iopsys.eu;\n dkim=pass header.d=iopsys.eu; arc=none",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=iopsys.eu;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=cDYITf06ZTyVDJ3101+2IV7z/ANl0/R3jI8hwu73Zd0=;\n b=jS0Qee5r/xTJbMc6nVTbZXFF9keYHbP7NGD7tnNTRjVJTXxqa1lK98GOzAGE+zLqfnoZ7Xv5NSPujXGol5tzjfgNN+IJjA1UUmLjfeWCRtxujCxAe197QWbLlE+a7+iCzuGNEu94h32f1k+eHadS2cq0rWQH4YajU2fUGPqXj42v+kIC7OlNFW1lHZDaMvzIEl4xENtYPPuioVORmYe2P+0UQz1uBBymvW4CMeMxPFtMs2Ws+Vf92dQzCzTlMuvndhaODNWMK9D1UiTKuJ+S68+6uJnQ6cZWRYGzBDwZbxNyZEZz9+e8g8ASrzPLz+4y3L4Zv0osOjx4Zp7bOyaqUw==",
        "From": "Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>",
        "To": "Tom Rini <trini@konsulko.com>, Christian Marangi <ansuelsmth@gmail.com>,\n Joe Hershberger <joe.hershberger@ni.com>,\n Ramon Fried <rfried.dev@gmail.com>,\n Jerome Forissier <jerome.forissier@arm.com>,\n Ray Liu <ray.xy.liu@gmail.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Paul Barker <paul.barker.ct@bp.renesas.com>,\n Robert Marko <robert.marko@sartura.hr>, Yao Zi <me@ziyao.cc>,\n Greg Malysa <malysagreg@gmail.com>,\n Oliver Gaskell <Oliver.Gaskell@analog.com>,\n Vasileios Bimpikas <vasileios.bimpikas@analog.com>, u-boot@lists.denx.de",
        "Cc": "Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>",
        "Subject": "[PATCH v2 07/16] net: airoha: add support for Airoha PCS driver",
        "Date": "Wed, 11 Feb 2026 21:22:21 +0300",
        "Message-ID": "<20260211182230.968921-8-mikhail.kshevetskiy@iopsys.eu>",
        "X-Mailer": "git-send-email 2.51.0",
        "In-Reply-To": "<20260211182230.968921-1-mikhail.kshevetskiy@iopsys.eu>",
        "References": "<20260211182230.968921-1-mikhail.kshevetskiy@iopsys.eu>",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-ClientProxiedBy": "MI1P293CA0012.ITAP293.PROD.OUTLOOK.COM\n (2603:10a6:290:2::10) To DU2PR08MB10037.eurprd08.prod.outlook.com\n (2603:10a6:10:49a::20)",
        "MIME-Version": "1.0",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-TrafficTypeDiagnostic": "DU2PR08MB10037:EE_|GV1PR08MB8572:EE_",
        "X-MS-Office365-Filtering-Correlation-Id": "a1dddc01-c71b-43b1-7201-08de699a9c3c",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-MS-Exchange-AntiSpam-Relay": "0",
        "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|52116014|7416014|376014|366016|921020|38350700014;",
        "X-Microsoft-Antispam-Message-Info": "\n DWRNAfJoiMm7j1cysVNxlUrUfw9mmEKUE4xFbolR+vVmnYycvQx/b00atxXhuqX8EHijj0fNlW0jxbv54l0MDQBws+vN2UJhRvWEMkOlOGTtq/rlpjh8OmbWVrJFcl6H4MC7R6PV+R+ndLtrOaDcvvcgQOMxEZC1Fkhqi6e7eTVfG+URA+tj5laJkjcAsbtTVF/ZCAG7eD7RrdqPzcycqdKcK9q8LGACiIExxZc/7HTUfOzCrga+h0EG0GmNSo5kLB38T4qyV4QwqoVi9X4Gz3twqvNealIvVz0HIOoT8KbrzTjrSL4uR3pZtx/8yE39o4sSayGbvxqydvHV1B7vphqKeTn/O4qLhrFqAx1GngHUgKME9SJbTQ7eQgcLAohijH+wEao8vAVpaH2eWL9o+aSvZTiRHChZCkMBsF79T3VCl+JzYI0GcQH+uJ5MKrtNWiZ8SF0Wg14GJyLMPU+Ni2Ch5l5DYku0sWjJtD3kyoSYKXN8KovnS5hw7Dtn1j8yZHgQn4h93wMUqyjYMPi4rRTkfdv1SCg9UM4kQ/DOIUlt+ohFQw+R3AUpSyl/ZLrs8+trid8Ray6P4lRkEC5+YmVEHnzy4Z260I5JNVoHTBa5BpcBfQ+AAyOa7i1armHRN6QNVBQ8MfLSe3eB5r4D7weS/s9DysS5sCcx57Mno1/olIdrKxhNIVSq65u8TYLuX2S6OPWwzDTyXelXCjypXt5k9ZrikM3UNHKkP5drDe+YFEU8qj2RRCYe/FJgoG1GHNnVHKwr6JT3Fl2rETehzg+iOE9sKbNRDM1bcYTY8Sx45dAXE0dACHP4RNWRMw16ovGu6g5pb4amLR+9pgfWC3ty1d7ag+Ubrj4YofXNCTOzhisiseBciYhx0s1lkAPyRv7UraizpXz5iPHIMmfQpxgOZKl4cNNXHMW0XcyN5sjJbQL0tIhkxhyiA0lEbbbg42nXdPs7Y4QRyG8elt6j/celWYW4fzRLs6V/mpDnbt8dyAhLI2hKBzIlevcFKP4tF+XMUOq5EdTPBqHTy8lrNSZD1oUqoLsg6XQZvbgQS0PSPbaTqdIwDjW7MXr9yIBPQA8nDX5kdxgZmR+7SuCFz1tYq+HE/q8nGrSxPDYbcS3CMU9q4YbAMVASDhdxgArHOnGtWDhjLBtWCIOGZTTyz2/Jq6W3BG+ii8Ny5INCDfP6V2CV33V8pHxY3u5nLYZ2PeNYT8+OghZ4DqyueInFUDfLssNkN86sJum58B2CNSCZoOIZWNAag9aM56Gt5x+9MygkDx7YDYGUS4/SoVKfnjS06AVuqMBVJLEl0OAwIfj6l2i+cMEKJEjcpgf52DYHCxYv5Y9/vihId7LtzBaweQot17VdBxSSyiLz0pbJwuHk03LZPZMNmivfn45EVhRFlb9Swx6asVIzm43wL+bFABUxsO7PCt2Iy2X/HMJqCi5S7iNAxIwpgd6zaz3MMRw+Rxw9zbs12yqmmadbt8U3wStRrbvzeHR4M+V+rWH/irX4N5r1GMEu7G6avXXBngkxoe+PGw2yS7vZPSjUyCdiSeR+JpaT5SJ7/Zp0FBBTFBl3sGZS3yUoYUTA7+MvJ4Ec2Uwjnx5wYFtH+j2dPDDj06o0tmfUmoCVpgXEUWNdYVE/Pa75aRiP+bBUrvjR1Bzr",
        "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:DU2PR08MB10037.eurprd08.prod.outlook.com; PTR:;\n CAT:NONE;\n SFS:(13230040)(1800799024)(52116014)(7416014)(376014)(366016)(921020)(38350700014);\n DIR:OUT; SFP:1102;",
        "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1",
        "X-MS-Exchange-AntiSpam-MessageData-0": "\n 39L9wpmh6B84b442II/xyZNynmMHlpwRTSbVbKVAtZC+8MS7LUM7M3xXRiCJLCoJFMO2KSA/JLGpHwfrxWR7Fmw1limO8Tu5/IUf2Qgqe8Vx7B2gcHKJ9r5nUnXjl2Menuyh50Wq5VfzSW7L63SGIBgKaVBlEFoA029OR0UwaqN5GmZ6S3ScVl1LoWezKYlQtjVhKELJtNjKLXWxcwt5vUp3ZdXs/utEid11cNE4XcEeaqmCbXrGCnXomFwoKZXQMIxxsIfgxvb3CpFeBHdKDewoBjDDh2mBrBoEHzrURPD5ikE17ns667ma+q4zQj8XW/8h4j/cZK4rJQYwb/THBXGkKA6BYnYl6w49PIB0NsXge4MWjznPMJLtKbh00IrkYpVsCtUAWI+c3YGVUhHee7mCvSHfeXKrKs6V4X6u3Ai/LTaixtsQu8GnjMevEcbk5UPZxREiw1KTRzIVj/vyseA1zY2Vy5LMU0Bsl+E5WMZnSJuwguUdUaiEJto3jpIVYH5JpCExRP+lkG7snnXHbxkwA3y0SHNgyyJThfAnpoMY3IPioJ2cjCBtPoxmbf1G1UcYgqOuQt4X4I3YN2mC6WNwoW8F4e9o4Ep5BiFzTV5fIGy1LKvLjE9by3MAxDS9kwKG6OoOp4OHHvK9phKiVDnOfT2vt1KxBuhFtDnc7LhaIs+snEyBOfoZu8MeflblXBddA15GT5KVp0Adox+urGFhHffUHRhz1jcq9gzBNHui3Rfyi1oFhkbcDOU5/MNlZ4LX/ZQu/0UuuWFX3BZ0/IAHZ235wywvq3oZ1YSc/hborOD1bHTpY4XNIJvakT4noNHiomAjrtxNX2clZQfxJYc8/Ak0LFKIb14T91m1joB0jVA/QC2SX5ntO8TPii+eyWttx781EyrRZN7ynyIGHEgW3qTMio9gEkLWfaZmq+L7h8tGaNCElQNhAAIMhZGNYCaTLeMg/hdICVo0fia/9GhggSYLls4VfE2dy+e0fCRInmL0j53F4Hjf2HG8kiu9rqYCl7HZhYbuyvDVjHBNiPkoGM9IMVoGOv2TRhCT3I2Z5pdY0mi0n1GeRk8PtexlvlViAFNTfv5M4Jt99dpJx/3VPrCsKDAo83imMOiWWnWumj9B8JBW+TSAv8KmHK5v4f7UxCmbdyhnpDdfo6A2XP9wb4zncLC7RCgnKTjJBZr1Rfi4owcMBqEIsFLYvSE+QhZtaPJxTExz2TKcwPGgBrGN8McViNViUokuM7thTiEsV8CGTZEkXZOSdv0EUtf3oQ6yoY1OipMqx+ub463CMQFRehVs+ObbhTrRJ5EvlPmfSau3kqSX9LpOr4aE0wQCqryRqBKWUlcpMAbljZKpHT08BdywziLQkxo1DPW2t5DAT9/9c6gPNnKtoNuVqpExNGsOudb0Xjc9uaXv5O6qD7INcR3fRHeHkYjO9xJX8/s43hspzQna2Kxv/AYme9BMx2GI/7RmG7qUf9xf3E7MJKW2Zt7+Bx1ccxlq/8vFubAoBocjJdmIFAPopUaXIGZhl94PLhUfLgTVED0R4up2CEbg/Drmpii96HmlVqBOZvFq8fScBp1n9xHghGf/yyoRrXagefFD4kl1I7ZNPoyIaFU5zhPZjaJOnXelxOnutCIfeyYds5OFF2WRPXzVSxZtolTHVmsvH3d0ZObP6qlKs/zV48Qs4Rh7Pm4ahHV42PujHODBfDj08KWnaRgzpiS4zB06ioMae6txxQ+3F9VgPHJpf5GAPExgAeMK7HRLp00=",
        "X-OriginatorOrg": "iopsys.eu",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a1dddc01-c71b-43b1-7201-08de699a9c3c",
        "X-MS-Exchange-CrossTenant-AuthSource": "DU2PR08MB10037.eurprd08.prod.outlook.com",
        "X-MS-Exchange-CrossTenant-AuthAs": "Internal",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "11 Feb 2026 18:23:10.8008 (UTC)",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted",
        "X-MS-Exchange-CrossTenant-Id": "8d891be1-7bce-4216-9a99-bee9de02ba58",
        "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED",
        "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n bIoW86Tk//ozG4jkliQj+zOzyuTLkZvn62ruXw/WOYcqD4za98Qsa4jZ6Vyr8mlwbsvBOxxb5l2ETb/7QNtNEVzzKxrThPwNCKif542cbes=",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "GV1PR08MB8572",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.39",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>",
        "List-Post": "<mailto:u-boot@lists.denx.de>",
        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>",
        "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de",
        "X-Virus-Status": "Clean"
    },
    "content": "From: Christian Marangi <ansuelsmth@gmail.com>\n\nAdd support for Airoha PCS driver present on AN7581 SoC.\nThis is needed to configure the Serdes port for the different PHY mode.\n\nSigned-off-by: Christian Marangi <ansuelsmth@gmail.com>\n---\n drivers/net/Kconfig                    |    2 +\n drivers/net/Makefile                   |    1 +\n drivers/net/airoha/Kconfig             |   12 +\n drivers/net/airoha/Makefile            |    6 +\n drivers/net/airoha/pcs-airoha-common.c |  811 ++++++++++++++\n drivers/net/airoha/pcs-airoha.h        | 1216 +++++++++++++++++++++\n drivers/net/airoha/pcs-an7581.c        | 1369 ++++++++++++++++++++++++\n 7 files changed, 3417 insertions(+)\n create mode 100644 drivers/net/airoha/Kconfig\n create mode 100644 drivers/net/airoha/Makefile\n create mode 100644 drivers/net/airoha/pcs-airoha-common.c\n create mode 100644 drivers/net/airoha/pcs-airoha.h\n create mode 100644 drivers/net/airoha/pcs-an7581.c",
    "diff": "diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig\nindex fce8004e134..8ed6ff2fe3d 100644\n--- a/drivers/net/Kconfig\n+++ b/drivers/net/Kconfig\n@@ -121,6 +121,8 @@ config AG7XXX\n \t  This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is\n \t  present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips.\n \n+source \"drivers/net/airoha/Kconfig\"\n+\n config AIROHA_ETH\n \tbool \"Airoha Ethernet QDMA Driver\"\n \tdepends on ARCH_AIROHA\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex 5bb40480d88..5e90183d090 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -5,6 +5,7 @@\n \n \n obj-$(CONFIG_AG7XXX) += ag7xxx.o\n+obj-y += airoha/\n obj-$(CONFIG_AIROHA_ETH) += airoha_eth.o\n obj-$(CONFIG_ALTERA_TSE) += altera_tse.o\n obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o\ndiff --git a/drivers/net/airoha/Kconfig b/drivers/net/airoha/Kconfig\nnew file mode 100644\nindex 00000000000..8c2d6db92fa\n--- /dev/null\n+++ b/drivers/net/airoha/Kconfig\n@@ -0,0 +1,12 @@\n+# SPDX-License-Identifier: GPL-2.0-only\n+\n+config PCS_AIROHA\n+\tbool\n+\tselect MISC\n+\n+config PCS_AIROHA_AN7581\n+\tbool \"Airoha AN7581 PCS driver\"\n+\tselect PCS_AIROHA\n+\thelp\n+\t  This module provides helper to phylink for managing the Airoha\n+\t  AN7581 PCS for SoC Ethernet and PON SERDES.\ndiff --git a/drivers/net/airoha/Makefile b/drivers/net/airoha/Makefile\nnew file mode 100644\nindex 00000000000..27f2969434c\n--- /dev/null\n+++ b/drivers/net/airoha/Makefile\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+obj-y\t\t\t\t+= pcs-airoha-common.o\n+ifdef CONFIG_PCS_AIROHA_AN7581\n+obj-y\t\t\t\t+= pcs-an7581.o\n+endif\ndiff --git a/drivers/net/airoha/pcs-airoha-common.c b/drivers/net/airoha/pcs-airoha-common.c\nnew file mode 100644\nindex 00000000000..8784d92a7a4\n--- /dev/null\n+++ b/drivers/net/airoha/pcs-airoha-common.c\n@@ -0,0 +1,811 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi <ansuelsmth@gmail.com>\n+ */\n+\n+#include <dm.h>\n+#include <dm/devres.h>\n+#include <linux/ethtool.h>\n+#include <net.h>\n+#include <regmap.h>\n+#include <reset.h>\n+#include <syscon.h>\n+\n+#include \"pcs-airoha.h\"\n+\n+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,\n+\t\t\t\t     phy_interface_t interface)\n+{\n+\tu32 xsi_sel;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\txsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\tdefault:\n+\t\txsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;\n+\t}\n+\n+\tregmap_update_bits(priv->scu, AIROHA_SCU_SSR3,\n+\t\t\t   AIROHA_SCU_ETH_XSI_SEL,\n+\t\t\t   xsi_sel);\n+}\n+\n+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,\n+\t\t\t\t     phy_interface_t interface)\n+{\n+\tu32 xsi_sel, wan_sel;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_SGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_HSGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_HSGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\tdefault:\n+\t\twan_sel = AIROHA_SCU_WAN_SEL_USXGMII;\n+\t\txsi_sel = AIROHA_SCU_PON_XSI_USXGMII;\n+\t}\n+\n+\tregmap_update_bits(priv->scu, AIROHA_SCU_SSTR,\n+\t\t\t   AIROHA_SCU_PON_XSI_SEL,\n+\t\t\t   xsi_sel);\n+\n+\tregmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,\n+\t\t\t   AIROHA_SCU_WAN_SEL,\n+\t\t\t   wan_sel);\n+}\n+\n+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,\n+\t\t\t\tphy_interface_t interface)\n+{\n+\tconst struct airoha_pcs_match_data *data = priv->data;\n+\tint ret;\n+\n+\tif (priv->xfi_rst) {\n+\t\tret = reset_assert(priv->xfi_rst);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tswitch (data->port_type) {\n+\tcase AIROHA_PCS_ETH:\n+\t\tairoha_pcs_setup_scu_eth(priv, interface);\n+\t\tbreak;\n+\tcase AIROHA_PCS_PON:\n+\t\tairoha_pcs_setup_scu_pon(priv, interface);\n+\t\tbreak;\n+\t}\n+\n+\tif (priv->xfi_rst) {\n+\t\tret = reset_deassert(priv->xfi_rst);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* TODO better handle reset from MAC */\n+\tret = reset_assert_bulk(&priv->rsts);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = reset_deassert_bulk(&priv->rsts);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv)\n+{\n+\tconst struct airoha_pcs_match_data *data = priv->data;\n+\n+\tregmap_set_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\tAIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\t/* Disable Hibernation */\n+\tif (data->hibernation_workaround)\n+\t\tregmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,\n+\t\t\t\tAIROHA_PCS_USXGMII_SPEED_SEL_H);\n+\n+\t/* FIXME: wait Airoha */\n+\t/* Avoid PCS sending garbage to MAC in some HW revision (E0) */\n+\tif (data->usxgmii_ber_time_fixup)\n+\t\tregmap_write(priv->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);\n+\n+\tif (data->usxgmii_rx_gb_out_vld_tweak)\n+\t\tregmap_clear_bits(priv->usxgmii_pcs, AN7583_PCS_USXGMII_RTL_MODIFIED,\n+\t\t\t\t  AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD);\n+}\n+\n+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv)\n+{\n+\tregmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\t  AIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\tregmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\tAIROHA_PCS_TBI_10B_MODE);\n+}\n+\n+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv)\n+{\n+\tregmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,\n+\t\t\t  AIROHA_PCS_HSGMII_XFI_SEL);\n+\n+\tregmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\tAIROHA_PCS_TBI_10B_MODE);\n+\n+\tregmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,\n+\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));\n+\n+\tregmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,\n+\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));\n+}\n+\n+static void airoha_pcs_init(struct airoha_pcs_priv *priv,\n+\t\t\t    phy_interface_t interface)\n+{\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tairoha_pcs_init_sgmii(priv);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tairoha_pcs_init_hsgmii(priv);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tairoha_pcs_init_usxgmii(priv);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv)\n+{\n+\t/* Disable every interrupt */\n+\tregmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);\n+\n+\t/* Clear interrupt */\n+\tregmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |\n+\t\t\tAIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);\n+\n+\tregmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |\n+\t\t\t  AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);\n+}\n+\n+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv)\n+{\n+\t/* Disable every Interrupt */\n+\tregmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,\n+\t\t\t  AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);\n+\n+\tregmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,\n+\t\t\t  AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);\n+\n+\tregmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,\n+\t\t\t  AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);\n+\n+\tregmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,\n+\t\t\t  AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |\n+\t\t\t  AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);\n+\n+\tregmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,\n+\t\t\t  AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);\n+\n+\t/* Clear any pending interrupt */\n+\tregmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,\n+\t\t\tAIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_E_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_T_INT |\n+\t\t\tAIROHA_PCS_USXGMII_R_TYPE_D_INT);\n+\n+\tregmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,\n+\t\t\tAIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_LINK_UP_ST_INT |\n+\t\t\tAIROHA_PCS_USXGMII_HI_BER_ST_INT);\n+\n+\tregmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,\n+\t\t\tAIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);\n+\n+\t/* Interrupt saddly seems to be not weel supported for Link Down.\n+\t * PCS Poll is a must to correctly read and react on Cable Deatch\n+\t * as only cable attach interrupt are fired and Link Down interrupt\n+\t * are fired only in special case like AN restart.\n+\t */\n+}\n+\n+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,\n+\t\t\t\t      phy_interface_t interface)\n+{\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\treturn airoha_pcs_interrupt_init_sgmii(priv);\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\treturn airoha_pcs_interrupt_init_usxgmii(priv);\n+\tdefault:\n+\t\treturn;\n+\t}\n+}\n+\n+int airoha_pcs_config(struct udevice *dev, bool neg_mode,\n+\t\t      phy_interface_t interface,\n+\t\t      const unsigned long *advertising,\n+\t\t      bool permit_pause_to_mac)\n+{\n+\tstruct airoha_pcs_priv *priv = dev_get_priv(dev);\n+\tconst struct airoha_pcs_match_data *data;\n+\tu32 rate_adapt;\n+\tint ret;\n+\n+\tpriv->interface = interface;\n+\tdata = priv->data;\n+\n+\t/* Apply Analog and Digital configuration for PCS */\n+\tif (data->bringup) {\n+\t\tret = data->bringup(priv, interface);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Set final configuration for various modes */\n+\tairoha_pcs_init(priv, interface);\n+\n+\t/* Configure Interrupt for various modes */\n+\tairoha_pcs_interrupt_init(priv, interface);\n+\n+\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |\n+\t\t     AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;\n+\n+\tif (interface == PHY_INTERFACE_MODE_SGMII)\n+\t\trate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |\n+\t\t\t      AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS;\n+\n+\t/* AN Auto Settings (Rate Adaptation) */\n+\tregmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,\n+\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |\n+\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |\n+\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |\n+\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);\n+\n+\t/* FIXME: With an attached Aeonsemi PHY, AN is needed\n+\t * even with no inband.\n+\t */\n+\tif (interface == PHY_INTERFACE_MODE_USXGMII ||\n+\t    interface == PHY_INTERFACE_MODE_10GBASER) {\n+\t\tif (interface == PHY_INTERFACE_MODE_USXGMII)\n+\t\t\tregmap_set_bits(priv->usxgmii_pcs,\n+\t\t\t\t\tAIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t\tAIROHA_PCS_USXGMII_AN_ENABLE);\n+\t\telse\n+\t\t\tregmap_clear_bits(priv->usxgmii_pcs,\n+\t\t\t\t\t  AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,\n+\t\t\t\t\t  AIROHA_PCS_USXGMII_AN_ENABLE);\n+\n+\t\tif (data->usxgmii_xfi_mode_sel && neg_mode)\n+\t\t\tregmap_set_bits(priv->usxgmii_pcs,\n+\t\t\t\t\tAIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,\n+\t\t\t\t\tAIROHA_PCS_USXGMII_XFI_MODE_TX_SEL |\n+\t\t\t\t\tAIROHA_PCS_USXGMII_XFI_MODE_RX_SEL);\n+\t}\n+\n+\t/* Clear any force bit that my be set by bootloader */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t    interface == PHY_INTERFACE_MODE_1000BASEX ||\n+\t    interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,\n+\t\t\t\t  AIROHA_PCS_LINK_MODE_P0 |\n+\t\t\t\t  AIROHA_PCS_FORCE_SPD_MODE_P0 |\n+\t\t\t\t  AIROHA_PCS_FORCE_LINKDOWN_P0 |\n+\t\t\t\t  AIROHA_PCS_FORCE_LINKUP_P0);\n+\t}\n+\n+\t/* Toggle Rate Adaption for SGMII/HSGMII mode */ /* TODO */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t    interface == PHY_INTERFACE_MODE_1000BASEX ||\n+\t    interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tif (neg_mode)\n+\t\t\tregmap_clear_bits(priv->hsgmii_rate_adp,\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);\n+\t\telse\n+\t\t\tregmap_set_bits(priv->hsgmii_rate_adp,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_P0_DIS_MII_MODE);\n+\t}\n+\n+\t/* Setup SGMII AN and advertisement in DEV_ABILITY */ /* TODO */\n+\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\tif (neg_mode) {\n+\t\t\tint advertise = 0x1;\n+\n+\t\t\tregmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,\n+\t\t\t\t\t   FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,\n+\t\t\t\t\t\t      advertise));\n+\n+\t\t\tregmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\t\t} else {\n+\t\t\tregmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\t\t}\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\tregmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,\n+\t\t\t\t  AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);\n+\n+\t\tregmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_TX_ENABLE);\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t    interface == PHY_INTERFACE_MODE_1000BASEX) {\n+\t\tu32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;\n+\n+\t\t/* Toggle SGMII or 1000base-x mode */\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII)\n+\t\t\tif_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN;\n+\n+\t\tif (neg_mode)\n+\t\t\tregmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);\n+\t\telse\n+\t\t\tregmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);\n+\n+\t\tif (neg_mode) {\n+\t\t\t/* Clear force speed bits and MAC mode */\n+\t\t\tregmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_PCS_MAC_MODE |\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |\n+\t\t\t\t\t  AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);\n+\t\t} else {\n+\t\t\t/* Enable compatibility with MAC PCS Layer */\n+\t\t\tif_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;\n+\n+\t\t\t/* AN off force rate adaption, speed is set later in Link Up */\n+\t\t\tregmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\tAIROHA_PCS_HSGMII_PCS_MAC_MODE |\n+\t\t\t\t\tAIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);\n+\t\t}\n+\n+\t\tregmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t   AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);\n+\n+\t\tregmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_TX_ENABLE |\n+\t\t\t\tAIROHA_PCS_HSGMII_PCS_MODE2_EN);\n+\t}\n+\n+\tif (interface == PHY_INTERFACE_MODE_1000BASEX &&\n+\t    !neg_mode) {\n+\t\tregmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,\n+\t\t\t\tAIROHA_PCS_SGMII_SEND_AN_ERR_EN);\n+\n+\t\tregmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,\n+\t\t\t\tAIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);\n+\t}\n+\n+\t/* Configure Flow Control on XFI */\n+\tregmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t   AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,\n+\t\t\t   permit_pause_to_mac ?\n+\t\t\t\tAIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :\n+\t\t\t\t0);\n+\n+\treturn 0;\n+}\n+\n+void airoha_pcs_link_up(struct udevice *dev, unsigned int neg_mode,\n+\t\t\tphy_interface_t interface, int speed, int duplex)\n+{\n+\tstruct airoha_pcs_priv *priv = dev_get_priv(dev);\n+\tconst struct airoha_pcs_match_data *data;\n+\n+\tdata = priv->data;\n+\n+\tif (neg_mode) {\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\t\tregmap_update_bits(priv->hsgmii_rate_adp,\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,\n+\t\t\t\t\t   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |\n+\t\t\t\t\t   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));\n+\t\t\tudelay(1);\n+\t\t\tregmap_update_bits(priv->hsgmii_rate_adp,\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,\n+\t\t\t\t\t   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |\n+\t\t\t\t\t   FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));\n+\t\t}\n+\t} else {\n+\t\tif (interface == PHY_INTERFACE_MODE_USXGMII ||\n+\t\t    interface == PHY_INTERFACE_MODE_10GBASER) {\n+\t\t\tu32 mode;\n+\t\t\tu32 rate_adapt;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_10000:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_10000;\n+\t\t\t\tbreak;\n+\t\t\t/* case SPEED_5000: not supported in U-Boot\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_5000;\n+\t\t\t\tbreak; */\n+\t\t\tcase SPEED_2500:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_2500;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_1000:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;\n+\t\t\t\tmode = AIROHA_PCS_USXGMII_MODE_100;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\t/* Trigger USXGMII change mode and force selected speed */\n+\t\t\tregmap_update_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,\n+\t\t\t\t\t   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE |\n+\t\t\t\t\t   AIROHA_PCS_USXGMII_MODE,\n+\t\t\t\t\t   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | mode);\n+\n+\t\t\tregmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |\n+\t\t\t\t\t   rate_adapt);\n+\t\t}\n+\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t\t    interface == PHY_INTERFACE_MODE_1000BASEX) {\n+\t\t\tu32 force_speed;\n+\t\t\tu32 rate_adapt;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_1000:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_10:\n+\t\t\t\tforce_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;\n+\t\t\t\trate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tregmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |\n+\t\t\t\t\t   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,\n+\t\t\t\t\t   force_speed | rate_adapt);\n+\t\t}\n+\n+\t\tif (interface == PHY_INTERFACE_MODE_SGMII ||\n+\t\t    interface == PHY_INTERFACE_MODE_2500BASEX) {\n+\t\t\tu32 ck_gen_mode;\n+\t\t\tu32 speed_reg;\n+\t\t\tu32 if_mode;\n+\n+\t\t\tswitch (speed) {\n+\t\t\tcase SPEED_2500:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_1000:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_1G;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_100:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_100M;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;\n+\t\t\t\tbreak;\n+\t\t\tcase SPEED_10:\n+\t\t\t\tspeed_reg = AIROHA_PCS_LINK_MODE_P0_100M;\n+\t\t\t\tif_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;\n+\t\t\t\tck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n+\t\t\t\tregmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,\n+\t\t\t\t\t\t   AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,\n+\t\t\t\t\t\t   if_mode);\n+\n+\t\t\t\tregmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,\n+\t\t\t\t\t\t   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |\n+\t\t\t\t\t\t   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,\n+\t\t\t\t\t\t   ck_gen_mode |\n+\t\t\t\t\t\t   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);\n+\t\t\t}\n+\n+\t\t\tregmap_update_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,\n+\t\t\t\t\t   AIROHA_PCS_LINK_MODE_P0 |\n+\t\t\t\t\t   AIROHA_PCS_FORCE_SPD_MODE_P0,\n+\t\t\t\t\t   speed_reg |\n+\t\t\t\t\t   AIROHA_PCS_FORCE_SPD_MODE_P0);\n+\t\t}\n+\t}\n+\n+\tif (data->link_up)\n+\t\tdata->link_up(priv);\n+\n+\t/* BPI BMI enable */\n+\tregmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t  AIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\t  AIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\t  AIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\t  AIROHA_PCS_XFI_TXMBI_STOP);\n+}\n+\n+void airoha_pcs_link_down(struct udevice *dev)\n+{\n+\tstruct airoha_pcs_priv *priv = dev_get_priv(dev);\n+\n+\t/* MPI MBI disable */\n+\tregmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMBI_STOP);\n+}\n+\n+void airoha_pcs_pre_config(struct udevice *dev, phy_interface_t interface)\n+{\n+\tstruct airoha_pcs_priv *priv = dev_get_priv(dev);\n+\n+\t/* Select HSGMII or USXGMII in SCU regs */\n+\tairoha_pcs_setup_scu(priv, interface);\n+\n+\t/* MPI MBI disable */\n+\tregmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_RXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_RXMBI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMPI_STOP |\n+\t\t\tAIROHA_PCS_XFI_TXMBI_STOP);\n+\n+\t/* Write 1 to trigger reset and clear */\n+\tregmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,\n+\t\t\t  AIROHA_PCS_XFI_MAC_LOGIC_RST);\n+\tregmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST,\n+\t\t\tAIROHA_PCS_XFI_MAC_LOGIC_RST);\n+\n+\tudelay(1000);\n+\n+\t/* Clear XFI MAC counter */\n+\tregmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR,\n+\t\t\tAIROHA_PCS_XFI_GLB_CNT_CLR);\n+}\n+\n+int airoha_pcs_post_config(struct udevice *dev, phy_interface_t interface)\n+{\n+\tstruct airoha_pcs_priv *priv = dev_get_priv(dev);\n+\n+\t/* Frag disable */\n+\tregmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t   AIROHA_PCS_XFI_RX_FRAG_LEN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31));\n+\tregmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t   AIROHA_PCS_XFI_TX_FRAG_LEN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31));\n+\n+\t/* IPG NUM */\n+\tregmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\t   AIROHA_PCS_XFI_IPG_NUM,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10));\n+\n+\t/* Enable TX/RX flow control */\n+\tregmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_TX_FC_EN);\n+\tregmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,\n+\t\t\tAIROHA_PCS_XFI_RX_FC_EN);\n+\n+\treturn 0;\n+}\n+\n+static const struct regmap_config airoha_pcs_regmap_config = {\n+\t.width = REGMAP_SIZE_32,\n+};\n+\n+static int airoha_pcs_probe(struct udevice *dev)\n+{\n+\tstruct regmap_config syscon_config = airoha_pcs_regmap_config;\n+\tstruct airoha_pcs_priv *priv = dev_get_priv(dev);\n+\tfdt_addr_t base;\n+\tfdt_size_t size;\n+\tint ret;\n+\n+\tpriv->dev = dev;\n+\tpriv->data = (void *)dev_get_driver_data(dev);\n+\n+\tbase = dev_read_addr_size_name(dev, \"xfi_mac\", &size);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tsyscon_config.r_start = base;\n+\tsyscon_config.r_size = size;\n+\tpriv->xfi_mac = devm_regmap_init(dev, NULL, NULL, &syscon_config);\n+\tif (IS_ERR(priv->xfi_mac))\n+\t\treturn PTR_ERR(priv->xfi_mac);\n+\n+\tbase = dev_read_addr_size_name(dev, \"hsgmii_an\", &size);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tsyscon_config.r_start = base;\n+\tsyscon_config.r_size = size;\n+\tpriv->hsgmii_an = devm_regmap_init(dev, NULL, NULL, &syscon_config);\n+\tif (IS_ERR(priv->hsgmii_an))\n+\t\treturn PTR_ERR(priv->hsgmii_an);\n+\n+\tbase = dev_read_addr_size_name(dev, \"hsgmii_pcs\", &size);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tsyscon_config.r_start = base;\n+\tsyscon_config.r_size = size;\n+\tpriv->hsgmii_pcs = devm_regmap_init(dev, NULL, NULL, &syscon_config);\n+\tif (IS_ERR(priv->hsgmii_pcs))\n+\t\treturn PTR_ERR(priv->hsgmii_pcs);\n+\n+\tbase = dev_read_addr_size_name(dev, \"hsgmii_rate_adp\", &size);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tsyscon_config.r_start = base;\n+\tsyscon_config.r_size = size;\n+\tpriv->hsgmii_rate_adp = devm_regmap_init(dev, NULL, NULL, &syscon_config);\n+\tif (IS_ERR(priv->hsgmii_rate_adp))\n+\t\treturn PTR_ERR(priv->hsgmii_rate_adp);\n+\n+\tbase = dev_read_addr_size_name(dev, \"multi_sgmii\", &size);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tsyscon_config.r_start = base;\n+\tsyscon_config.r_size = size;\n+\tpriv->multi_sgmii = devm_regmap_init(dev, NULL, NULL, &syscon_config);\n+\tif (IS_ERR(priv->multi_sgmii))\n+\t\treturn PTR_ERR(priv->multi_sgmii);\n+\n+\tbase = dev_read_addr_size_name(dev, \"usxgmii\", &size);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tsyscon_config.r_start = base;\n+\tsyscon_config.r_size = size;\n+\tpriv->usxgmii_pcs = devm_regmap_init(dev, NULL, NULL, &syscon_config);\n+\tif (IS_ERR(priv->usxgmii_pcs))\n+\t\treturn PTR_ERR(priv->usxgmii_pcs);\n+\n+\tbase = dev_read_addr_size_name(dev, \"xfi_pma\", &size);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tsyscon_config.r_start = base;\n+\tsyscon_config.r_size = size;\n+\tpriv->xfi_pma = devm_regmap_init(dev, NULL, NULL, &syscon_config);\n+\tif (IS_ERR(priv->xfi_pma))\n+\t\treturn PTR_ERR(priv->xfi_pma);\n+\n+\tbase = dev_read_addr_size_name(dev, \"xfi_ana\", &size);\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\tsyscon_config.r_start = base;\n+\tsyscon_config.r_size = size;\n+\tpriv->xfi_ana = devm_regmap_init(dev, NULL, NULL, &syscon_config);\n+\tif (IS_ERR(priv->xfi_ana))\n+\t\treturn PTR_ERR(priv->xfi_ana);\n+\n+\t/* SCU is used to toggle XFI or HSGMII in global SoC registers */\n+\tpriv->scu = syscon_regmap_lookup_by_phandle(dev, \"airoha,scu\");\n+\tif (IS_ERR(priv->scu))\n+\t\treturn PTR_ERR(priv->scu);\n+\n+\tpriv->rsts.resets = devm_kcalloc(dev, AIROHA_PCS_MAX_NUM_RSTS,\n+\t\t\t\t\t sizeof(struct reset_ctl), GFP_KERNEL);\n+\tif (!priv->rsts.resets)\n+\t\treturn -ENOMEM;\n+\tpriv->rsts.count = AIROHA_PCS_MAX_NUM_RSTS;\n+\n+\tret = reset_get_by_name(dev, \"mac\", &priv->rsts.resets[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = reset_get_by_name(dev, \"phy\", &priv->rsts.resets[1]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tpriv->xfi_rst = devm_reset_control_get_optional(dev, \"xfi\");\n+\n+\treturn 0;\n+}\n+\n+static const struct airoha_pcs_match_data an7581_pcs_eth = {\n+\t.port_type = AIROHA_PCS_ETH,\n+\t.hibernation_workaround = true,\n+\t.usxgmii_ber_time_fixup = true,\n+\t.bringup = an7581_pcs_bringup,\n+\t.link_up = an7581_pcs_phya_link_up,\n+};\n+\n+static const struct airoha_pcs_match_data an7581_pcs_pon = {\n+\t.port_type = AIROHA_PCS_PON,\n+\t.hibernation_workaround = true,\n+\t.usxgmii_ber_time_fixup = true,\n+\t.bringup = an7581_pcs_bringup,\n+\t.link_up = an7581_pcs_phya_link_up,\n+};\n+\n+static const struct udevice_id airoha_pcs_of_table[] = {\n+\t{ .compatible = \"airoha,an7581-pcs-eth\",\n+\t  .data = (ulong)&an7581_pcs_eth },\n+\t{ .compatible = \"airoha,an7581-pcs-pon\",\n+\t  .data = (ulong)&an7581_pcs_pon },\n+\t{ },\n+};\n+\n+U_BOOT_DRIVER(airoha_pcs) = {\n+\t.name = \"airoha-pcs\",\n+\t.id = UCLASS_MISC,\n+\t.of_match = airoha_pcs_of_table,\n+\t.probe = airoha_pcs_probe,\n+\t.priv_auto = sizeof(struct airoha_pcs_priv),\n+};\ndiff --git a/drivers/net/airoha/pcs-airoha.h b/drivers/net/airoha/pcs-airoha.h\nnew file mode 100644\nindex 00000000000..f9e325511af\n--- /dev/null\n+++ b/drivers/net/airoha/pcs-airoha.h\n@@ -0,0 +1,1216 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi <ansuelsmth@gmail.com>\n+ */\n+\n+#include <linux/bitfield.h>\n+#include <regmap.h>\n+#include <reset.h>\n+\n+/* SCU*/\n+#define AIROHA_SCU_WAN_CONF\t\t\t0x70\n+#define   AIROHA_SCU_ETH_MAC_SEL\t\tBIT(24)\n+#define   AIROHA_SCU_ETH_MAC_SEL_XFI\t\tFIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x0)\n+#define   AIROHA_SCU_ETH_MAC_SEL_PON\t\tFIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x1)\n+#define   AIROHA_SCU_WAN_SEL\t\t\tGENMASK(7, 0)\n+#define   AIROHA_SCU_WAN_SEL_SGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)\n+#define   AIROHA_SCU_WAN_SEL_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)\n+#define   AIROHA_SCU_WAN_SEL_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)\n+#define AIROHA_SCU_SSR3\t\t\t\t0x94\n+#define   AIROHA_SCU_ETH_XSI_SEL\t\tGENMASK(14, 13)\n+#define   AIROHA_SCU_ETH_XSI_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)\n+#define   AIROHA_SCU_ETH_XSI_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)\n+#define AIROHA_SCU_SSTR\t\t\t\t0x9c\n+#define   AIROHA_SCU_PON_XSI_SEL\t\tGENMASK(10, 9)\n+#define   AIROHA_SCU_PON_XSI_USXGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)\n+#define   AIROHA_SCU_PON_XSI_HSGMII\t\tFIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)\n+\n+/* XFI_MAC */\n+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG\t\t0x0\n+#define   AIROHA_PCS_XFI_RX_FRAG_LEN\t\tGENMASK(26, 22)\n+#define   AIROHA_PCS_XFI_TX_FRAG_LEN\t\tGENMASK(21, 17)\n+#define   AIROHA_PCS_XFI_IPG_NUM\t\tGENMASK(15, 10)\n+#define   AIROHA_PCS_XFI_TX_FC_EN\t\tBIT(5)\n+#define   AIROHA_PCS_XFI_RX_FC_EN\t\tBIT(4)\n+#define   AIROHA_PCS_XFI_RXMPI_STOP\t\tBIT(3)\n+#define   AIROHA_PCS_XFI_RXMBI_STOP\t\tBIT(2)\n+#define   AIROHA_PCS_XFI_TXMPI_STOP\t\tBIT(1)\n+#define   AIROHA_PCS_XFI_TXMBI_STOP\t\tBIT(0)\n+#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST\t0x10\n+#define   AIROHA_PCS_XFI_MAC_LOGIC_RST\t\tBIT(0)\n+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH\t\t0x60\n+#define   AIROHA_PCS_XFI_MAC_MACADDRH\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL\t\t0x64\n+#define   AIROHA_PCS_XFI_MAC_MACADDRL\t\tGENMASK(31, 0)\n+#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR\t\t0x100\n+#define   AIROHA_PCS_XFI_GLB_CNT_CLR\t\tBIT(0)\n+\n+/* HSGMII_AN */\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0\t0x0\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE\tBIT(12)\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART\tBIT(9)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1\t0x4 /* BMSR */\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4\t0x10\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5\t0x14 /* LPA */\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11\t0x2c\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER\tGENMASK(19, 0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13\t0x34\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)\n+#define   AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)\n+#define     AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)\n+#define     AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)\n+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)\n+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)\n+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)\n+#define     AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)\n+#define     AIROHA_PCS_HSGMII_AN_SIDEBAND_EN\tBIT(1)\n+#define     AIROHA_PCS_HSGMII_AN_SGMII_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60\n+#define   AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE\tBIT(0)\n+\n+/* HSGMII_PCS */\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_1\t\t0x0\n+#define   AIROHA_PCS_TBI_10B_MODE\t\tBIT(30)\n+#define   AIROHA_PCS_SGMII_SEND_AN_ERR_EN\tBIT(24)\n+#define   AIROHA_PCS_REMOTE_FAULT_DIS\t\tBIT(12)\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_3\t\t0x8\n+#define   AIROHA_PCS_HSGMII_PCS_LINK_STSTIME\tGENMASK(19, 0)\n+#define AIROHA_PCS_HSGMII_PCS_CTROL_6\t\t0x14\n+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)\n+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)\n+#define   AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)\n+#define   AIROHA_PCS_HSGMII_PCS_MAC_MODE\tBIT(8)\n+#define   AIROHA_PCS_HSGMII_PCS_TX_ENABLE\tBIT(4)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT\tBIT(1)\n+#define   AIROHA_PCS_HSGMII_PCS_MODE2_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20\n+#define   AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)\n+#define   AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)\n+#define   AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)\n+#define   AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)\n+#define   AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)\n+#define   AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT\tBIT(4)\n+#define   AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)\n+#define   AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)\n+#define   AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)\n+#define   AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)\n+#define   AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)\n+#define ARIOHA_PCS_HSGMII_PCS_STATE_2\t\t0x104\n+#define   AIROHA_PCS_HSGMII_PCS_RX_SYNC\t\tBIT(5)\n+#define   AIROHA_PCS_HSGMII_PCS_AN_DONE\t\tBIT(0)\n+#define AIROHA_PCS_HSGMII_PCS_INT_STATE\t\t0x15c\n+#define   AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)\n+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS\tBIT(3)\n+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)\n+#define   AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC\tBIT(1)\n+#define   AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE\tBIT(0)\n+\n+/* MULTI_SGMII */\n+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0\t0x14\n+#define   AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18\n+#define   AIROHA_PCS_LINK_MODE_P0\t\tGENMASK(5, 4)\n+#define   AIROHA_PCS_LINK_MODE_P0_2_5G\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)\n+#define   AIROHA_PCS_LINK_MODE_P0_1G\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)\n+#define   AIROHA_PCS_LINK_MODE_P0_100M\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)\n+#define   AIROHA_PCS_LINK_MODE_P0_10M\t\tFIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)\n+#define   AIROHA_PCS_FORCE_SPD_MODE_P0\t\tBIT(2)\n+#define   AIROHA_PCS_FORCE_LINKDOWN_P0\t\tBIT(1)\n+#define   AIROHA_PCS_FORCE_LINKUP_P0\t\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0\t0x100\n+#define   AIROHA_PCS_HSGMII_XFI_SEL\t\tBIT(28)\n+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL\t0x14c\n+#define   AIROHA_PCS_HSGMII_PCS_INT\t\tBIT(0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15\t0x43c\n+#define   AIROHA_PCS_LINK_STS_P0\t\tBIT(3)\n+#define   AIROHA_PCS_SPEED_STS_P0\t\tGENMASK(2, 0)\n+#define   AIROHA_PCS_SPEED_STS_P0_1G\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)\n+#define   AIROHA_PCS_SPEED_STS_P0_100M\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)\n+#define   AIROHA_PCS_SPEED_STS_P0_10M\t\tFIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)\n+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18\t0x448\n+#define   AIROHA_PCS_P0_SGMII_IS_10\t\tBIT(2)\n+#define   AIROHA_PCS_P0_SGMII_IS_100\t\tBIT(1)\n+#define   AIROHA_PCS_P0_SGMII_IS_1000\t\tBIT(0)\n+\n+/* HSGMII_RATE_ADP */\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0\t0x0\n+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)\n+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)\n+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN\tBIT(4)\n+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN\tBIT(0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1\t0x4\n+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)\n+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6\t0x18\n+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8\t0x20\n+#define   AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)\n+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11\t0x2c\n+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)\n+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)\n+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)\n+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)\n+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)\n+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)\n+#define   AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \\\n+\tFIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)\n+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0\t0x100\n+#define   AIROHA_PCS_HSGMII_P0_DIS_MII_MODE\tBIT(31)\n+\n+/* USXGMII */\n+#define AIROHA_PCS_USXGMII_PCS_CTROL_1\t\t0x0\n+#define   AIROHA_PCS_USXGMII_SPEED_SEL_H\tBIT(13)\n+#define AIROHA_PCS_USXGMII_PCS_STUS_1\t\t0x30\n+#define   AIROHA_PCS_USXGMII_RX_LINK_STUS\tBIT(12)\n+#define   AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)\n+#define   AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)\n+#define   AIROHA_PCS_USXGMII_PCS_BLK_LK\t\tBIT(0)\n+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116\t0x22c\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_0\t\t0x2c0\n+#define   AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN\tBIT(24)\n+#define   AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN\tBIT(16)\n+#define   AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN\tBIT(8)\n+#define   AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_1\t\t0x2c4\n+#define   AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN\tBIT(24)\n+#define   AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN\tBIT(16)\n+#define   AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)\n+#define   AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_2\t\t0x2c8\n+#define   AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)\n+#define   AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN\tBIT(16)\n+#define   AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN\tBIT(8)\n+#define   AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_3\t\t0x2cc\n+#define   AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)\n+#define   AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)\n+#define   AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN\tBIT(8)\n+#define   AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2\t0x2d8\n+#define   AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)\n+#define   AIROHA_PCS_USXGMII_R_TYPE_E_INT\tBIT(16)\n+#define   AIROHA_PCS_USXGMII_R_TYPE_T_INT\tBIT(8)\n+#define   AIROHA_PCS_USXGMII_R_TYPE_D_INT\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3\t0x2dc\n+#define   AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)\n+#define   AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)\n+#define   AIROHA_PCS_USXGMII_LINK_UP_ST_INT\tBIT(8)\n+#define   AIROHA_PCS_USXGMII_HI_BER_ST_INT\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_CTRL_4\t\t0x2e0\n+#define   AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4\t0x2e4\n+#define   AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0\t0x2f8\n+#define   AIROHA_PCS_USXGMII_AN_RESTART\t\tBIT(8)\n+#define   AIROHA_PCS_USXGMII_AN_ENABLE\t\tBIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0\t0x310\n+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE\tGENMASK(30, 28)\n+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)\n+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)\n+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)\n+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)\n+#define   AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)\n+#define   AIROHA_PCS_USXGMII_PARTNER_ABILITY\tGENMASK(15, 0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2\t0x318\n+#define   AIROHA_PCS_USXGMII_PCS_AN_COMPLETE\tBIT(24)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6\t0x31c\n+#define   AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)\n+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7\t0x320\n+#define   AIROHA_PCS_USXGMII_XFI_MODE_TX_SEL\tBIT(20)\n+#define   AIROHA_PCS_USXGMII_XFI_MODE_RX_SEL\tBIT(16)\n+#define   AIROHA_PCS_USXGMII_RATE_UPDATE_MODE\tBIT(12)\n+#define   AIROHA_PCS_USXGMII_MODE\t\tGENMASK(10, 8)\n+#define   AIROHA_PCS_USXGMII_MODE_10000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)\n+#define   AIROHA_PCS_USXGMII_MODE_5000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1)\n+#define   AIROHA_PCS_USXGMII_MODE_2500\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)\n+#define   AIROHA_PCS_USXGMII_MODE_1000\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)\n+#define   AIROHA_PCS_USXGMII_MODE_100\t\tFIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)\n+#define AN7583_PCS_USXGMII_RTL_MODIFIED\t\t0x334\n+#define   AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD BIT(25)\n+\n+/* PMA_PHYA */\n+#define AIROHA_PCS_ANA_PXP_CMN_EN\t\t0x0\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL\t\tGENMASK(18, 16)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL_8V\t\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x0)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL_8_25V\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x1)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL_8_5V\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x2)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL_8_75V\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x3)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL_9V\t\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x4)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL_9_25V\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x5)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL_9_5V\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x6)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL_9_75V\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x7)\n+#define   AIROHA_PCS_ANA_CMN_VREFSEL\t\tGENMASK(18, 16)\n+/* GENMASK(2, 0) input selection from 0 to 7\n+ * BIT(3) OPAMP and path EN\n+ * BIT(4) Current path measurement\n+ * BIT(5) voltage/current path to PAD\n+ */\n+#define   AIROHA_PCS_ANA_CMN_MPXSELTOP_DC\tGENMASK(13, 8)\n+#define   AIROHA_PCS_ANA_CMN_EN\t\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN\t0x4\n+#define   AIROHA_PCS_ANA_JCPLL_CHP_IOFST\tGENMASK(29, 24)\n+#define   AIROHA_PCS_ANA_JCPLL_CHP_IBIAS\tGENMASK(21, 16)\n+#define   AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR\t\t0x8\n+#define   AIROHA_PCS_ANA_JCPLL_LPF_BWR\t\tGENMASK(28, 24)\n+#define   AIROHA_PCS_ANA_JCPLL_LPF_BP\t\tGENMASK(20, 16)\n+#define   AIROHA_PCS_ANA_JCPLL_LPF_BC\t\tGENMASK(12, 8)\n+#define   AIROHA_PCS_ANA_JCPLL_LPF_BR\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC\t0xc\n+#define   AIROHA_PCS_ANA_JCPLL_KBAND_DIV\tGENMASK(26, 24)\n+#define   AIROHA_PCS_ANA_JCPLL_KBAND_CODE\tGENMASK(23, 16)\n+#define   AIROHA_PCS_ANA_JCPLL_KBAND_OPTION\tBIT(8)\n+#define   AIROHA_PCS_ANA_JCPLL_LPF_BWC\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC\t0x10\n+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KS\t\tGENMASK(17, 16)\n+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KF\t\tGENMASK(9, 8)\n+#define   AIROHA_PCS_ANA_JCPLL_KBAND_KFC\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14\n+#define   AIROHA_PCS_ANA_JCPLL_POSTDIV_D5\tBIT(24)\n+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE\tGENMASK(1, 0)\n+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0)\n+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1)\n+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2)\n+#define   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY\t0x1c\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS\tGENMASK(25, 24)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_DI_EN\tBIT(16)\n+#define   AIROHA_PCS_ANA_JCPLL_PLL_RSTB\t\tBIT(8)\n+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY\t\tGENMASK(2, 0)\n+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1)\n+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2)\n+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3)\n+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4)\n+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5)\n+#define   AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM\t0x20\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_OUT\t\tBIT(24)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD\t\tGENMASK(17, 16)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_MODE\t\tGENMASK(9, 8)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_IFM\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN\t0x24\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF\tGENMASK(28, 24)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN\tGENMASK(18, 16)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN\tBIT(8)\n+#define   AIROHA_PCS_ANA_JCPLL_SDM_HREN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN\t0x28\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW\tGENMASK(26, 24)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN\tBIT(16)\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW\tGENMASK(26, 24)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV\t\t0x2c\n+#define   AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR\tGENMASK(26, 24)\n+#define   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN\tBIT(16)\n+#define   AIROHA_PCS_ANA_JCPLL_VCO_CFIX\t\tGENMASK(9, 8)\n+#define   AIROHA_PCS_ANA_JCPLL_VCODIV\t\tGENMASK(1, 0)\n+#define   AIROHA_PCS_ANA_JCPLL_VCODIV_1\t\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0)\n+#define   AIROHA_PCS_ANA_JCPLL_VCODIV_2\t\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR\t0x30\n+#define   AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI\tBIT(17)\n+#define   AIROHA_PCS_ANA_JCPLL_SSC_EN\t\tBIT(16)\n+#define   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)\n+#define   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)\n+#define   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN\t0x34\n+#define   AIROHA_PCS_ANA_JCPLL_SSC_DELTA1\tGENMASK(23, 8)\n+#define   AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA\t0x38\n+#define   AIROHA_PCS_ANA_JCPLL_SSC_PERIOD\tGENMASK(31, 16)\n+#define   AIROHA_PCS_ANA_JCPLL_SSC_DELTA\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H\t0x48\n+#define   AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF\tGENMASK(20, 16)\n+#define   AIROHA_PCS_ANA_JCPLL_SPARE_L\t\tGENMASK(15, 8)\n+#define     AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO\tFIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))\n+#define AIROHA_PCS_ANA_PXP_JCPLL_FREQ_MEAS_EN\t0x4c\n+#define   AIROHA_PCS_ANA_TXPLL_IB_EXT_EN\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS\t0x50\n+#define   AIROHA_PCS_ANA_TXPLL_LPF_BC\t\tGENMASK(28, 24)\n+#define   AIROHA_PCS_ANA_TXPLL_LPF_BR\t\tGENMASK(20, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_CHP_IOFST\tGENMASK(13, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_CHP_IBIAS\tGENMASK(5, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP\t\t0x54\n+#define   AIROHA_PCS_ANA_TXPLL_KBAND_OPTION\tBIT(24)\n+#define   AIROHA_PCS_ANA_TXPLL_LPF_BWC\t\tGENMASK(20, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_LPF_BWR\t\tGENMASK(12, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_LPF_BP\t\tGENMASK(4, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE\t0x58\n+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KF\t\tGENMASK(25, 24)\n+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KFC\tGENMASK(17, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_KBAND_DIV\tGENMASK(10, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_KBAND_CODE\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS\t0x5c\n+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE\tGENMASK(17, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0)\n+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1)\n+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2)\n+#define   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3)\n+#define   AIROHA_PCS_ANA_TXPLL_POSTDIV_EN\tBIT(8)\n+#define   AIROHA_PCS_ANA_TXPLL_KBAND_KS\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_PHY_CK1_EN\t0x60\n+#define   AIROHA_PCS_ANA_TXPLL_PHY_CK2_EN\tBIT(8)\n+#define   AIROHA_PCS_ANA_TXPLL_PHY_CK1_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL\t0x64\n+#define   AIROHA_PCS_ANA_TXPLL_PLL_RSTB\t\tBIT(24)\n+#define   AIROHA_PCS_ANA_TXPLL_RST_DLY\t\tGENMASK(18, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV\tGENMASK(9, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0)\n+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1)\n+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2)\n+#define   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3)\n+#define   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN\t0x68\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_MODE\t\tGENMASK(25, 24)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_IFM\t\tBIT(16)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS\tGENMASK(9, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_DI_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD\t0x6c\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN\tBIT(24)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_HREN\t\tBIT(16)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_OUT\t\tBIT(8)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD\t\tGENMASK(1, 0)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2)\n+#define   AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN\t0x70\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF\tGENMASK(12, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN\tGENMASK(2, 0)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN\t0x74\n+#define   AIROHA_PCS_ANA_TXPLL_VCO_CFIX\t\tGENMASK(25, 24)\n+#define   AIROHA_PCS_ANA_TXPLL_VCODIV\t\tGENMASK(17, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_1\t\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0)\n+#define   AIROHA_PCS_ANA_TXPLL_VCODIV_2\t\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW\tGENMASK(10, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN\t0x78\n+#define   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)\n+#define   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)\n+#define   AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR\tGENMASK(18, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR\tGENMASK(10, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN\t\t0x7c\n+#define   AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN\tBIT(16)\n+#define   AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI\tBIT(8)\n+#define   AIROHA_PCS_ANA_TXPLL_SSC_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1\t0x80\n+#define   AIROHA_PCS_ANA_TXPLL_SSC_DELTA\tGENMASK(31, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_SSC_DELTA1\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD\t0x84\n+#define   AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT\tGENMASK(25, 24)\n+#define   AIROHA_PCS_ANA_TXPLL_LDO_OUT\t\tGENMASK(17, 16)\n+#define   AIROHA_PCS_ANA_TXPLL_SSC_PERIOD\tGENMASK(15, 0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_VTP_EN\t\t0x88\n+#define   AIROHA_PCS_ANA_TXPLL_VTP\t\tGENMASK(10, 8)\n+#define   AIROHA_PCS_ANA_TXPLL_VTP_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF\t0x94\n+#define   AIROHA_PCS_ANA_TXPLL_POSTDIV_D256_EN\tBIT(25) /* 0: 128 1: 256 */\n+#define   AIROHA_PCS_ANA_TXPLL_VCO_KBAND_MEAS_EN BIT(24)\n+#define   AIROHA_PCS_ANA_TXPLL_FREQ_MEAS_EN\tBIT(16)\n+#define   AIROHA_PCS_ANA_TXPLL_VREF_SEL\t\tBIT(8)\n+#define   AIROHA_PCS_ANA_TXPLL_VREF_SEL_VBG\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x0)\n+#define   AIROHA_PCS_ANA_TXPLL_VREF_SEL_AVDD\tFIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x1)\n+#define   AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF\tGENMASK(4, 0)\n+#define AN7583_PCS_ANA_PXP_TXPLL_CHP_DOUBLE_EN\t0x98\n+#define   AIROHA_PCS_ANA_TXPLL_SPARE_L\t\tBIT(0) /* ICHP_DOUBLE */\n+#define AIROHA_PCS_ANA_PXP_PLL_MONCLK_SEL\t0xa0\n+#define   AIROHA_PCS_ANA_TDC_AUTOEN\t\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_TDC_SYNC_CK_SEL\t0xa8\n+#define   AIROHA_PCS_ANA_PLL_LDO_CKDRV_VSEL\tGENMASK(17, 16)\n+#define   AIROHA_PCS_ANA_PLL_LDO_CKDRV_EN\tBIT(8)\n+#define AIROHA_PCS_ANA_PXP_TX_TXLBRC_EN\t\t0xc0\n+#define   AIROHA_PCS_ANA_TX_TERMCAL_VREF_L\tGENMASK(26, 24)\n+#define   AIROHA_PCS_ANA_TX_TERMCAL_VREF_H\tGENMASK(18, 16)\n+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN\t\t0xc4\n+#define   AIROHA_PCS_ANA_TX_DMEDGEGEN_EN\tBIT(24)\n+#define   AIROHA_PCS_ANA_TX_CKLDO_EN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_TX_TERMCAL_SELPN\t0xc8\n+#define   AIROHA_PCS_ANA_TX_TDC_CK_SEL\t\tGENMASK(17, 16)\n+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL\t0xcc\n+#define    AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE\tBIT(24)\n+#define    AIROHA_PCS_ANA_RX_PHY_CK_SEL\t\tBIT(16)\n+#define      AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_PHY_CK_SEL, 0x0)\n+#define      AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_PHY_CK_SEL, 0x1)\n+#define    AIROHA_PCS_ANA_RX_BUSBIT_SEL_FORCE\tBIT(8)\n+#define    AIROHA_PCS_ANA_RX_BUSBIT_SEL\t\tBIT(0)\n+#define      AIROHA_PCS_ANA_RX_BUSBIT_SEL_8BIT\tFIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x0)\n+#define      AIROHA_PCS_ANA_RX_BUSBIT_SEL_16BIT\tFIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x1)\n+#define AIROHA_PCS_ANA_PXP_RX_REV_0\t\t0xd4\n+#define   AIROHA_PCS_ANA_RX_REV_1\t\tGENMASK(31, 16)\n+#define     AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)\n+#define     AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)\n+#define     AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)\n+#define     AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK\tGENMASK(19, 18)\n+#define     AIROHA_PCS_ANA_REV_1_FECUR_PWDB\tBIT(16)\n+#define   AIROHA_PCS_ANA_RX_REV_0\t\tGENMASK(15, 0)\n+#define     AIROHA_PCS_ANA_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12)\n+#define     AIROHA_PCS_ANA_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11)\n+#define     AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10)\n+#define     AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8)\n+#define     AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6)\n+#define     AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4)\n+#define     AIROHA_PCS_ANA_REV_0_VOS_PNINV\tGENMASK(3, 2)\n+#define     AIROHA_PCS_ANA_REV_0_PLEYEBD4\tBIT(1)\n+#define     AIROHA_PCS_ANA_REV_0_PLEYE_XOR_MON_EN BIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV\t\t0xd8\n+#define   AIROHA_PCS_ANA_RX_TDC_CK_SEL\t\tBIT(24)\n+#define   AIROHA_PCS_ANA_RX_PHYCK_RSTB\t\tBIT(16)\n+#define   AIROHA_PCS_ANA_RX_PHYCK_SEL\t\tGENMASK(9, 8)\n+#define   AIROHA_PCS_ANA_RX_PHYCK_DIV\t\tGENMASK(7, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc\n+#define   AIROHA_PCS_ANA_CDR_PD_EDGE_DIS\tBIT(8)\n+#define   AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_CDR_LPF_BOT_LIM\t0xe0\n+#define   AIROHA_PCS_ANA_CDR_LPF_BOT_LIM\tGENMASK(18, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO\t0xe8\n+#define   AIROHA_PCS_ANA_CDR_LPF_TOP_LIM\tGENMASK(26, 8)\n+#define   AIROHA_PCS_ANA_CDR_LPF_RATIO\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE\t0xf4\n+#define   AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC\t0xf8\n+#define   AIROHA_PCS_ANA_CDR_PR_KBAND_DIV\tGENMASK(26, 24)\n+#define   AIROHA_PCS_ANA_CDR_PR_BETA_SEL\tGENMASK(19, 16)\n+#define   AIROHA_PCS_ANA_CDR_PR_VCOADC_OS\tGENMASK(11, 8)\n+#define   AIROHA_PCS_ANA_CDR_PR_BETA_DAC\tGENMASK(6, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc\n+#define   AIROHA_PCS_ANA_CDR_PR_FBKSEL\t\tGENMASK(25, 24)\n+#define   AIROHA_PCS_ANA_CDR_PR_DAC_BAND\tGENMASK(20, 16)\n+#define   AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL\tGENMASK(10, 8)\n+#define   AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL\tGENMASK(2, 0)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_CKREF_DIV\t0x100\n+#define   AIROHA_PCS_ANA_CDR_PR_RSTB_BYPASS\tBIT(16)\n+#define   AIROHA_PCS_ANA_CDR_PR_CKREF_DIV\tGENMASK(1, 0)\n+#define     AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_1\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x0)\n+#define     AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_2\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x1)\n+#define     AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_4\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x2)\n+#define     AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_X\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x3)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_TDC_REF_SEL\t0x108\n+#define   AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1\tGENMASK(25, 24)\n+#define     AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_1\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x0)\n+#define     AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_2\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x1)\n+#define     AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_4\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x2)\n+#define     AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_X\tFIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x3)\n+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN\t0x10c\n+#define   AIROHA_PCS_ANA_RX_DAC_MON\t\tGENMASK(28, 24)\n+#define   AIROHA_PCS_ANA_CDR_PR_CAP_EN\t\tBIT(19)\n+#define   AIROHA_PCS_ANA_CDR_BUF_IN_SR\t\tGENMASK(18, 16)\n+#define   AIROHA_PCS_ANA_CDR_PR_XFICK_EN\tBIT(2)\n+#define   AIROHA_PCS_ANA_CDR_PR_MONDPI_EN\tBIT(1)\n+#define   AIROHA_PCS_ANA_CDR_PR_MONDPR_EN\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE\t\t0x110\n+#define   AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL\tGENMASK(25, 24)\n+#define   AIROHA_PCS_ANA_RX_DAC_RANGE_EYE\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH\t0x114\n+#define   AIROHA_PCS_ANA_RX_FE_50OHMS_SEL\tGENMASK(25, 24)\n+#define   AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL\tGENMASK(20, 16)\n+#define   AIROHA_PCS_ANA_RX_SIGDET_PEAK\t\tGENMASK(9, 8)\n+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN\t0x118\n+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN\tBIT(24)\n+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN\tBIT(16)\n+#define   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN\tBIT(8)\n+#define   AIROHA_PCS_ANA_RX_FE_EQ_HZEN\t\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB\t0x11c\n+#define   AIROHA_PCS_ANA_FE_VCM_GEN_PWDB\tBIT(0)\n+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW\t0x120\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE\t\tGENMASK(17, 8)\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS\tFIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS\tFIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS\tFIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS\tFIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH\tFIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8))\n+#define   AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS\tFIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9))\n+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE\t\t0x13c\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE\t\tGENMASK(19, 8)\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_SAOS\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_VGA\t\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_CTLE\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9))\n+#define   AIROHA_PCS_ANA_AEQ_OFORCE_ATT\t\tFIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10))\n+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144\n+#define   AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ\tBIT(24)\n+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ\t0x148\n+#define   AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ\tBIT(24)\n+#define   AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ\tBIT(16)\n+#define   AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ\tBIT(8)\n+#define   AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ\tBIT(0)\n+\n+/* PMA_PHYD */\n+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0\t0x0\n+#define   AIROHA_PCS_PMA_SW_LCPLL_EN\t\tBIT(24)\n+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1\t0x4\n+#define   AIROHA_PCS_PMA_LCPLL_CK_STB_TIMER\tGENMASK(31, 24)\n+#define   AIROHA_PCS_PMA_LCPLL_PCW_MAN_LOAD_TIMER GENMASK(23, 16)\n+#define   AIROHA_PCS_PMA_LCPLL_EN_TIMER\t\tGENMASK(15, 8)\n+#define   AIROHA_PCS_PMA_LCPLL_MAN_PWDB\t\tBIT(0)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_PW_0\t\t0x10\n+#define   AIROHA_PCS_PMA_LCPLL_TDC_DIG_PWDB\tBIT(0)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_PW_5\t\t0x24\n+#define   AIROHA_PCS_PMA_LCPLL_TDC_SYNC_IN_MODE\tBIT(24)\n+#define   AIROHA_PCS_PMA_LCPLL_AUTOK_TDC\tBIT(16)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_0\t\t0x28\n+#define   AIROHA_PCS_PMA_LCPLL_KI\t\tGENMASK(10, 8)\n+#define   AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC GENMASK(1, 0)\n+#define   AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x0)\n+#define   AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x1)\n+#define   AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x2)\n+#define   AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x3)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_1\t\t0x2c\n+#define   AIROHA_PCS_PMA_LCPLL_A_TDC\t\tGENMASK(11, 8)\n+#define   AIROHA_PCS_PMA_LCPLL_GPON_SEL\t\tBIT(0)\n+#define   AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_EPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x0)\n+#define   AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_GPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x1)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_3\t\t0x34\n+#define   AIROHA_PCS_PMA_LCPLL_NCPO_LOAD\tBIT(8)\n+#define   AIROHA_PCS_PMA_LCPLL_NCPO_SHIFT\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_5\t\t0x3c\n+#define   AIROHA_PCS_PMA_LCPLL_TDC_AUTOPW_NCPO\tBIT(16)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_6\t\t0x40\n+#define   AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY\tGENMASK(9, 8)\n+#define   AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x0)\n+#define   AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D1 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x1)\n+#define   AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D2 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x2)\n+#define   AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D3 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x3)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_PCW_1\t\t0x48\n+#define   AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)\n+#define AIROHA_PCS_PMA_LCPLL_TDC_PCW_2\t\t0x4c\n+#define   AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_EPON GENMASK(30, 0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_0 0x68\n+#define   AIROHA_PCS_PMA_X_MAX\t\t\tGENMASK(26, 16)\n+#define   AIROHA_PCS_PMA_X_MIN\t\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_1 0x6c\n+#define   AIROHA_PCS_PMA_INDEX_MODE\t\tBIT(16)\n+#define   AIROHA_PCS_PMA_Y_MAX\t\t\tGENMASK(14, 8)\n+#define   AIROHA_PCS_PMA_Y_MIN\t\t\tGENMASK(6, 0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_2 0x70\n+#define   AIROHA_PCS_PMA_EYEDUR\t\t\tGENMASK(19, 0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_3 0x74\n+#define   AIROHA_PCS_PMA_EYE_NEXTPTS\t\tBIT(16)\n+#define   AIROHA_PCS_PMA_EYE_NEXTPTS_TOGGLE\tBIT(8)\n+#define   AIROHA_PCS_PMA_EYE_NEXTPTS_SEL\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_0 0x78\n+#define   AIROHA_PCS_PMA_EYECNT_VTH\t\tGENMASK(15, 8)\n+#define   AIROHA_PCS_PMA_EYECNT_HTH\t\tGENMASK(7, 0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_1 0x7c\n+#define   AIROHA_PCS_PMA_EO_VTH\t\t\tGENMASK(23, 16)\n+#define   AIROHA_PCS_PMA_EO_HTH\t\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0 0x80\n+#define   AIROHA_PCS_PMA_EYE_MASK\t\tGENMASK(31, 24)\n+#define   AIROHA_PCS_PMA_CNTFOREVER\t\tBIT(16)\n+#define   AIROHA_PCS_PMA_CNTLEN\t\t\tGENMASK(9, 0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1\t0x84\n+#define   AIROHA_PCS_PMA_FORCE_EYEDUR_INIT_B\tBIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_EYEDUR_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_DISB_EYEDUR_INIT_B\tBIT(8)\n+#define   AIROHA_PCS_PMA_DISB_EYEDUR_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2\t0x88\n+#define   AIROHA_PCS_PMA_DATA_SHIFT\t\tBIT(8)\n+#define   AIROHA_PCS_PMA_EYECNT_FAST\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0\t0x8c\n+#define   AIROHA_PCS_PMA_RX_OS_START\t\tGENMASK(23, 8)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT\t\tGENMASK(2, 0)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)\n+#define   AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4\tFIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1\t0x90\n+#define   AIROHA_PCS_PMA_RX_PICAL_END\t\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_RX_PICAL_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2\t0x94\n+#define   AIROHA_PCS_PMA_RX_PDOS_END\t\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_RX_PDOS_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3\t0x98\n+#define   AIROHA_PCS_PMA_RX_FEOS_END\t\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_RX_FEOS_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4\t0x9c\n+#define   AIROHA_PCS_PMA_RX_SDCAL_END\t\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_RX_SDCAL_START\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5\t0x100\n+#define   AIROHA_PCS_PMA_RX_RDY\t\t\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_RX_BLWC_RDY_EN\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6\t0x104\n+#define   AIROHA_PCS_PMA_RX_OS_END\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0 0x108\n+#define   AIROHA_PCS_PMA_DISB_RX_FEOS_EN\tBIT(24)\n+#define   AIROHA_PCS_PMA_DISB_RX_PDOS_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_DISB_RX_PICAL_EN\tBIT(8)\n+#define   AIROHA_PCS_PMA_DISB_RX_OS_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c\n+#define   AIROHA_PCS_PMA_DISB_RX_RDY\t\tBIT(24)\n+#define   AIROHA_PCS_PMA_DISB_RX_BLWC_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_DISB_RX_OS_RDY\t\tBIT(8)\n+#define   AIROHA_PCS_PMA_DISB_RX_SDCAL_EN\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0 0x110\n+#define   AIROHA_PCS_PMA_FORCE_RX_FEOS_EN\tBIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_RX_PDOS_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_RX_PICAL_EN\tBIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_RX_OS_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114\n+#define   AIROHA_PCS_PMA_FORCE_RX_RDY\t\tBIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_RX_BLWC_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_RX_OS_RDY\tBIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_RX_SDCAL_EN\tBIT(0)\n+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_0\t\t0x118\n+#define   AIROHA_PCS_PMA_VEO_MASK\t\tGENMASK(31, 24)\n+#define   AIROHA_PCS_PMA_HEO_MASK\t\tGENMASK(18, 8)\n+#define   AIROHA_PCS_PMA_EQ_EN_DELAY\t\tGENMASK(7, 0)\n+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_1\t\t0x11c\n+#define   AIROHA_PCS_PMA_B_ZERO_SEL\t\tBIT(24)\n+#define   AIROHA_PCS_PMA_HEO_EMPHASIS\t\tBIT(16)\n+#define   AIROHA_PCS_PMA_A_MGAIN\t\tBIT(8)\n+#define   AIROHA_PCS_PMA_A_LGAIN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2\t\t0x120\n+#define   AIROHA_PCS_PMA_EQ_DEBUG_SEL\t\tGENMASK(17, 16)\n+#define   AIROHA_PCS_PMA_FOM_NUM_ORDER\t\tGENMASK(12, 8)\n+#define   AIROHA_PCS_PMA_A_SEL\t\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FEOS\t\t0x144\n+#define   AIROHA_PCS_PMA_EQ_FORCE_BLWC_FREEZE\tBIT(8)\n+#define   AIROHA_PCS_PMA_LFSEL\t\t\tGENMASK(7, 0)\n+#define AIROHA_PCS_PMA_SS_RX_BLWC\t\t0x148\n+#define   AIROHA_PCS_PMA_EQ_BLWC_CNT_BOT_LIM\tGENMASK(29, 23)\n+#define   AIROHA_PCS_PMA_EQ_BLWC_CNT_TOP_LIM\tGENMASK(22, 16)\n+#define   AIROHA_PCS_PMA_EQ_BLWC_GAIN\t\tGENMASK(11, 8)\n+#define   AIROHA_PCS_PMA_EQ_BLWC_POL\t\tBIT(0)\n+#define   AIROHA_PCS_PMA_EQ_BLWC_POL_NORMAL\tFIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x0)\n+#define   AIROHA_PCS_PMA_EQ_BLWC_POL_INVERSION\tFIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x1)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1\t\t0x14c\n+#define   AIROHA_PCS_PMA_UNLOCK_CYCLECNT\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_LOCK_CYCLECNT\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2\t\t0x150\n+#define   AIROHA_PCS_PMA_LOCK_TARGET_END\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_LOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3\t\t0x154\n+#define   AIROHA_PCS_PMA_UNLOCK_TARGET_END\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_UNLOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4\t\t0x158\n+#define   AIROHA_PCS_PMA_LOCK_UNLOCKTH\t\tGENMASK(15, 12)\n+#define   AIROHA_PCS_PMA_LOCK_LOCKTH\t\tGENMASK(11, 8)\n+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN\tGENMASK(2, 0)\n+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)\n+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)\n+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT\tFIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)\n+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL\tFIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)\n+#define   AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)\n+#define AIROHA_PCS_PMA_RX_PI_CAL\t\t0x15c\n+#define   AIROHA_PCS_PMA_KPGAIN\t\t\tGENMASK(10, 8)\n+#define AIROHA_PCS_PMA_RX_CAL1\t\t\t0x160\n+#define   AIROHA_PCS_PMA_CAL_CYC\t\tGENMASK(25, 24)\n+#define     AIROHA_PCS_PMA_CAL_CYC_63\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x0)\n+#define     AIROHA_PCS_PMA_CAL_CYC_15\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x1)\n+#define     AIROHA_PCS_PMA_CAL_CYC_31\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x2)\n+#define     AIROHA_PCS_PMA_CAL_CYC_127\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x3)\n+#define   AIROHA_PCS_PMA_CAL_STB\t\tGENMASK(17, 16)\n+#define     AIROHA_PCS_PMA_CAL_STB_5US\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x0)\n+#define     AIROHA_PCS_PMA_CAL_STB_8US\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x1)\n+#define     AIROHA_PCS_PMA_CAL_STB_16US\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x2)\n+#define     AIROHA_PCS_PMA_CAL_STB_32US\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x3)\n+#define   AIROHA_PCS_PMA_CAL_1US_SET\t\tGENMASK(15, 8)\n+#define   AIROHA_PCS_PMA_SIM_FAST_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_CAL2\t\t\t0x164\n+#define   AIROHA_PCS_PMA_CAL_CYC_TIME\t\tGENMASK(17, 16)\n+#define   AIROHA_PCS_PMA_CAL_OUT_OS\t\tGENMASK(11, 8)\n+#define   AIROHA_PCS_PMA_CAL_OS_PULSE\t\tBIT(0)\n+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1\t\t0x16c\n+#define   AIROHA_PCS_PMA_SIGDET_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FLL_0\t\t\t0x170\n+#define   AIROHA_PCS_PMA_KBAND_KFC\t\tGENMASK(25, 24)\n+#define     AIROHA_PCS_PMA_KBAND_KFC_8\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x0)\n+#define     AIROHA_PCS_PMA_KBAND_KFC_16\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x1)\n+#define     AIROHA_PCS_PMA_KBAND_KFC_32\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x2)\n+#define     AIROHA_PCS_PMA_KBAND_KFC_64\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x3)\n+#define   AIROHA_PCS_PMA_FPKDIV\t\t\tGENMASK(18, 8)\n+#define   AIROHA_PCS_PMA_KBAND_PREDIV\t\tGENMASK(2, 0)\n+#define     AIROHA_PCS_PMA_KBAND_PREDIV_1\tFIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x0)\n+#define     AIROHA_PCS_PMA_KBAND_PREDIV_2\tFIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x1)\n+#define     AIROHA_PCS_PMA_KBAND_PREDIV_4\tFIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x2)\n+#define     AIROHA_PCS_PMA_KBAND_PREDIV_8\tFIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x3)\n+#define AIROHA_PCS_PMA_RX_FLL_1\t\t\t0x174\n+#define   AIROHA_PCS_PMA_SYMBOL_WD\t\tGENMASK(26, 24)\n+#define   AIROHA_PCS_PMA_SETTLE_TIME_SEL\tGENMASK(18, 16)\n+#define   AIROHA_PCS_PMA_LPATH_IDAC\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_RX_FLL_2\t\t\t0x178\n+#define   AIROHA_PCS_PMA_CK_RATE\t\tGENMASK(18, 16)\n+#define   AIROHA_PCS_PMA_CK_RATE_20\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)\n+#define   AIROHA_PCS_PMA_CK_RATE_10\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)\n+#define   AIROHA_PCS_PMA_CK_RATE_5\t\tFIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)\n+#define   AIROHA_PCS_PMA_AMP\t\t\tGENMASK(10, 8)\n+#define   AIROHA_PCS_PMA_PRBS_SEL\t\tGENMASK(2, 0)\n+#define AIROHA_PCS_PMA_RX_FLL_5\t\t\t0x184\n+#define   AIROHA_PCS_PMA_FLL_IDAC_MIN\t\tGENMASK(26, 16)\n+#define   AIROHA_PCS_PMA_FLL_IDAC_MAX\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_RX_FLL_6\t\t\t0x188\n+#define  AIROHA_PCS_PMA_LNX_SW_FLL_4_LATCH_EN\tBIT(24)\n+#define  AIROHA_PCS_PMA_LNX_SW_FLL_3_LATCH_EN\tBIT(16)\n+#define  AIROHA_PCS_PMA_LNX_SW_FLL_2_LATCH_EN\tBIT(8)\n+#define  AIROHA_PCS_PMA_LNX_SW_FLL_1_LATCH_EN\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FLL_B\t\t\t0x19c\n+#define   AIROHA_PCS_PMA_LOAD_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_PDOS_CTRL_0\t\t0x200\n+#define   AIROHA_PCS_PMA_SAP_SEL\t\tGENMASK(18, 16)\n+#define     AIROHA_PCS_PMA_SAP_SEL_SHIFT_6\tFIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x0)\n+#define     AIROHA_PCS_PMA_SAP_SEL_SHIFT_7\tFIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x1)\n+#define     AIROHA_PCS_PMA_SAP_SEL_SHIFT_8\tFIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x2)\n+#define     AIROHA_PCS_PMA_SAP_SEL_SHIFT_9\tFIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x3)\n+#define     AIROHA_PCS_PMA_SAP_SEL_SHIFT_10\tFIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x4)\n+#define   AIROHA_PCS_PMA_EYE_BLWC_ADD\t\tBIT(8)\n+#define   AIROHA_PCS_PMA_DATA_BLWC_ADD\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_RESET_0\t\t0x204\n+#define   AIROHA_PCS_PMA_CAL_RST_B\t\tBIT(24)\n+#define   AIROHA_PCS_PMA_EQ_PI_CAL_RST_B\tBIT(16)\n+#define   AIROHA_PCS_PMA_FEOS_RST_B\t\tBIT(8)\n+#define AIROHA_PCS_PMA_RX_RESET_1\t\t0x208\n+#define   AIROHA_PCS_PMA_SIGDET_RST_B\t\tBIT(8)\n+#define   AIROHA_PCS_PMA_PDOS_RST_B\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DEBUG_0\t\t0x20c\n+#define   AIROHA_PCS_PMA_RO_TOGGLE\t\tBIT(24)\n+#define AIROHA_PCS_PMA_BISTCTL_CONTROL\t\t0x210\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL\tGENMASK(4, 0)\n+/*        AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x0) */\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS7\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x1)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS9\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x2)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS15\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x3)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS23\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x4)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS31\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x5)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_HFTP\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x6)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_MFTP\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x7)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x8)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_5_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x9)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xa)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xb)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_8_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xc)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xd)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xe)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xf)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PROG_80 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x10)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_1\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x11)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x12)\n+#define   AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS11\tFIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x13)\n+#define AIROHA_PCS_PMA_BISTCTL_ALIGN_PAT\t0x214\n+#define AIROHA_PCS_PMA_BISTCTL_POLLUTION\t0x220\n+#define   AIROHA_PCS_PMA_BIST_TX_DATA_POLLUTION_LATCH BIT(16)\n+#define AIROHA_PCS_PMA_BISTCTL_PRBS_INITIAL_SEED 0x224\n+#define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD 0x230\n+#define   AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD_MASK GENMASK(15, 0)\n+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_2\t\t0x23c\n+#define   AIROHA_PCS_PMA_PI_CAL_DATA_OUT\tGENMASK(22, 16)\n+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_5\t\t0x248\n+#define   AIROHA_PCS_PMA_VEO_RDY\t\tBIT(24)\n+#define   AIROHA_PCS_PMA_HEO_RDY\t\tBIT(16)\n+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_9\t\t0x258\n+#define   AIROHA_PCS_PMA_EO_Y_DONE\t\tBIT(24)\n+#define   AIROHA_PCS_PMA_EO_X_DONE\t\tBIT(16)\n+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_10\t0x25c\n+#define   AIROHA_PCS_PMA_EYE_EL\t\t\tGENMASK(26, 16)\n+#define   AIROHA_PCS_PMA_EYE_ER\t\t\tGENMASK(10, 0)\n+#define AIROHA_PCS_PMA_TX_RST_B\t\t\t0x260\n+#define   AIROHA_PCS_PMA_TXCALIB_RST_B\t\tBIT(8)\n+#define   AIROHA_PCS_PMA_TX_TOP_RST_B\t\tBIT(0)\n+#define AIROHA_PCS_PMA_TX_CALIB_0\t\t0x264\n+#define   AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL GENMASK(25, 24)\n+#define   AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL_EN BIT(16)\n+#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_11\t0x290\n+#define   AIROHA_PCS_PMA_EYE_EB\t\t\tGENMASK(14, 8)\n+#define   AIROHA_PCS_PMA_EYE_EU\t\t\tGENMASK(6, 0)\n+#define AIROHA_PCS_PMA_RX_FORCE_MODE_0\t\t0x294\n+#define   AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL GENMASK(1, 0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_0\t\t0x300\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_CDR_LPF_RSTB BIT(24)\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_GAIN_CTRL BIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_1\t\t0x304\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E0\tBIT(24)\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D1\tBIT(16)\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D0\tBIT(8)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_2\t\t0x308\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_CDR_PR_PIEYE BIT(24)\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_VOS BIT(16)\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_EYE BIT(8)\n+#define   AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E1 BIT(0)\n+#define AIROHA_PCS_PMA_RX_FORCE_MODE_3\t\t0x30c\n+#define   AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FORCE_MODE_6\t\t0x318\n+#define   AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN\tBIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_EYECNT_RDY\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_3\t\t0x31c\n+#define   AIROHA_PCS_PMA_DISB_RQ_PI_CAL_RDY\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_4\t\t0x320\n+#define   AIROHA_PCS_PMA_DISB_BLWC_OFFSET\tBIT(24)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_5\t\t0x324\n+#define   AIROHA_PCS_PMA_DISB_RX_OR_PICAL_EN\tBIT(24)\n+#define   AIROHA_PCS_PMA_DISB_EYECNT_RDY\tBIT(16)\n+#define AIROHA_PCS_PMA_RX_FORCE_MODE_7\t\t0x328\n+#define   AIROHA_PCS_PMA_FORCE_PDOS_RX_RST_B\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB BIT(0)\n+#define AIROHA_PCS_PMA_RX_FORCE_MODE_8\t\t0x32c\n+#define   AIROHA_PCS_PMA_FORCE_EYECNT_RX_RST_B\tBIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_FEOS_RX_RST_B\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SDCAL_REF_RST_B\tBIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_BLWC_RX_RST_B\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9\t\t0x330\n+#define   AIROHA_PCS_PMA_FORCE_EYE_TOP_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O\tBIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_FBCK_LOCK\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_6\t\t0x334\n+#define   AIROHA_PCS_PMA_DISB_PDOS_RX_RST_B\tBIT(16)\n+#define   AIROHA_PCS_PMA_DISB_RX_AND_PICAL_RSTB\tBIT(8)\n+#define   AIROHA_PCS_PMA_DISB_REF_AND_PICAL_RSTB BIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_7\t\t0x338\n+#define   AIROHA_PCS_PMA_DISB_EYECNT_RX_RST_B\tBIT(24)\n+#define   AIROHA_PCS_PMA_DISB_FEOS_RX_RST_B\tBIT(16)\n+#define   AIROHA_PCS_PMA_DISB_SDCAL_REF_RST_B\tBIT(8)\n+#define   AIROHA_PCS_PMA_DISB_BLWC_RX_RST_B\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_DISB_MODE_8\t\t0x33c\n+#define   AIROHA_PCS_PMA_DISB_EYE_TOP_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_DISB_EYE_RESET_PLU_O\tBIT(8)\n+#define   AIROHA_PCS_PMA_DISB_FBCK_LOCK\t\tBIT(0)\n+#define AIROHA_PCS_PMA_SS_BIST_1\t\t0x344\n+#define   AIROHA_PCS_PMA_LNX_BISTCTL_BIT_ERROR_RST_SEL BIT(24)\n+#define   AIROHA_PCS_PMA_ANLT_PX_LNX_LT_LOS\tBIT(0)\n+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0\t0x34c\n+#define   AIROHA_PCS_PMA_XPON_CDR_PD_PWDB\tBIT(24)\n+#define   AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB\tBIT(16)\n+#define   AIROHA_PCS_PMA_XPON_CDR_PW_PWDB\tBIT(8)\n+#define   AIROHA_PCS_PMA_XPON_RX_FE_PWDB\tBIT(0)\n+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1\t0x350\n+#define   AIROHA_PCS_PMA_RX_SIDGET_PWDB\t\tBIT(0)\n+#define AIROHA_PCS_PMA_DIG_RESERVE_0\t\t0x360\n+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1\t0x374\n+#define   AIROHA_PCS_PMA_XPON_RX_RATE_CTRL\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0\t\t0x38c\n+#define   AIROHA_PCS_PMA_RX_SYS_EN_SEL\t\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0\t0x390\n+#define   AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1\t0x394\n+#define   AIROHA_PCS_PMA_PLL_LOCK_TARGET_END\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3\t0x39c\n+#define   AIROHA_PCS_PMA_PLL_LOCK_LOCKTH\tGENMASK(11, 8)\n+#define AIROHA_PCS_PMA_ADD_CLKPATH_RST_0\t0x410\n+#define   AIROHA_PCS_PMA_CLKPATH_RSTB_CK\tBIT(8)\n+#define   AIROHA_PCS_PMA_CLKPATH_RST_EN\t\tBIT(0)\n+#define AIROHA_PCS_PMA_ADD_XPON_MODE_1\t\t0x414\n+#define   AIROHA_PCS_PMA_TX_BIST_GEN_EN\t\tBIT(16)\n+#define   AIROHA_PCS_PMA_R2T_MODE\t\tBIT(8)\n+#define AIROHA_PCS_PMA_ADD_RX2ANA_1\t\t0x424\n+#define   AIROHA_PCS_PMA_RX_DAC_E0\t\tGENMASK(30, 24)\n+#define   AIROHA_PCS_PMA_RX_DAC_D1\t\tGENMASK(22, 16)\n+#define   AIROHA_PCS_PMA_RX_DAC_D0\t\tGENMASK(14, 8)\n+#define   AIROHA_PCS_PMA_RX_DAC_EYE\t\tGENMASK(6, 0)\n+#define AIROHA_PCS_PMA_ADD_RX2ANA_2\t\t0x428\n+#define   AIROHA_PCS_PMA_RX_FEOS_OUT\t\tGENMASK(13, 8)\n+#define   AIROHA_PCS_PMA_RX_DAC_E1\t\tGENMASK(6, 0)\n+#define AIROHA_PCS_PMA_PON_TX_COUNTER_0\t\t0x440\n+#define   AIROHA_PCS_PMA_TXCALIB_5US\t\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_TXCALIB_50US\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_PON_TX_COUNTER_1\t\t0x444\n+#define   AIROHA_PCS_PMA_TX_HSDATA_EN_WAIT\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_TX_CK_EN_WAIT\t\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_PON_TX_COUNTER_2\t\t0x448\n+#define   AIROHA_PCS_PMA_TX_SERDES_RDY_WAIT\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_TX_POWER_ON_WAIT\tGENMASK(15, 0)\n+#define AIROHA_PCS_PMA_SW_RST_SET\t\t0x460\n+#define   AIROHA_PCS_PMA_SW_XFI_RXMAC_RST_N\tBIT(17)\n+#define   AIROHA_PCS_PMA_SW_XFI_TXMAC_RST_N\tBIT(16)\n+#define   AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N\tBIT(11)\n+#define   AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N\tBIT(10)\n+#define   AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)\n+#define   AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N\tBIT(8)\n+#define   AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N\tBIT(7)\n+#define   AIROHA_PCS_PMA_SW_TX_FIFO_RST_N\tBIT(6)\n+#define   AIROHA_PCS_PMA_SW_REF_RST_N\t\tBIT(5)\n+#define   AIROHA_PCS_PMA_SW_ALLPCS_RST_N\tBIT(4)\n+#define   AIROHA_PCS_PMA_SW_PMA_RST_N\t\tBIT(3)\n+#define   AIROHA_PCS_PMA_SW_TX_RST_N\t\tBIT(2)\n+#define   AIROHA_PCS_PMA_SW_RX_RST_N\t\tBIT(1)\n+#define   AIROHA_PCS_PMA_SW_RX_FIFO_RST_N\tBIT(0)\n+#define AIROHA_PCS_PMA_TX_DLY_CTRL\t\t0x468\n+#define   AIROHA_PCS_PMA_OUTBEN_DATA_MODE\tGENMASK(30, 28)\n+#define   AIROHA_PCS_PMA_TX_BEN_EXTEN_FTUNE\tGENMASK(23, 16)\n+#define   AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE\tGENMASK(14, 8)\n+#define   AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE\tGENMASK(6, 0)\n+#define AIROHA_PCS_PMA_XPON_INT_EN_3\t\t0x474\n+#define   AIROHA_PCS_PMA_RX_SIGDET_INT_EN\tBIT(16)\n+#define AIROHA_PCS_PMA_XPON_INT_STA_3\t\t0x47c\n+#define   AIROHA_PCS_PMA_RX_SIGDET_INT\t\tBIT(16)\n+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL\t\t0x48c\n+/* 4ref_ck step:\n+ * - 0x1 4ref_ck\n+ * - 0x2 8ref_ck\n+ * - 0x3 12ref_ck\n+ * ...\n+ */\n+#define   AIROHA_PCS_PMA_L2D_TRIG_EQ_EN_TIME\tGENMASK(15, 8)\n+#define   AIROHA_PCS_PMA_OS_RDY_LATCH\t\tBIT(1)\n+#define   AIROHA_PCS_PMA_DISB_LEQ\t\tBIT(0)\n+#define AIROHA_PCS_PMA_RX_FREQDET\t\t0x530\n+#define   AIROHA_PCS_PMA_FL_OUT\t\t\tGENMASK(31, 16)\n+#define   AIROHA_PCS_PMA_FBCK_LOCK\t\tBIT(0)\n+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL\t0x580\n+#define   AIROHA_PCS_PMA_PON_TX_RATE_CTRL\tGENMASK(1, 0)\n+#define AIROHA_PCS_PMA_MD32_MEM_CLK_CTRL\t0x60c\n+#define   AIROHA_PCS_PMA_MD32PM_CK_SEL\t\tGENMASK(31, 0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN\t0x768\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)\n+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED\t\t0x76c\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL\tBIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_OSR_SEL\tGENMASK(17, 16)\n+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B\t\t0x778\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1\tGENMASK(20, 16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL\t\t0x77c\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL\tGENMASK(2, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1\t\t0x780\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2\tGENMASK(20, 16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL\t\t0x784\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE\tGENMASK(22, 16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_FLL_COR\t0x790\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_DAC_EYE BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_DAC_EYE\tGENMASK(22, 16)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC\t\t0x794\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC\tGENMASK(10, 0)\n+#define     AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)\n+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW\t0x798\n+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW\tGENMASK(30, 0)\n+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS\t\t0x79c\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS\tBIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_FE_VOS\tGENMASK(5, 0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW\t0x800\n+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW\tGENMASK(30, 0)\n+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS\t\t0x80c\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON\tBIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB\t\t0x814\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA\t0x818\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB\t\t0x81c\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN\t0x820\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB\t0x824\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN\t0x828\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN\tBIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN_RSTB\t0x83c\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_CKON BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_CKON\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_RX_OSCAL_EN\t\t0x840\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_RSTB BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_RSTB\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_EN\tBIT(0)\n+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B\t0x84c\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B\t BIT(0)\n+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN\t0x854\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN\tBIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_TXPLL_KBAND_LOAD_EN\t0x858\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_KBAND_LOAD_EN BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_KBAND_LOAD_EN BIT(0)\n+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW_CHG\t0x864\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW_CHG BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW_CHG BIT(0)\n+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN\t\t0x874\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL\tBIT(16)\n+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL\t\t0x88c\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)\n+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB\t\t0x894\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN\tBIT(16)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB\t BIT(0)\n+#define AIROHA_PCS_PMA_PXP_RX_SIGDET_CAL_EN\t0x898\n+#define   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_CAL_EN BIT(8)\n+#define   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_CAL_EN BIT(0)\n+#define AIROHA_PCS_PMA_DIG_RESERVE_12\t\t0x8b8\n+#define   AIROHA_PCS_PMA_RESERVE_12_FEOS_0\tBIT(0)\n+#define AIROHA_PCS_PMA_DIG_RESERVE_24\t\t0x8fc\n+#define   AIROHA_PCS_PMA_FORCE_RX_GEARBOX\tBIT(12)\n+#define   AIROHA_PCS_PMA_FORCE_SEL_RX_GEARBOX\tBIT(8)\n+\n+#define AIROHA_PCS_MAX_CALIBRATION_TRY\t\t50\n+#define AIROHA_PCS_MAX_NUM_RSTS\t\t\t2\n+\n+enum pon_eo_buf_vals {\n+\tEYE_EU,\n+\tEYE_EB,\n+\tDAC_D0,\n+\tDAC_D1,\n+\tDAC_E0,\n+\tDAC_E1,\n+\tDAC_EYE,\n+\tFEOS,\n+\n+\tEO_BUF_MAX,\n+};\n+\n+enum xfi_port_type {\n+\tAIROHA_PCS_ETH,\n+\tAIROHA_PCS_PON,\n+};\n+\n+struct airoha_pcs_priv {\n+\tstruct udevice *dev;\n+\tconst struct airoha_pcs_match_data *data;\n+\tphy_interface_t interface;\n+\n+\tstruct regmap *scu;\n+\n+\tstruct regmap *xfi_mac;\n+\tstruct regmap *hsgmii_an;\n+\tstruct regmap *hsgmii_pcs;\n+\tstruct regmap *hsgmii_rate_adp;\n+\tstruct regmap *multi_sgmii;\n+\tstruct regmap *usxgmii_pcs;\n+\n+\tstruct regmap *xfi_pma;\n+\tstruct regmap *xfi_ana;\n+\n+\tstruct reset_ctl *xfi_rst;\n+\tstruct reset_ctl_bulk rsts;\n+};\n+\n+struct airoha_pcs_match_data {\n+\tenum xfi_port_type port_type;\n+\n+\tbool hibernation_workaround;\n+\tbool usxgmii_ber_time_fixup;\n+\tbool usxgmii_rx_gb_out_vld_tweak;\n+\tbool usxgmii_xfi_mode_sel;\n+\n+\tint (*bringup)(struct airoha_pcs_priv *priv,\n+\t\t\tphy_interface_t interface);\n+\tvoid (*link_up)(struct airoha_pcs_priv *priv);\n+};\n+\n+void airoha_pcs_pre_config(struct udevice *dev, phy_interface_t interface);\n+int airoha_pcs_post_config(struct udevice *dev, phy_interface_t interface);\n+int airoha_pcs_config(struct udevice *dev, bool neg_mode,\n+\t\t      phy_interface_t interface,\n+\t\t      const unsigned long *advertising,\n+\t\t      bool permit_pause_to_mac);\n+void airoha_pcs_link_up(struct udevice *dev, unsigned int neg_mode,\n+\t\t\tphy_interface_t interface, int speed, int duplex);\n+void airoha_pcs_link_down(struct udevice *dev);\n+\n+#ifdef CONFIG_PCS_AIROHA_AN7581\n+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,\n+\t\t       phy_interface_t interface);\n+\n+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv);\n+#else\n+static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t     phy_interface_t interface)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv)\n+{\n+}\n+#endif\ndiff --git a/drivers/net/airoha/pcs-an7581.c b/drivers/net/airoha/pcs-an7581.c\nnew file mode 100644\nindex 00000000000..a95eb8d54d1\n--- /dev/null\n+++ b/drivers/net/airoha/pcs-an7581.c\n@@ -0,0 +1,1369 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2024 AIROHA Inc\n+ * Author: Christian Marangi <ansuelsmth@gmail.com>\n+ */\n+#include <dm.h>\n+#include <dm/device_compat.h>\n+#include <regmap.h>\n+\n+#include \"pcs-airoha.h\"\n+\n+static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t     phy_interface_t interface)\n+{\n+\tu32 kband_vref;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tkband_vref = 0x10;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tkband_vref = 0xf;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* Setup LDO */\n+\tudelay(200);\n+\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,\n+\t\t\tAIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);\n+\n+\t/* Setup RSTB */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_RST_DLY,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);\n+\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,\n+\t\t\tAIROHA_PCS_ANA_JCPLL_PLL_RSTB);\n+\n+\t/* Enable PLL force selection and Force Disable */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);\n+\n+\t/* Setup SDM */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SDM_DI_EN,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SDM_OUT |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SDM_ORD |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SDM_MODE |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SDM_IFM,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_MODE, 0x0));\n+\n+\tregmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,\n+\t\t\t  AIROHA_PCS_ANA_JCPLL_SDM_HREN);\n+\n+\t/* Setup SSC */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SSC_PERIOD |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SSC_DELTA,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_PERIOD, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA, 0x0));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA1, 0x0));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_SSC_EN |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x0));\n+\n+\t/* Setup LPF */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_CHP_IOFST |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_CHP_IBIAS |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IOFST, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IBIAS, 0x18));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_LPF_BWR |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_LPF_BP |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_LPF_BC |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_LPF_BR,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWR, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BP, 0x10) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BC, 0x1f) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BR, BIT(3) | BIT(1)));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_LPF_BWC,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWC, 0x0));\n+\n+\t/* Setup VCO */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_CFIX,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR, 0x4) |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_CFIX, 0x1));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H, 0x3) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x3));\n+\n+\t/* Setup PCW */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);\n+\n+\t/* Setup DIV */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCODIV,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_VCODIV_1);\n+\n+\t/* Setup KBand */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_KBAND_KS |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_KBAND_KF |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_KBAND_KFC,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KS, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KF, 0x3) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KFC, 0x0));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_KBAND_DIV |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_KBAND_CODE |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_KBAND_OPTION,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_DIV, 0x2) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_CODE, 0xe4));\n+\n+\t/* Setup TCL */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, kband_vref));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF, 0x5) |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN,\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 |\n+\t\t\t   AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN);\n+\n+\t/* Enable PLL */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);\n+\n+\t/* Enale PLL Output */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);\n+}\n+\n+static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t     phy_interface_t interface)\n+{\n+\tu32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;\n+\tu32 vco_cfix;\n+\tu32 pcw;\n+\tu32 tcl_amp_vref;\n+\tbool sdm_hren;\n+\tbool vcodiv;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tlpf_chp_ibias = 0xf;\n+\t\tlpf_bp = BIT(1);\n+\t\tlpf_bwr = BIT(3) | BIT(1) | BIT(0);\n+\t\tlpf_bwc = BIT(4) | BIT(3);\n+\t\tvco_cfix = BIT(1) | BIT(0);\n+\t\tpcw = BIT(27);\n+\t\ttcl_amp_vref = BIT(3) | BIT(1) | BIT(0);\n+\t\tvcodiv = false;\n+\t\tsdm_hren = false;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tlpf_chp_ibias = 0xa;\n+\t\tlpf_bp = BIT(2) | BIT(0);\n+\t\tlpf_bwr = 0;\n+\t\tlpf_bwc = 0;\n+\t\tvco_cfix = 0;\n+\t\tpcw = BIT(27) | BIT(25);\n+\t\ttcl_amp_vref = BIT(3) | BIT(2) | BIT(0);\n+\t\tvcodiv = true;\n+\t\tsdm_hren = false;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tlpf_chp_ibias = 0xf;\n+\t\tlpf_bp = BIT(1);\n+\t\tlpf_bwr = BIT(3) | BIT(1) | BIT(0);\n+\t\tlpf_bwc = BIT(4) | BIT(3);\n+\t\tvco_cfix = BIT(0);\n+\t\tpcw = BIT(27) | BIT(22);\n+\t\ttcl_amp_vref = BIT(3) | BIT(1) | BIT(0);\n+\t\tvcodiv = false;\n+\t\tsdm_hren = true;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* Setup VCO LDO Output */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_LDO_OUT,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1));\n+\n+\t/* Setup RSTB */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_PLL_RSTB |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_RST_DLY |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_REFIN_DIV |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_PLL_RSTB |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL);\n+\n+\t/* Enable PLL force selection and Force Disable */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);\n+\n+\t/* Setup SDM */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_MODE |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_IFM |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_DI_EN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_HREN |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_OUT |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_ORD,\n+\t\t\t   (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);\n+\n+\t/* Setup SSC */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SSC_DELTA |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SSC_DELTA1,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0));\n+\n+\tregmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN,\n+\t\t\t  AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN |\n+\t\t\t  AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI |\n+\t\t\t  AIROHA_PCS_ANA_TXPLL_SSC_EN);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_SSC_PERIOD,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0));\n+\n+\t/* Setup LPF */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_LPF_BC |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_LPF_BR |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_CHP_IOFST |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_CHP_IBIAS,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, 0x5) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, lpf_chp_ibias));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_LPF_BWC |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_LPF_BWR |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_LPF_BP,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, lpf_bwc) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, lpf_bp));\n+\n+\t/* Setup VCO */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_VCO_CFIX,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN);\n+\n+\t/* Setup PCW */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);\n+\n+\t/* Setup KBand */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_KBAND_KF |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_KBAND_KFC |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_KBAND_DIV |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_KBAND_CODE,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x4) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_KBAND_KS,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1));\n+\n+\tregmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,\n+\t\t\t  AIROHA_PCS_ANA_TXPLL_KBAND_OPTION);\n+\n+\t/* Setup DIV */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_POSTDIV_EN,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_VCODIV,\n+\t\t\t   vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :\n+\t\t\t\t    AIROHA_PCS_ANA_TXPLL_VCODIV_1);\n+\n+\t/* Setup TCL */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN,\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 |\n+\t\t\t   AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN);\n+\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,\n+\t\t\tAIROHA_PCS_ANA_TXPLL_TCL_AMP_EN);\n+\n+\t/* Enable PLL */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);\n+\n+\t/* Enale PLL Output */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);\n+}\n+\n+static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t  phy_interface_t interface)\n+{\n+\tu32 tx_rate_ctrl;\n+\tu32 ckin_divisor;\n+\tu32 fir_cn1, fir_c0b, fir_c1;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tckin_divisor = BIT(1);\n+\t\ttx_rate_ctrl = BIT(0);\n+\t\tfir_cn1 = 0;\n+\t\tfir_c0b = 12;\n+\t\tfir_c1 = 0;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tckin_divisor = BIT(2);\n+\t\ttx_rate_ctrl = BIT(0);\n+\t\tfir_cn1 = 0;\n+\t\tfir_c0b = 11;\n+\t\tfir_c1 = 1;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tckin_divisor = BIT(2) | BIT(0);\n+\t\ttx_rate_ctrl = BIT(1);\n+\t\tfir_cn1 = 1;\n+\t\tfir_c0b = 1;\n+\t\tfir_c1 = 11;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* Set TX rate ctrl */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,\n+\t\t\t   AIROHA_PCS_PMA_PON_TX_RATE_CTRL,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,\n+\t\t\t\t      tx_rate_ctrl));\n+\n+\t/* Setup TX Config */\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN,\n+\t\t\tAIROHA_PCS_ANA_TX_DMEDGEGEN_EN |\n+\t\t\tAIROHA_PCS_ANA_TX_CKLDO_EN);\n+\n+\tudelay(1);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);\n+\n+\t/* FIXME: Ask Airoha TX term is OK to reset? */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,\n+\t\t\t\t      ckin_divisor) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, 0x0));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,\n+\t\t\t\t      tx_rate_ctrl));\n+\n+\t/* Setup TX FIR Load Parameters (Reference 660mV) */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));\n+\n+\t/* Reset TX Bar */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_RST_B,\n+\t\t\tAIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);\n+}\n+\n+static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t  phy_interface_t interface)\n+{\n+\tu32 rx_rate_ctrl;\n+\tu32 osr;\n+\tu32 pr_cdr_beta_dac;\n+\tu32 cdr_pr_buf_in_sr;\n+\tbool cdr_pr_cap_en;\n+\tu32 sigdet_vth_sel;\n+\tu32 phyck_div, phyck_sel;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tosr = BIT(1) | BIT(0); /* 1.25G */\n+\t\tpr_cdr_beta_dac = BIT(3);\n+\t\trx_rate_ctrl = 0;\n+\t\tcdr_pr_cap_en = false;\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);\n+\t\tsigdet_vth_sel = BIT(2) | BIT(1);\n+\t\tphyck_div = BIT(5) | BIT(3) | BIT(0);\n+\t\tphyck_sel = BIT(0);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tosr = BIT(0); /* 2.5G */\n+\t\tpr_cdr_beta_dac = BIT(2) | BIT(1);\n+\t\trx_rate_ctrl = 0;\n+\t\tcdr_pr_cap_en = true;\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1);\n+\t\tsigdet_vth_sel = BIT(2) | BIT(1);\n+\t\tphyck_div = BIT(3) | BIT(1) | BIT(0);\n+\t\tphyck_sel = BIT(0);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tosr = 0; /* 10G */\n+\t\tcdr_pr_cap_en = false;\n+\t\tpr_cdr_beta_dac = BIT(3);\n+\t\trx_rate_ctrl = BIT(1);\n+\t\tcdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);\n+\t\tsigdet_vth_sel = BIT(1);\n+\t\tphyck_div = BIT(6) | BIT(1);\n+\t\tphyck_sel = BIT(1);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\t/* Set RX rate ctrl */\n+\tif (interface == PHY_INTERFACE_MODE_2500BASEX)\n+\t\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_2,\n+\t\t\t\t   AIROHA_PCS_PMA_CK_RATE,\n+\t\t\t\t   AIROHA_PCS_PMA_CK_RATE_10);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,\n+\t\t\t   AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl));\n+\n+\t/* Setup RX Path */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_5,\n+\t\t\t   AIROHA_PCS_PMA_FLL_IDAC_MIN |\n+\t\t\t   AIROHA_PCS_PMA_FLL_IDAC_MAX,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));\n+\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ,\n+\t\t\tAIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ |\n+\t\t\tAIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ |\n+\t\t\tAIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ |\n+\t\t\tAIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ);\n+\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB,\n+\t\t\tAIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ);\n+\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB,\n+\t\t\tAIROHA_PCS_ANA_FE_VCM_GEN_PWDB);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,\n+\t\t\tAIROHA_PCS_PMA_LCPLL_MAN_PWDB);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_AEQ_CFORCE,\n+\t\t\t   AIROHA_PCS_ANA_AEQ_OFORCE,\n+\t\t\t   AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW,\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE,\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |\n+\t\t\t   AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);\n+\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,\n+\t\t\t  AIROHA_PCS_PMA_DISB_BLWC_OFFSET);\n+\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,\n+\t\t\t  AIROHA_PCS_PMA_DISB_LEQ);\n+\n+\tregmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,\n+\t\t\t  AIROHA_PCS_ANA_CDR_PD_EDGE_DIS |\n+\t\t\t  AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,\n+\t\t\t   AIROHA_PCS_ANA_RX_DAC_MON |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_XFICK_EN |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_MONDPI_EN |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_MONDPR_EN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_MON, 0x0) |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_XFICK_EN);\n+\n+\t/* Setup FE Gain and FE Peacking */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0));\n+\n+\t/* Setup FE VOS */\n+\tif (interface != PHY_INTERFACE_MODE_USXGMII &&\n+\t    interface != PHY_INTERFACE_MODE_10GBASER)\n+\t\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,\n+\t\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |\n+\t\t\t\t   AIROHA_PCS_PMA_FORCE_DA_FE_VOS,\n+\t\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |\n+\t\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));\n+\n+\t/* Setup FLL PR FMeter (no bypass mode)*/\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,\n+\t\t\t   AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,\n+\t\t\t   AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |\n+\t\t\t   AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,\n+\t\t\t   AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));\n+\n+\t/* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */\n+\t/* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */\n+\t/* Setup REV */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_REV_0,\n+\t\t\t   AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL |\n+\t\t\t   AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL |\n+\t\t\t   AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0));\n+\n+\t/* Setup Rdy Timeout */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,\n+\t\t\t   AIROHA_PCS_PMA_RX_RDY |\n+\t\t\t   AIROHA_PCS_PMA_RX_BLWC_RDY_EN,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));\n+\n+\t/* Setup CaBoundry Init */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,\n+\t\t\t   AIROHA_PCS_PMA_RX_OS_START |\n+\t\t\t   AIROHA_PCS_PMA_OSC_SPEED_OPT,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |\n+\t\t\t   AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,\n+\t\t\t   AIROHA_PCS_PMA_RX_OS_END,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,\n+\t\t\t   AIROHA_PCS_PMA_RX_PICAL_END |\n+\t\t\t   AIROHA_PCS_PMA_RX_PICAL_START,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,\n+\t\t\t   AIROHA_PCS_PMA_RX_SDCAL_END |\n+\t\t\t   AIROHA_PCS_PMA_RX_SDCAL_START,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,\n+\t\t\t   AIROHA_PCS_PMA_RX_PDOS_END |\n+\t\t\t   AIROHA_PCS_PMA_RX_PDOS_START,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,\n+\t\t\t   AIROHA_PCS_PMA_RX_FEOS_END |\n+\t\t\t   AIROHA_PCS_PMA_RX_FEOS_START,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));\n+\n+\t/* Setup By Serdes*/\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));\n+\n+\t/* Setup RX OSR */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,\n+\t\t\t   AIROHA_PCS_ANA_CDR_PD_EDGE_DIS,\n+\t\t\t   osr ? AIROHA_PCS_ANA_CDR_PD_EDGE_DIS : 0);\n+\n+\t/* Setup CDR LPF Ratio */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,\n+\t\t\t   AIROHA_PCS_ANA_CDR_LPF_TOP_LIM |\n+\t\t\t   AIROHA_PCS_ANA_CDR_LPF_RATIO,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x20000) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO, osr));\n+\n+\t/* Setup CDR PR */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC,\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_KBAND_DIV |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_BETA_SEL |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_VCOADC_OS |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_BETA_DAC,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_KBAND_DIV, 0x4) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_SEL, 0x1) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VCOADC_OS, 0x8) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC, pr_cdr_beta_dac));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_FBKSEL |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_DAC_BAND |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL |\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_DAC_BAND, pr_cdr_beta_dac) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x6) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x6));\n+\n+\t/* Setup Eye Mon */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2,\n+\t\t\t   AIROHA_PCS_PMA_EQ_DEBUG_SEL |\n+\t\t\t   AIROHA_PCS_PMA_FOM_NUM_ORDER |\n+\t\t\t   AIROHA_PCS_PMA_A_SEL,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,\n+\t\t\t   AIROHA_PCS_PMA_DATA_SHIFT |\n+\t\t\t   AIROHA_PCS_PMA_EYECNT_FAST,\n+\t\t\t   AIROHA_PCS_PMA_EYECNT_FAST);\n+\n+\t/* Calibration Start */\n+\n+\t/* Enable SYS */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,\n+\t\t\t   AIROHA_PCS_PMA_RX_SYS_EN_SEL,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,\n+\t\t\tAIROHA_PCS_PMA_SW_LCPLL_EN);\n+\n+\tudelay(500);\n+\n+\t/* Setup FLL PR FMeter (bypass mode)*/\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,\n+\t\t\t  AIROHA_PCS_PMA_DISB_FBCK_LOCK);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,\n+\t\t\tAIROHA_PCS_PMA_FORCE_FBCK_LOCK);\n+\n+\t/* Enable CMLEQ */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN,\n+\t\t\t   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |\n+\t\t\t   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |\n+\t\t\t   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN |\n+\t\t\t   AIROHA_PCS_ANA_RX_FE_EQ_HZEN,\n+\t\t\t   AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |\n+\t\t\t   AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |\n+\t\t\t   AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN);\n+\n+\t/* Setup CDR PR */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,\n+\t\t\t   AIROHA_PCS_ANA_CDR_PR_CAP_EN |\n+\t\t\t   AIROHA_PCS_ANA_CDR_BUF_IN_SR,\n+\t\t\t   (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr));\n+\n+\t/* Setup CDR xxx Pwdb, set force and disable */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);\n+\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,\n+\t\t\t  AIROHA_PCS_PMA_XPON_CDR_PD_PWDB |\n+\t\t\t  AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |\n+\t\t\t  AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |\n+\t\t\t  AIROHA_PCS_PMA_XPON_RX_FE_PWDB);\n+\n+\t/* FIXME: Ask Airoha WHY it's cleared? */\n+\t/* regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,\n+\t *\t\t  AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);\n+\t */\n+\n+\t/* Setup SigDet */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,\n+\t\t\t   AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL |\n+\t\t\t   AIROHA_PCS_ANA_RX_SIGDET_PEAK,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, sigdet_vth_sel) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, BIT(1)));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE,\n+\t\t\t   AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, BIT(1) | BIT(0)));\n+\n+\t/* Disable SigDet Pwdb */\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,\n+\t\t\t  AIROHA_PCS_PMA_RX_SIDGET_PWDB);\n+\n+\t/* Setup PHYCK */\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,\n+\t\t\t   AIROHA_PCS_ANA_RX_TDC_CK_SEL |\n+\t\t\t   AIROHA_PCS_ANA_RX_PHYCK_RSTB |\n+\t\t\t   AIROHA_PCS_ANA_RX_PHYCK_SEL |\n+\t\t\t   AIROHA_PCS_ANA_RX_PHYCK_DIV,\n+\t\t\t   AIROHA_PCS_ANA_RX_PHYCK_RSTB |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div));\n+\n+\tregmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL,\n+\t\t\t   AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE |\n+\t\t\t   AIROHA_PCS_ANA_RX_PHY_CK_SEL,\n+\t\t\t   AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE);\n+\n+\tudelay(100);\n+\n+\t/* Enable CDR xxx Pwdb */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PD_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_CDR_PW_PWDB |\n+\t\t\tAIROHA_PCS_PMA_XPON_RX_FE_PWDB);\n+\n+\t/* Enable SigDet Pwdb */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,\n+\t\t\tAIROHA_PCS_PMA_RX_SIDGET_PWDB);\n+}\n+\n+static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t\t u32 cdr_pr_idac)\n+{\n+\tu32 val;\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,\n+\t\t\t\t      cdr_pr_idac));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t   AIROHA_PCS_PMA_FREQLOCK_DET_EN,\n+\t\t\t   AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t   AIROHA_PCS_PMA_FREQLOCK_DET_EN,\n+\t\t\t   AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);\n+\n+\tudelay(5000);\n+\n+\tregmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);\n+\n+\treturn FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);\n+}\n+\n+static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv,\n+\t\t\t\t\t  u32 target_fl_out)\n+{\n+\tunsigned int fl_out_diff = UINT_MAX;\n+\tunsigned int prcal_search;\n+\tu32 cdr_pr_idac = 0;\n+\n+\tfor (prcal_search = 0; prcal_search < 8 ; prcal_search++) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tunsigned int fl_out;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\t/* try to find the upper value by setting the last 3 bit */\n+\t\tcdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t     prcal_search);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs(fl_out - target_fl_out);\n+\t\tdev_dbg(priv->dev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\t\tif (fl_out_diff_new < fl_out_diff) {\n+\t\t\tcdr_pr_idac = cdr_pr_idac_tmp;\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\t\t}\n+\t}\n+\n+\treturn cdr_pr_idac;\n+}\n+\n+static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, u32 target_fl_out,\n+\t\t\t\t\t  u32 cdr_pr_idac_major)\n+{\n+\tunsigned int remaining_prcal_search_bits = 0;\n+\tu32 cdr_pr_idac = cdr_pr_idac_major;\n+\tunsigned int fl_out, fl_out_diff;\n+\tint best_prcal_search_bit = -1;\n+\tint prcal_search_bit;\n+\n+\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac);\n+\tfl_out_diff = abs(fl_out - target_fl_out);\n+\n+\t/* Deadline search part.\n+\t * We start from top bits to bottom as we progressively decrease the\n+\t * signal.\n+\t */\n+\tfor (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tcdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs(fl_out - target_fl_out);\n+\t\tdev_dbg(priv->dev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\t\tif (fl_out_diff_new < fl_out_diff) {\n+\t\t\tbest_prcal_search_bit = prcal_search_bit;\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\t\t}\n+\t}\n+\n+\t/* Set the idac with the best value we found and\n+\t * reset the search bit to start from bottom to top.\n+\t */\n+\tif (best_prcal_search_bit >= 0) {\n+\t\tcdr_pr_idac |= BIT(best_prcal_search_bit);\n+\t\tremaining_prcal_search_bits = best_prcal_search_bit;\n+\t\tprcal_search_bit = 0;\n+\t}\n+\n+\t/* Fine tune part.\n+\t * Test remaining bits to find an even closer signal level to target\n+\t * by increasing the signal.\n+\t */\n+\twhile (remaining_prcal_search_bits) {\n+\t\tunsigned int fl_out_diff_new;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tcdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);\n+\t\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);\n+\n+\t\t/* Use absolute values to find the closest one to target */\n+\t\tfl_out_diff_new = abs(fl_out - target_fl_out);\n+\t\t/* Assume we found the deadline when the new absolue signal difference\n+\t\t * from target is greater than the previous and the difference is at\n+\t\t * least 10% greater between the old and new value.\n+\t\t * This is to account for signal detection level tollerance making\n+\t\t * sure we are actually over a deadline (AKA we are getting farther\n+\t\t * from target)\n+\t\t */\n+\t\tdev_dbg(priv->dev, \"Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\\n\",\n+\t\t\tcdr_pr_idac_tmp, fl_out, fl_out_diff_new);\n+\t\tif (fl_out_diff_new > fl_out_diff &&\n+\t\t    (abs(fl_out_diff_new - fl_out_diff) * 100) / fl_out_diff > 10) {\n+\t\t\t/* Exit early if we are already at the deadline */\n+\t\t\tif (prcal_search_bit == 0)\n+\t\t\t\tbreak;\n+\n+\t\t\t/* We found the deadline, set the value to the previous\n+\t\t\t * bit, and reset the loop to fine tune with the\n+\t\t\t * remaining values.\n+\t\t\t */\n+\t\t\tcdr_pr_idac |= BIT(prcal_search_bit - 1);\n+\t\t\tremaining_prcal_search_bits = prcal_search_bit - 1;\n+\t\t\tprcal_search_bit = 0;\n+\t\t} else {\n+\t\t\t/* Update the signal level diff and try the next bit */\n+\t\t\tfl_out_diff = fl_out_diff_new;\n+\n+\t\t\t/* If we didn't found the deadline, set the last bit\n+\t\t\t * and reset the loop to fine tune with the remainig\n+\t\t\t * values.\n+\t\t\t */\n+\t\t\tif (prcal_search_bit == remaining_prcal_search_bits - 1) {\n+\t\t\t\tcdr_pr_idac |= BIT(prcal_search_bit);\n+\t\t\t\tremaining_prcal_search_bits = prcal_search_bit;\n+\t\t\t\tprcal_search_bit = 0;\n+\t\t\t} else {\n+\t\t\t\tprcal_search_bit++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn cdr_pr_idac;\n+}\n+\n+static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv,\n+\t\t\t\tphy_interface_t interface)\n+{\n+\tu32 cdr_pr_idac_major, cdr_pr_idac;\n+\tunsigned int fl_out, fl_out_diff;\n+\n+\tu32 target_fl_out;\n+\tu32 cyclecnt;\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_SGMII:  /* DS_1.25G      / US_1.25G  */\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\ttarget_fl_out = 0xa3d6;\n+\t\tcyclecnt = 32767;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G   / US_9.95328G */\n+\t\ttarget_fl_out = 0xa000;\n+\t\tcyclecnt = 20000;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G  / US_1.25G */\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\ttarget_fl_out = 0x9edf;\n+\t\tcyclecnt = 32767;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tudelay(100);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,\n+\t\t\t   AIROHA_PCS_PMA_LOCK_TARGET_END |\n+\t\t\t   AIROHA_PCS_PMA_LOCK_TARGET_BEG,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,\n+\t\t\t   AIROHA_PCS_PMA_UNLOCK_CYCLECNT |\n+\t\t\t   AIROHA_PCS_PMA_LOCK_CYCLECNT,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,\n+\t\t\t   AIROHA_PCS_PMA_LOCK_UNLOCKTH |\n+\t\t\t   AIROHA_PCS_PMA_LOCK_LOCKTH,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,\n+\t\t\t   AIROHA_PCS_PMA_UNLOCK_TARGET_END |\n+\t\t\t   AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));\n+\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,\n+\t\t\tAIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t  AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\t/* Calibration logic:\n+\t * First check the major value by looping with every\n+\t * value in the last 3 bit of CDR_PR_IDAC.\n+\t * Get the signal level and save the value that is closer to\n+\t * the target.\n+\t *\n+\t * Then check each remaining 7 bits in search of the deadline\n+\t * where the signal gets farther than signal target.\n+\t *\n+\t * Finally fine tune for the remaining bits to find the one that\n+\t * produce the closest signal level.\n+\t */\n+\tcdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv,  target_fl_out);\n+\n+\tcdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, target_fl_out, cdr_pr_idac_major);\n+\n+\tfl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac);\n+\tfl_out_diff = abs(fl_out - target_fl_out);\n+\tif (fl_out_diff > 100) {\n+\t\tu32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t      cdr_pr_idac_major);\n+\t\tunsigned int fl_out_tmp, fl_out_diff_tmp;\n+\t\tu32 cdr_pr_idac_tmp;\n+\n+\t\tif (pr_idac_major > 0) {\n+\t\t\tcdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,\n+\t\t\t\t\t\t     pr_idac_major - 1);\n+\n+\t\t\tdev_dbg(priv->dev, \"Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\\n\",\n+\t\t\t\tfl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp);\n+\n+\t\t\tcdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, target_fl_out,\n+\t\t\t\t\t\t\t\t\t cdr_pr_idac_tmp);\n+\n+\t\t\tfl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);\n+\t\t\tfl_out_diff_tmp = abs(fl_out_tmp - target_fl_out);\n+\t\t\tif (fl_out_diff_tmp < fl_out_diff) {\n+\t\t\t\tfl_out = fl_out_tmp;\n+\t\t\t\tfl_out_diff = fl_out_diff_tmp;\n+\t\t\t\tcdr_pr_idac = cdr_pr_idac_tmp;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tdev_dbg(priv->dev, \"Selected CDR Pr Idac: %x Fl Out: %x\\n\", cdr_pr_idac, fl_out);\n+\tif (fl_out_diff > 100)\n+\t\tdev_dbg(priv->dev, \"Fl Out is %d far from target %d on intermediate calibration.\\n\",\n+\t\t\t fl_out_diff, target_fl_out);\n+\n+\n+\t/* Setup Load Band */\n+\tregmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,\n+\t\t\t  AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);\n+\n+\t/* Disable force of LPF C previously enabled */\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,\n+\t\t\t  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);\n+\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,\n+\t\t\t  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_B,\n+\t\t\tAIROHA_PCS_PMA_LOAD_EN);\n+\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_1,\n+\t\t\t   AIROHA_PCS_PMA_LPATH_IDAC,\n+\t\t\t   FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));\n+\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t  AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,\n+\t\t\t  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);\n+\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t  AIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tudelay(100);\n+}\n+\n+/* This is used to both calibrate and lock to signal (after a previous\n+ * calibration) after a global reset.\n+ */\n+static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv,\n+\t\t\t\t phy_interface_t interface, bool calibrate)\n+{\n+\t/* Setup LPF L2D force and disable */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);\n+\n+\t/* Calibrate IDAC and setup Load Band */\n+\tif (calibrate)\n+\t\tan7581_pcs_rx_prcal(priv, interface);\n+\n+\t/* Setup LPF RSTB force and disable */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |\n+\t\t\t   AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,\n+\t\t\t   AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);\n+\n+\tudelay(700);\n+\n+\t/* Force Enable LPF RSTB */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);\n+\n+\tudelay(100);\n+\n+\t/* Force Enable LPF L2D */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\tAIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);\n+\n+\t/* Disable LPF RSTB force bit */\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);\n+\n+\t/* Disable LPF L2D force bit */\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,\n+\t\t\t  AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);\n+}\n+\n+static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t   phy_interface_t interface)\n+{\n+\tint calibration_try = 0;\n+\tu32 val;\n+\n+\tan7581_pcs_tx_bringup(priv, interface);\n+\tan7581_pcs_rx_bringup(priv, interface);\n+\n+\tudelay(100);\n+\n+retry_calibration:\n+\tan7581_pcs_cdr_reset(priv, interface, true);\n+\n+\t/* Global reset clear */\n+\tregmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t   AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_REF_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_ALLPCS_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_PMA_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_TX_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_RX_RST_N |\n+\t\t\t   AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,\n+\t\t\t   AIROHA_PCS_PMA_SW_REF_RST_N);\n+\n+\tudelay(100);\n+\n+\t/* Global reset */\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_TX_FIFO_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_REF_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_ALLPCS_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_PMA_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_TX_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_RX_RST_N |\n+\t\t\tAIROHA_PCS_PMA_SW_RX_FIFO_RST_N);\n+\n+\tudelay(5000);\n+\n+\tan7581_pcs_cdr_reset(priv, interface, false);\n+\n+\t/* It was discovered that after a global reset and auto mode gets\n+\t * actually enabled, the fl_out from calibration might change and\n+\t * might deviates a lot from the expected value it was calibrated for.\n+\t * To correctly work, the PCS FreqDet module needs to Lock to the fl_out\n+\t * (frequency level output) or no signal can correctly be transmitted.\n+\t * This is detected by checking the FreqDet module Lock bit.\n+\t *\n+\t * If it's detected that the FreqDet module is not locked, retry\n+\t * calibration. From observation on real hardware with a 10g SFP module,\n+\t * it required a maximum of an additional calibration to actually make\n+\t * the FreqDet module to lock. Try 10 times before failing to handle\n+\t * really strange case.\n+\t */\n+\tregmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);\n+\tif (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {\n+\t\tif (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {\n+\t\t\tdev_err(priv->dev, \"No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\\n\",\n+\t\t\t\tAIROHA_PCS_MAX_CALIBRATION_TRY);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tcalibration_try++;\n+\n+\t\tdev_dbg(priv->dev, \"No FBCK Lock from FreqDet module, retry calibration.\\n\");\n+\t\tgoto retry_calibration;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t   phy_interface_t interface)\n+{\n+\tan7581_pcs_jcpll_bringup(priv, interface);\n+\n+\tudelay(200);\n+\n+\tan7581_pcs_txpll_bringup(priv, interface);\n+\n+\tudelay(200);\n+}\n+\n+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,\n+\t\t\t\t     phy_interface_t interface)\n+{\n+\t/* Enable Analog Common Lane */\n+\tregmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CMN_EN,\n+\t\t\tAIROHA_PCS_ANA_CMN_EN);\n+\n+\t/* Setup PLL */\n+\tan7581_pcs_pll_bringup(priv, interface);\n+\n+\t/* Setup PHYA */\n+\treturn an7581_pcs_phya_bringup(priv, interface);\n+}\n+\n+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv)\n+{\n+\t/* Reset TXPCS on link up */\n+\tregmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\t  AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);\n+\n+\tudelay(100);\n+\n+\tregmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,\n+\t\t\tAIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);\n+}\n",
    "prefixes": [
        "v2",
        "07/16"
    ]
}