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GET /api/patches/2195555/?format=api
{ "id": 2195555, "url": "http://patchwork.ozlabs.org/api/patches/2195555/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260211111328.1481562-2-s-joshi@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260211111328.1481562-2-s-joshi@ti.com>", "list_archive_url": null, "date": "2026-02-11T11:13:28", "name": "[1/1] board: toradex: Make A53 get RAM size from DT in K3 boards", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f1fb915d0a49dbe255834cb0dc0e4e0cb266769f", "submitter": { "id": 92409, "url": "http://patchwork.ozlabs.org/api/people/92409/?format=api", "name": "Suhaas Joshi", "email": "s-joshi@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260211111328.1481562-2-s-joshi@ti.com/mbox/", "series": [ { "id": 491822, "url": "http://patchwork.ozlabs.org/api/series/491822/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491822", "date": "2026-02-11T11:13:27", "name": "Fix regression caused in Verdin boards by 42b3ee7fa524", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491822/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195555/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195555/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=selector1 header.b=dqw/IfqJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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helo=lewvzet201.ext.ti.com; pr=C", "From": "Suhaas Joshi <s-joshi@ti.com>", "To": "<u-boot@lists.denx.de>", "CC": "<vigneshr@ti.com>, <trini@konsulko.com>, <n-francis@ti.com>,\n <s-tripathi1@ti.com>, <k-malarvizhi@ti.com>, <kamlesh@ti.com>,\n <vishalm@ti.com>, <d.schultz@phytec.de>, <w.egorov@phytec.de>,\n <francesco.dolcini@toradex.com>, <ggiordano@phytec.com>", "Subject": "[PATCH 1/1] board: toradex: Make A53 get RAM size from DT in K3\n boards", "Date": "Wed, 11 Feb 2026 16:43:28 +0530", "Message-ID": "<20260211111328.1481562-2-s-joshi@ti.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260211111328.1481562-1-s-joshi@ti.com>", "References": "<20260211111328.1481562-1-s-joshi@ti.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-C2ProcessedOrg": "333ef613-75bf-4e12-a4b1-8e3623f5dcea", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF0002BA52:EE_|SJ5PPF4B54CB2EB:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2bc468f9-7f6f-47c6-697d-08de695ea774", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|36860700013|1800799024|82310400026;", "X-Microsoft-Antispam-Message-Info": "\n Pr/yOnPNuzxptgYtJ0fdkjeS6Ez10N4Pg6/uNGnxmoTs5paGXTXk4sX0zBE42GznZGsiGPn09p1W8gs99r+7iQUUKrdusRpb9zqIqt4LNXoLVmFRo73L4+uPE3uK5R34fOlaTHahAP66Jcz6XP21yUEP7cZEen5eO1o6IzHXam4SsZrgdM8nkVzRD/x4HFkZyRe/RQWy8UBJ+98tzKLjtkXJE1H9y/J8xnMJqhul5Q3SgC/lpxI3LTvHsTTFAcXmgija/4Ab+uV47PeQ6f+VZQJyEgb6+QC1fSffjCTlZempkBkGFiL81ic9LCzmNPR1NGUL2MDh1NdganZFu9ckMZFEd+963ZdmOBwUW1Ws1JafP8WIqGU5yFLyvKvXMkzfySYi9G400eNgAcS+wApqTEgQuqEUU4Rc05SQLaWcR8GWUDY8UllIu7u5hQicME8/i1fSkbxHhe6LMIyC1PEe8eYwBY0vTKLF9lwO3pQDVp3EzBi9pBbNDo3n0Fg1wdGJC+I6CAx8dDlOlK5zZTOG8q+Vv5xRpVXBIhJfVmG1iBkccZVA21yLxYMKfrqm6asmv3Ff83+xNDNWIsb9/ThHAhiK1lQCMYxEh9Z5Lv5caL2MxUSZIAhfA6NSpyTt/ORUE5dwCSDElhGiZOt8pxkI3xX/mvZ8y7Zd4SJWcVmGt79x0MEnX+d53R+Vr3lyJ6LGFAzTAMO0SoXRCowa4AolMA7gTd3Tzp5XnAJOvJ0CjzUL7xrtTh7jXalJ0T5b16IpbsWfWSyRCrKc1WTquj6vniYTJjNBlobjINcWbZdBCIenlYN7lTlUU9bcAZMaFStV6ey7Bt8AUdvwb3zXlwt3SQ0zj2poI2LKXrUJ6f1EsfPE+Tymmry6USyT+gC+SG+3WKr50tLuRUVcQDWLvyx/4GMaZ340k4Z4/oahtXLoECuEg6XuDEw7xdBkQXgC6lI7zL+hMNQ28MZlczcuD81LASfQ0IIai+JY6ImHVm6MKILVvOsXszJebzoT2acMC7UL4TxJPjTczhfuEj2HE8yqCtVkXFLBwEEHgDTB5CJ/rW6eRy5yJIVIMAaiJo2Incm1XXtdkaX9bSHeJ1nC3anWI6Ahjng2Cerf17NQDYxnVBLeaJIEG2BoI9nRdQTMuxShqZxTh/XbkwO7pZTMMjPB0iqX4Zy+ArgGvja/moaWH1q8/5Fs/h8S88qcBoWwMD7hbdKEnAy6SdiIVHV0LEW9GDuKZu6VXsEbHaBN5cpAFj/Ti5LGV+fR7Qi8dAnX7MyRmy2iXN3g5jULqSgh1fkkb+5NdqBV8zwt580uQvMGXbthQ5elkjzhmUSqqdhFnuVi7lgj+TxZKd1bXhjZAcsGohmx9Y4oa4fwWHZSTM1aIyVsfObwh3cvg73JTsMJHXHXAf5MMPeBTH7IudcCv0aByEnDW5u0cOPUcz5QO99yNVg068rQFhkBwUeQW0+SUJ5ewx4n8iOmZE00d5DUwkKRg21b2xcuWb4xkkwapPC8Pm05FYhzJpZazJYIT9FgzP5OUVPvzjI8g5GLkZ6614WNiQv3wSQXbqYIHIYtzddBNtwso37985Fr7LGGD+9Kb7bqyrZrIvV8Saj3LA8CDJTDlb5ePHx6zWjVkI7tUe6avIauJo3dEw9xpSHkH2a56S0czENH3MWhf3o/S7JsI7IbrQ==", "X-Forefront-Antispam-Report": "CIP:198.47.23.195; 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Ip=[198.47.23.195];\n Helo=[lewvzet201.ext.ti.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF0002BA52.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ5PPF4B54CB2EB", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "`dram_init()` is called by R5 SPL and U-Boot, both. It starts by\ncomputing the size of the RAM. In verdin-am62(p), it does so by calling\n`get_ram_size()`. This function computes the size of the RAM by writing\nover the RAM.\n\nWhen R5 computes the size of the RAM, it does not update the DT with\nthis size. As a result, when A53 invokes `dram_init()` again, it has to\ncompute the size through `get_ram_size()` again.\n\nCommit 13c54cf588d82 and 0c3a6f748c9 add firewall over ATF's and OPTEE's\nregions. This firewall is added during the R5 SPL stage of boot. So when\nA53 attempts to write over RAM in `get_ram_size()`, it writes over the\nprotected region. Since A53 is a non-secure core, this is blocked by the\nfirewall.\n\nTo fix this, do the following:\n * Implement `spl_perform_board_fixups()` function for verdin-am62\n and verdin-am62p. Make this function call `fixup_memory_node()`,\n which updates the DT.\n * Add an if-block in `dram_init()`, to ensure that only R5 is able\n to call `get_ram_size()`, and that A53 reads this size from the\n DT.\n\nSigned-off-by: Suhaas Joshi <s-joshi@ti.com>\n---\n board/toradex/verdin-am62/verdin-am62.c | 10 ++++++++++\n board/toradex/verdin-am62p/verdin-am62p.c | 11 +++++++++++\n 2 files changed, 21 insertions(+)", "diff": "diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c\nindex 069aa6c7909..1aa106afbd9 100644\n--- a/board/toradex/verdin-am62/verdin-am62.c\n+++ b/board/toradex/verdin-am62/verdin-am62.c\n@@ -24,6 +24,9 @@ DECLARE_GLOBAL_DATA_PTR;\n \n int dram_init(void)\n {\n+\tif (!IS_ENABLED(CONFIG_CPU_V7R))\n+\t\treturn fdtdec_setup_mem_size_base();\n+\n \tgd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);\n \n \tif (gd->ram_size < SZ_512M)\n@@ -103,6 +106,13 @@ int board_late_init(void)\n \treturn 0;\n }\n \n+#if IS_ENABLED(CONFIG_XPL_BUILD)\n+void spl_perform_board_fixups(struct spl_image_info *spl_image)\n+{\n+\tfixup_memory_node(spl_image);\n+}\n+#endif\n+\n #define CTRLMMR_USB0_PHY_CTRL\t\t0x43004008\n #define CTRLMMR_USB1_PHY_CTRL\t\t0x43004018\n #define CORE_VOLTAGE\t\t\t0x80000000\ndiff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c\nindex 7c631f380ff..12693c1a46b 100644\n--- a/board/toradex/verdin-am62p/verdin-am62p.c\n+++ b/board/toradex/verdin-am62p/verdin-am62p.c\n@@ -18,6 +18,7 @@\n #include <k3-ddrss.h>\n #include <spl.h>\n #include <linux/sizes.h>\n+#include <mach/k3-ddr.h>\n \n #include \"../common/tdx-cfg-block.h\"\n \n@@ -57,6 +58,9 @@ static void read_hw_cfg(void)\n \n int dram_init(void)\n {\n+\tif (!IS_ENABLED(CONFIG_CPU_V7R))\n+\t\treturn fdtdec_setup_mem_size_base();\n+\n \tgd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);\n \n \tif (gd->ram_size < SZ_1G)\n@@ -132,6 +136,13 @@ int board_late_init(void)\n \treturn 0;\n }\n \n+#if IS_ENABLED(CONFIG_XPL_BUILD)\n+void spl_perform_board_fixups(struct spl_image_info *spl_image)\n+{\n+\tfixup_memory_node(spl_image);\n+}\n+#endif\n+\n #define MCU_CTRL_LFXOSC_32K_BYPASS_VAL\tBIT(4)\n \n void spl_board_init(void)\n", "prefixes": [ "1/1" ] }