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GET /api/patches/2195494/?format=api
{ "id": 2195494, "url": "http://patchwork.ozlabs.org/api/patches/2195494/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260211083415.133534-4-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260211083415.133534-4-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-02-11T08:34:13", "name": "[v5,3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated SMMUv3 devices", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4f7bd7d6aba3c7a00e7ba80430b1ad967f85beed", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260211083415.133534-4-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 491794, "url": "http://patchwork.ozlabs.org/api/series/491794/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491794", "date": "2026-02-11T08:34:10", "name": "vEVENTQ support for accelerated SMMUv3 devices", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491794/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195494/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195494/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=UoPZAgXR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c001::2;\n envelope-from=skolothumtho@nvidia.com;\n helo=SJ2PR03CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <nicolinc@nvidia.com>, <nathanc@nvidia.com>, <mochs@nvidia.com>,\n <jan@nvidia.com>, <jgg@nvidia.com>, <jonathan.cameron@huawei.com>,\n <zhangfei.gao@linaro.org>, <zhenzhong.duan@intel.com>, <kjaju@nvidia.com>,\n <skolothumtho@nvidia.com>", "Subject": "[PATCH v5 3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated\n SMMUv3 devices", "Date": "Wed, 11 Feb 2026 08:34:13 +0000", "Message-ID": "<20260211083415.133534-4-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260211083415.133534-1-skolothumtho@nvidia.com>", "References": "<20260211083415.133534-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN3PEPF0000B06B:EE_|MN2PR12MB4303:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d45c7737-5e2a-40f7-742d-08de6948844f", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700013|82310400026|1800799024|376014;", "X-Microsoft-Antispam-Message-Info": "\n quklAGjI6oYXTTz0tNq3KrPuizTfi/LjbeXdDSV/agJTQpwDiUCWMCV++qa7/M/1qwFXAoRE3bB2RM/J5FRS3iA50xhLng/GFyB6g5xkPYmj3bE8vKi30EOJJAodE9MOaKstI71x7eRKp9hVCwW0VBnqy+zP/ZSTqWGqRPEstEOFNubqMRvAN92YDj8mrq15se9vu+EO9EISyRsANGBoAZYUAlG/bSUB+ex8WT/2QBEug/RCzijQ29Y/Kb8hPJLxwdrr2JMGSY7rl5yoAXl5wycz26SMfRjySg2GtEh9WbnsWjxa/FeW58bVw5jMoIU0zdqXrXMeosv71NSeKGYNqHqaJ1IunM4Yyf1sM+l7y8hwrXAPYFYzxU5LWGB23ddA3ABLVN8HEY0JfvebudMDOcb5fMC4jGlYjOVkMZnKfHZJdcZohua7Ca76FeegAu2v7slMwrVf2z1dgibF4f5+rF5nos9xFayAF2T/0tR1V1zz1Cx3McyjhO7ajhrkpg+Mkty0DfGM25njmAqaVPr1HLYeyZQOioYR2bzGKrT93sWz0zv0w3XfIkvxIVcqCRgL0VMAgWKvu1VB3zgPU85+sicAlb6bdVN+gj1Z/0GPRLG/MaU7RRsHT8/f1ZBY2x7Rr0vYmt+b7rDHT8tj3QKqw+hcaKkLK7qakUWWJaD3NrJB8z2VRoObd5DS6NDl7Hfe5SWDdFnSBrBGZEMIInlS84awDZx8t5jfRhNzpYdNcBJvBC2GmW0GOI58Os6TJwtBmXbvcBACkYj7RuXFfhxq62VIJWALYjbsP+YnMV2p2rHSSeCFJe5nejuctEsjOne7bRCmSZ9g+D6qMeOX0kOTLGoppTn/CVbsr5CmULSfwKZfgo1386JsWB7CCXh7gQn291XqDAGNGTq06SmXQ1/+hvTTqkxyRLdPlKT2PVHk5jRotjtJHT99ka4/Q8mz7ywx3DSNsPtG5cPUrE04lhIZt9M4g1J2RUiBJ0aEwIMyxee3NQiHsp3fMl3bIOTkbe1LooXTdjEgmRmbh7X+vFarrNEp80+UxKmVtbZ27skZBuvb5yjI8fNBT4fr+kkifb7hN5/BfCTHvAiBUM/FSdTT06pwXFkCWKaKePEebowAPyBrLSlcP9agWSlvGHKQqGxPLY4lAIKEdynFIjVGlC0IgAZdlQ8uy9JCniwn2057yKbPZPvMX9MHiE76nFQiCqlWPRNRR1aSlahGsQZasLok3yr0J7P+RuMJyBtqISx9VsKtqE18NKykUxs/vc1xldu0SOUiJnXYVGAksdjp7ny5m8QIwA5HrTRr1cTl0LunTSzDnQF/NqWN8CUqqwiae3xjUcgbjl6QrIN2QQqaqvHYjZt8/5GVLWqTT4/j25fGpoFv9HF75cgi3vezn3IXql5bxpIiFgsdpmfaqUHzfl/Ya/BydBgNog6o887DTUYhMXfOdAJjJdNAtR3ODpHJ6b7auPjiV8EG7LgJVA2ZaY+1QBS4h6b46UpJth4X9ZPiK4/qzx0vvNwM/nRfcBaKFn0P9cipYyfdoQ0avWScUZI4BPl+590CuEFHFlz1E2c/Wrf3yf81arB3O3NMRC4YA3JRIDf81AtYsbBBkLIbBXP/r+dseoJ3708mgMocy9NFxv9pJE7HiLoGfqIlxKlphninr2EZz9iSO9x81WtwJe+Vmw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN3PEPF0000B06B.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4303", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nWhen the guest enables the Event Queue and a vIOMMU is present, allocate a\nvEVENTQ object so that host-side events related to the vIOMMU can be\nreceived and propagated back to the guest.\n\nFor cold-plugged devices using SMMUv3 acceleration, the vIOMMU is created\nbefore the guest boots. In this case, the vEVENTQ is allocated when the\nguest writes to SMMU_CR0 and sets EVENTQEN = 1.\n\nIf no cold-plugged device exists at boot (i.e. no vIOMMU initially), the\nvEVENTQ is allocated when a vIOMMU is created, i.e. during the first\ndevice hot-plug.\n\nEvent read and propagation will be added in a later patch.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nTested-by: Nicolin Chen <nicolinc@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 61 +++++++++++++++++++++++++++++++++++++++++--\n hw/arm/smmuv3-accel.h | 6 +++++\n hw/arm/smmuv3.c | 4 +++\n 3 files changed, 69 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex c19c526fca..d92fcb1a89 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -390,6 +390,19 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n+static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n+{\n+ IOMMUFDVeventq *veventq = accel->veventq;\n+\n+ if (!veventq) {\n+ return;\n+ }\n+ close(veventq->veventq_fd);\n+ iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id);\n+ g_free(veventq);\n+ accel->veventq = NULL;\n+}\n+\n static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n {\n IOMMUFDViommu *viommu = accel->viommu;\n@@ -397,6 +410,7 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n if (!viommu) {\n return;\n }\n+ smmuv3_accel_free_veventq(accel);\n iommufd_backend_free_id(viommu->iommufd, accel->bypass_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->abort_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->viommu->viommu_id);\n@@ -404,6 +418,41 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n accel->viommu = NULL;\n }\n \n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ SMMUv3AccelState *accel = s->s_accel;\n+ IOMMUFDVeventq *veventq;\n+ uint32_t veventq_id;\n+ uint32_t veventq_fd;\n+\n+ if (!accel || !accel->viommu) {\n+ return true;\n+ }\n+\n+ if (accel->veventq) {\n+ return true;\n+ }\n+\n+ if (!smmuv3_eventq_enabled(s)) {\n+ return true;\n+ }\n+\n+ if (!iommufd_backend_alloc_veventq(accel->viommu->iommufd,\n+ accel->viommu->viommu_id,\n+ IOMMU_VEVENTQ_TYPE_ARM_SMMUV3,\n+ 1 << s->eventq.log2size, &veventq_id,\n+ &veventq_fd, errp)) {\n+ return false;\n+ }\n+\n+ veventq = g_new(IOMMUFDVeventq, 1);\n+ veventq->veventq_id = veventq_id;\n+ veventq->veventq_fd = veventq_fd;\n+ veventq->viommu = accel->viommu;\n+ accel->veventq = veventq;\n+ return true;\n+}\n+\n static bool\n smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n@@ -429,6 +478,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n viommu->viommu_id = viommu_id;\n viommu->s2_hwpt_id = s2_hwpt_id;\n viommu->iommufd = idev->iommufd;\n+ accel->viommu = viommu;\n \n /*\n * Pre-allocate HWPTs for S1 bypass and abort cases. These will be attached\n@@ -448,14 +498,20 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n goto free_abort_hwpt;\n }\n \n+ /* Allocate a vEVENTQ if guest has enabled event queue */\n+ if (!smmuv3_accel_alloc_veventq(s, errp)) {\n+ goto free_bypass_hwpt;\n+ }\n+\n /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */\n hwpt_id = smmuv3_accel_gbpa_hwpt(s, accel);\n if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) {\n- goto free_bypass_hwpt;\n+ goto free_veventq;\n }\n- accel->viommu = viommu;\n return true;\n \n+free_veventq:\n+ smmuv3_accel_free_veventq(accel);\n free_bypass_hwpt:\n iommufd_backend_free_id(idev->iommufd, accel->bypass_hwpt_id);\n free_abort_hwpt:\n@@ -463,6 +519,7 @@ free_abort_hwpt:\n free_viommu:\n iommufd_backend_free_id(idev->iommufd, viommu->viommu_id);\n g_free(viommu);\n+ accel->viommu = NULL;\n return false;\n }\n \ndiff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex a8a64802ec..dba6c71de5 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -22,6 +22,7 @@\n */\n typedef struct SMMUv3AccelState {\n IOMMUFDViommu *viommu;\n+ IOMMUFDVeventq *veventq;\n uint32_t bypass_hwpt_id;\n uint32_t abort_hwpt_id;\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n@@ -50,6 +51,7 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp);\n bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n Error **errp);\n void smmuv3_accel_idr_override(SMMUv3State *s);\n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n void smmuv3_accel_reset(SMMUv3State *s);\n #else\n static inline void smmuv3_accel_init(SMMUv3State *s)\n@@ -80,6 +82,10 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n static inline void smmuv3_accel_idr_override(SMMUv3State *s)\n {\n }\n+static inline bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ return true;\n+}\n static inline void smmuv3_accel_reset(SMMUv3State *s)\n {\n }\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex c08d58c579..210ac038fe 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1605,6 +1605,10 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n s->cr0ack = data & ~SMMU_CR0_RESERVED;\n /* in case the command queue has been enabled */\n smmuv3_cmdq_consume(s, &local_err);\n+ /* Allocate vEVENTQ if EventQ is enabled and a vIOMMU is available */\n+ if (local_err == NULL) {\n+ smmuv3_accel_alloc_veventq(s, &local_err);\n+ }\n break;\n case A_CR1:\n s->cr[1] = data;\n", "prefixes": [ "v5", "3/5" ] }