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GET /api/patches/2195493/?format=api
{ "id": 2195493, "url": "http://patchwork.ozlabs.org/api/patches/2195493/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260211083415.133534-6-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260211083415.133534-6-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-02-11T08:34:15", "name": "[v5,5/5] hw/arm/smmuv3-accel: Read and propagate host vIOMMU events", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "913e2abe9fa3443df2a68b5f86fbc5d68b527485", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260211083415.133534-6-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 491794, "url": "http://patchwork.ozlabs.org/api/series/491794/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491794", "date": "2026-02-11T08:34:10", "name": "vEVENTQ support for accelerated SMMUv3 devices", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491794/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195493/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195493/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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<qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <nicolinc@nvidia.com>, <nathanc@nvidia.com>, <mochs@nvidia.com>,\n <jan@nvidia.com>, <jgg@nvidia.com>, <jonathan.cameron@huawei.com>,\n <zhangfei.gao@linaro.org>, <zhenzhong.duan@intel.com>, <kjaju@nvidia.com>,\n <skolothumtho@nvidia.com>", "Subject": "[PATCH v5 5/5] hw/arm/smmuv3-accel: Read and propagate host vIOMMU\n events", "Date": "Wed, 11 Feb 2026 08:34:15 +0000", "Message-ID": "<20260211083415.133534-6-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260211083415.133534-1-skolothumtho@nvidia.com>", "References": "<20260211083415.133534-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", 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66c35351-17b1-4c7c-cac1-08de694888f2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000E9CD.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB7738", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Install an event handler on the vEVENTQ fd to read and propagate host\ngenerated vIOMMU events to the guest.\n\nThe handler runs in QEMU's main loop, using a non-blocking fd registered\nvia qemu_set_fd_handler().\n\nTested-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 62 +++++++++++++++++++++++++++++++++++++++++++\n hw/arm/smmuv3-accel.h | 2 ++\n 2 files changed, 64 insertions(+)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex d92fcb1a89..0d5dcef941 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -390,6 +390,48 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n+static void smmuv3_accel_event_read(void *opaque)\n+{\n+ SMMUv3State *s = opaque;\n+ SMMUv3AccelState *accel = s->s_accel;\n+ struct {\n+ struct iommufd_vevent_header hdr;\n+ struct iommu_vevent_arm_smmuv3 vevent;\n+ } buf;\n+ uint32_t last_seq = accel->last_event_seq;\n+ ssize_t bytes;\n+\n+ bytes = read(accel->veventq->veventq_fd, &buf, sizeof(buf));\n+ if (bytes <= 0) {\n+ if (errno == EAGAIN || errno == EINTR) {\n+ return;\n+ }\n+ error_report_once(\"vEVENTQ: read failed (%m)\");\n+ return;\n+ }\n+\n+ if (bytes == sizeof(buf.hdr) &&\n+ (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) {\n+ error_report_once(\"vEVENTQ has lost events\");\n+ accel->event_start = false;\n+ return;\n+ }\n+ if (bytes < sizeof(buf)) {\n+ error_report_once(\"vEVENTQ: incomplete read (%zd/%zd bytes)\",\n+ bytes, sizeof(buf));\n+ return;\n+ }\n+\n+ /* Check sequence in hdr for lost events if any */\n+ if (accel->event_start && (buf.hdr.sequence - last_seq != 1)) {\n+ error_report_once(\"vEVENTQ: detected lost %u event(s)\",\n+ buf.hdr.sequence - last_seq - 1);\n+ }\n+ accel->last_event_seq = buf.hdr.sequence;\n+ accel->event_start = true;\n+ smmuv3_propagate_event(s, (Evt *)&buf.vevent);\n+}\n+\n static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n {\n IOMMUFDVeventq *veventq = accel->veventq;\n@@ -397,6 +439,7 @@ static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n if (!veventq) {\n return;\n }\n+ qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL);\n close(veventq->veventq_fd);\n iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id);\n g_free(veventq);\n@@ -424,6 +467,7 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n IOMMUFDVeventq *veventq;\n uint32_t veventq_id;\n uint32_t veventq_fd;\n+ int flags;\n \n if (!accel || !accel->viommu) {\n return true;\n@@ -445,12 +489,30 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n return false;\n }\n \n+ flags = fcntl(veventq_fd, F_GETFL);\n+ if (flags < 0) {\n+ error_setg_errno(errp, errno, \"Failed to get flags for vEVENTQ fd\");\n+ goto free_veventq;\n+ }\n+ if (fcntl(veventq_fd, F_SETFL, flags | O_NONBLOCK) < 0) {\n+ error_setg_errno(errp, errno, \"Failed to set O_NONBLOCK on vEVENTQ fd\");\n+ goto free_veventq;\n+ }\n+\n veventq = g_new(IOMMUFDVeventq, 1);\n veventq->veventq_id = veventq_id;\n veventq->veventq_fd = veventq_fd;\n veventq->viommu = accel->viommu;\n accel->veventq = veventq;\n+\n+ /* Set up event handler for veventq fd */\n+ qemu_set_fd_handler(veventq_fd, smmuv3_accel_event_read, NULL, s);\n return true;\n+\n+free_veventq:\n+ close(veventq_fd);\n+ iommufd_backend_free_id(accel->viommu->iommufd, veventq_id);\n+ return false;\n }\n \n static bool\ndiff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex dba6c71de5..c9c10e55c3 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -23,6 +23,8 @@\n typedef struct SMMUv3AccelState {\n IOMMUFDViommu *viommu;\n IOMMUFDVeventq *veventq;\n+ uint32_t last_event_seq;\n+ bool event_start;\n uint32_t bypass_hwpt_id;\n uint32_t abort_hwpt_id;\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n", "prefixes": [ "v5", "5/5" ] }