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GET /api/patches/2195371/?format=api
{ "id": 2195371, "url": "http://patchwork.ozlabs.org/api/patches/2195371/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210214044.1174699-5-iii@linux.ibm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210214044.1174699-5-iii@linux.ibm.com>", "list_archive_url": null, "date": "2026-02-10T21:39:03", "name": "[v5,4/5] target/s390x: Implement DIVIDE TO INTEGER", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "938b7a410387d098b381b037263ebfebc0df28db", "submitter": { "id": 74525, "url": "http://patchwork.ozlabs.org/api/people/74525/?format=api", "name": "Ilya Leoshkevich", "email": "iii@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210214044.1174699-5-iii@linux.ibm.com/mbox/", "series": [ { "id": 491741, "url": "http://patchwork.ozlabs.org/api/series/491741/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491741", "date": "2026-02-10T21:39:00", "name": "target/s390x: Implement DIVIDE TO INTEGER", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491741/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195371/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195371/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=jjqONq6M;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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envelope-from=iii@linux.ibm.com;\n helo=mx0b-001b2d01.pphosted.com", "X-Spam_score_int": "-19", "X-Spam_score": "-2.0", "X-Spam_bar": "--", "X-Spam_report": "(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "DIVIDE TO INTEGER computes floating point remainder and is used by\nLuaJIT, so add it to QEMU.\n\nPut the main logic into fpu/, because it is way more convenient to\noperate on FloatParts than to convert floats back-and-forth.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Ilya Leoshkevich <iii@linux.ibm.com>\n---\n fpu/softfloat.c | 142 +++++++++++++++++++++++++++++++\n include/fpu/softfloat.h | 11 +++\n target/s390x/helper.h | 1 +\n target/s390x/tcg/fpu_helper.c | 56 ++++++++++++\n target/s390x/tcg/insn-data.h.inc | 5 +-\n target/s390x/tcg/translate.c | 26 ++++++\n 6 files changed, 240 insertions(+), 1 deletion(-)", "diff": "diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 8094358c2e4..87409753483 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -5361,6 +5361,148 @@ floatx80 floatx80_round(floatx80 a, float_status *status)\n return floatx80_round_pack_canonical(&p, status);\n }\n \n+static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n+ int final_quotient_rounding_mode,\n+ bool mask_underflow, bool mask_inexact,\n+ const FloatFmt *fmt,\n+ FloatParts64 *r, FloatParts64 *n,\n+ uint32_t *cc, int *dxc,\n+ float_status *status)\n+{\n+ /* POp table \"Results: DIVIDE TO INTEGER (Part 1 of 2)\" */\n+ if ((float_cmask(a->cls) | float_cmask(b->cls)) & float_cmask_anynan) {\n+ *r = *parts_pick_nan(a, b, status);\n+ *n = *r;\n+ *cc = 1;\n+ } else if (a->cls == float_class_inf || b->cls == float_class_zero) {\n+ parts_default_nan(r, status);\n+ *n = *r;\n+ *cc = 1;\n+ status->float_exception_flags |= float_flag_invalid;\n+ } else if (b->cls == float_class_inf) {\n+ *r = *a;\n+ n->cls = float_class_zero;\n+ n->sign = a->sign ^ b->sign;\n+ *cc = 0;\n+ } else {\n+ FloatParts64 *q, q_buf, *r_precise, r_precise_buf;\n+ int float_exception_flags = 0;\n+ bool is_q_smallish;\n+ uint32_t r_flags;\n+\n+ /* Compute precise quotient */\n+ q_buf = *a;\n+ q = parts_div(&q_buf, b, status);\n+\n+ /*\n+ * Check whether two closest integers can be precisely represented,\n+ * i.e., all their bits fit into the fractional part.\n+ */\n+ is_q_smallish = q->exp < (fmt->frac_size + 1);\n+\n+ /*\n+ * Final quotient is rounded using final-quotient-rounding method, and\n+ * partial quotient is rounded toward zero.\n+ *\n+ * Rounding of partial quotient may be inexact. This is the whole point\n+ * of distinguishing partial quotients, so ignore the exception.\n+ */\n+ *n = *q;\n+ parts_round_to_int_normal(n,\n+ is_q_smallish ?\n+ final_quotient_rounding_mode :\n+ float_round_to_zero,\n+ 0, fmt->frac_size);\n+\n+ /* Compute precise remainder */\n+ r_precise_buf = *b;\n+ r_precise = parts_muladd_scalbn(&r_precise_buf, n, a, 0,\n+ float_muladd_negate_product, status);\n+\n+ /* Round remainder to the target format */\n+ *r = *r_precise;\n+ status->float_exception_flags = 0;\n+ parts_uncanon(r, status, fmt);\n+ r_flags = status->float_exception_flags;\n+ r->frac &= (1ULL << fmt->frac_size) - 1;\n+ parts_canonicalize(r, status, fmt);\n+\n+ /* POp table \"Results: DIVIDE TO INTEGER (Part 2 of 2)\" */\n+ if (is_q_smallish) {\n+ if (r->cls != float_class_zero) {\n+ if (r->exp < 2 - (1 << (fmt->exp_size - 1))) {\n+ if (mask_underflow) {\n+ float_exception_flags |= float_flag_underflow;\n+ *dxc = 0x10;\n+ r->exp += fmt->exp_re_bias;\n+ }\n+ } else if (r_flags & float_flag_inexact) {\n+ float_exception_flags |= float_flag_inexact;\n+ if (mask_inexact) {\n+ bool saved_r_sign, saved_r_precise_sign;\n+\n+ /*\n+ * Check whether remainder was truncated (rounded\n+ * toward zero) or incremented.\n+ */\n+ saved_r_sign = r->sign;\n+ saved_r_precise_sign = r_precise->sign;\n+ r->sign = false;\n+ r_precise->sign = false;\n+ if (parts_compare(r, r_precise, status, true) <\n+ float_relation_equal) {\n+ *dxc = 0x8;\n+ } else {\n+ *dxc = 0xc;\n+ }\n+ r->sign = saved_r_sign;\n+ r_precise->sign = saved_r_precise_sign;\n+ }\n+ }\n+ }\n+ *cc = 0;\n+ } else if (n->exp > (1 << (fmt->exp_size - 1)) - 1) {\n+ n->exp -= fmt->exp_re_bias;\n+ *cc = r->cls == float_class_zero ? 1 : 3;\n+ } else {\n+ *cc = r->cls == float_class_zero ? 0 : 2;\n+ }\n+\n+ /* Adjust signs of zero results */\n+ if (r->cls == float_class_zero) {\n+ r->sign = a->sign;\n+ }\n+ if (n->cls == float_class_zero) {\n+ n->sign = a->sign ^ b->sign;\n+ }\n+\n+ status->float_exception_flags = float_exception_flags;\n+ }\n+}\n+\n+#define DEFINE_S390_DIVIDE_TO_INTEGER(floatN) \\\n+void floatN ## _s390_divide_to_integer(floatN a, floatN b, \\\n+ int final_quotient_rounding_mode, \\\n+ bool mask_underflow, bool mask_inexact, \\\n+ floatN *r, floatN *n, \\\n+ uint32_t *cc, int *dxc, \\\n+ float_status *status) \\\n+{ \\\n+ FloatParts64 pa, pb, pr, pn; \\\n+ \\\n+ floatN ## _unpack_canonical(&pa, a, status); \\\n+ floatN ## _unpack_canonical(&pb, b, status); \\\n+ parts_s390_divide_to_integer(&pa, &pb, final_quotient_rounding_mode, \\\n+ mask_underflow, mask_inexact, \\\n+ &floatN ## _params, \\\n+ &pr, &pn, cc, dxc, status); \\\n+ *r = floatN ## _round_pack_canonical(&pr, status); \\\n+ *n = floatN ## _round_pack_canonical(&pn, status); \\\n+}\n+\n+DEFINE_S390_DIVIDE_TO_INTEGER(float32)\n+DEFINE_S390_DIVIDE_TO_INTEGER(float64)\n+\n static void __attribute__((constructor)) softfloat_init(void)\n {\n union_float64 ua, ub, uc, ur;\ndiff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h\nindex c18ab2cb609..66b0c47b5eb 100644\n--- a/include/fpu/softfloat.h\n+++ b/include/fpu/softfloat.h\n@@ -1372,4 +1372,15 @@ static inline bool float128_unordered_quiet(float128 a, float128 b,\n *----------------------------------------------------------------------------*/\n float128 float128_default_nan(float_status *status);\n \n+#define DECLARE_S390_DIVIDE_TO_INTEGER(floatN) \\\n+void floatN ## _s390_divide_to_integer(floatN a, floatN b, \\\n+ int final_quotient_rounding_mode, \\\n+ bool mask_underflow, bool mask_inexact, \\\n+ floatN *r, floatN *n, \\\n+ uint32_t *cc, int *dxc, \\\n+ float_status *status)\n+DECLARE_S390_DIVIDE_TO_INTEGER(float32);\n+DECLARE_S390_DIVIDE_TO_INTEGER(float64);\n+\n+\n #endif /* SOFTFLOAT_H */\ndiff --git a/target/s390x/helper.h b/target/s390x/helper.h\nindex 1a8a76abb98..6a7426fdac7 100644\n--- a/target/s390x/helper.h\n+++ b/target/s390x/helper.h\n@@ -46,6 +46,7 @@ DEF_HELPER_FLAGS_3(sxb, TCG_CALL_NO_WG, i128, env, i128, i128)\n DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64)\n DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64)\n DEF_HELPER_FLAGS_3(dxb, TCG_CALL_NO_WG, i128, env, i128, i128)\n+DEF_HELPER_6(dib, void, env, i32, i32, i32, i32, i32)\n DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64)\n DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64)\n DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64)\ndiff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c\nindex 7a3ff501a46..122994960a6 100644\n--- a/target/s390x/tcg/fpu_helper.c\n+++ b/target/s390x/tcg/fpu_helper.c\n@@ -315,6 +315,62 @@ Int128 HELPER(dxb)(CPUS390XState *env, Int128 a, Int128 b)\n return RET128(ret);\n }\n \n+void HELPER(dib)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t r3,\n+ uint32_t m4, uint32_t bits)\n+{\n+ int final_quotient_rounding_mode = s390_get_bfp_rounding_mode(env, m4);\n+ bool mask_underflow = (env->fpc >> 24) & S390_IEEE_MASK_UNDERFLOW;\n+ bool mask_inexact = (env->fpc >> 24) & S390_IEEE_MASK_INEXACT;\n+ float32 a32, b32, n32, r32;\n+ float64 a64, b64, n64, r64;\n+ int dxc = -1;\n+ uint32_t cc;\n+\n+ if (bits == 32) {\n+ a32 = env->vregs[r1][0] >> 32;\n+ b32 = env->vregs[r2][0] >> 32;\n+\n+ float32_s390_divide_to_integer(\n+ a32, b32,\n+ final_quotient_rounding_mode,\n+ mask_underflow, mask_inexact,\n+ &r32, &n32, &cc, &dxc, &env->fpu_status);\n+ } else {\n+ a64 = env->vregs[r1][0];\n+ b64 = env->vregs[r2][0];\n+\n+ float64_s390_divide_to_integer(\n+ a64, b64,\n+ final_quotient_rounding_mode,\n+ mask_underflow, mask_inexact,\n+ &r64, &n64, &cc, &dxc, &env->fpu_status);\n+ }\n+\n+ /* Flush the results if needed */\n+ if ((env->fpu_status.float_exception_flags & float_flag_invalid) &&\n+ ((env->fpc >> 24) & S390_IEEE_MASK_INVALID)) {\n+ /* The action for invalid operation is \"Suppress\" */\n+ } else {\n+ /* The action for other exceptions is \"Complete\" */\n+ if (bits == 32) {\n+ env->vregs[r1][0] = deposit64(env->vregs[r1][0], 32, 32, r32);\n+ env->vregs[r3][0] = deposit64(env->vregs[r3][0], 32, 32, n32);\n+ } else {\n+ env->vregs[r1][0] = r64;\n+ env->vregs[r3][0] = n64;\n+ }\n+ env->cc_op = cc;\n+ }\n+\n+ /* Raise an exception if needed */\n+ if (dxc == -1) {\n+ handle_exceptions(env, false, GETPC());\n+ } else {\n+ env->fpu_status.float_exception_flags = 0;\n+ tcg_s390_data_exception(env, dxc, GETPC());\n+ }\n+}\n+\n /* 32-bit FP multiplication */\n uint64_t HELPER(meeb)(CPUS390XState *env, uint64_t f1, uint64_t f2)\n {\ndiff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc\nindex baaafe922e9..0d5392eac54 100644\n--- a/target/s390x/tcg/insn-data.h.inc\n+++ b/target/s390x/tcg/insn-data.h.inc\n@@ -9,7 +9,7 @@\n * OPC = (op << 8) | op2 where op is the major, op2 the minor opcode\n * NAME = name of the opcode, used internally\n * FMT = format of the opcode (defined in insn-format.h.inc)\n- * FAC = facility the opcode is available in (defined in DisasFacility)\n+ * FAC = facility the opcode is available in (define in translate.c)\n * I1 = func in1_xx fills o->in1\n * I2 = func in2_xx fills o->in2\n * P = func prep_xx initializes o->*out*\n@@ -361,6 +361,9 @@\n C(0xb91d, DSGFR, RRE, Z, r1p1, r2_32s, r1_P, 0, divs64, 0)\n C(0xe30d, DSG, RXY_a, Z, r1p1, m2_64, r1_P, 0, divs64, 0)\n C(0xe31d, DSGF, RXY_a, Z, r1p1, m2_32s, r1_P, 0, divs64, 0)\n+/* DIVIDE TO INTEGER */\n+ D(0xb35b, DIDBR, RRF_b, Z, 0, 0, 0, 0, dib, 0, 64)\n+ D(0xb353, DIEBR, RRF_b, Z, 0, 0, 0, 0, dib, 0, 32)\n \n /* EXCLUSIVE OR */\n C(0x1700, XR, RR_a, Z, r1, r2, new, r1_32, xor, nz32)\ndiff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c\nindex 203afe265bc..92344441878 100644\n--- a/target/s390x/tcg/translate.c\n+++ b/target/s390x/tcg/translate.c\n@@ -2283,6 +2283,32 @@ static DisasJumpType op_dxb(DisasContext *s, DisasOps *o)\n return DISAS_NEXT;\n }\n \n+static DisasJumpType op_dib(DisasContext *s, DisasOps *o)\n+{\n+ const bool fpe = s390_has_feat(S390_FEAT_FLOATING_POINT_EXT);\n+ uint8_t m4 = get_field(s, m4);\n+\n+ if (get_field(s, r1) == get_field(s, r2) ||\n+ get_field(s, r1) == get_field(s, r3) ||\n+ get_field(s, r2) == get_field(s, r3)) {\n+ gen_program_exception(s, PGM_SPECIFICATION);\n+ return DISAS_NORETURN;\n+ }\n+\n+ if (m4 == 2 || (!fpe && m4 == 3) || m4 > 7) {\n+ gen_program_exception(s, PGM_SPECIFICATION);\n+ return DISAS_NORETURN;\n+ }\n+\n+ gen_helper_dib(tcg_env, tcg_constant_i32(get_field(s, r1)),\n+ tcg_constant_i32(get_field(s, r2)),\n+ tcg_constant_i32(get_field(s, r3)), tcg_constant_i32(m4),\n+ tcg_constant_i32(s->insn->data));\n+ set_cc_static(s);\n+\n+ return DISAS_NEXT;\n+}\n+\n static DisasJumpType op_ear(DisasContext *s, DisasOps *o)\n {\n int r2 = get_field(s, r2);\n", "prefixes": [ "v5", "4/5" ] }