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GET /api/patches/2195360/?format=api
{ "id": 2195360, "url": "http://patchwork.ozlabs.org/api/patches/2195360/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210201540.1405424-10-pierrick.bouvier@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210201540.1405424-10-pierrick.bouvier@linaro.org>", "list_archive_url": null, "date": "2026-02-10T20:15:37", "name": "[v3,09/12] target/arm/tcg/vec_helper.c: make compilation unit common", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fb47e326a18d65af5bb5103ef6f9e0efe3362be2", "submitter": { "id": 85798, "url": "http://patchwork.ozlabs.org/api/people/85798/?format=api", "name": "Pierrick Bouvier", "email": "pierrick.bouvier@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210201540.1405424-10-pierrick.bouvier@linaro.org/mbox/", "series": [ { "id": 491737, "url": "http://patchwork.ozlabs.org/api/series/491737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491737", "date": "2026-02-10T20:15:31", "name": "target/arm: single-binary", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/491737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195360/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195360/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=w2jXsTjj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x531.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We need to extract 64 bits helper in a new file (vec_helper64.c), and\nextract some macro definition also, since they will be used in both\nfiles.\nAs well, DO_3OP_PAIR was defined twice, so rename the second variant\nto DO_3OP_PAIR_NO_STATUS to reflect what it does.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n---\n target/arm/tcg/vec_internal.h | 49 ++++++++\n target/arm/tcg/vec_helper.c | 225 +++-------------------------------\n target/arm/tcg/vec_helper64.c | 142 +++++++++++++++++++++\n target/arm/tcg/meson.build | 4 +-\n 4 files changed, 212 insertions(+), 208 deletions(-)\n create mode 100644 target/arm/tcg/vec_helper64.c", "diff": "diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h\nindex cf41b03dbcd..4edd2b4fc18 100644\n--- a/target/arm/tcg/vec_internal.h\n+++ b/target/arm/tcg/vec_internal.h\n@@ -450,4 +450,53 @@ static inline void depositn(uint64_t *p, unsigned pos,\n }\n }\n \n+#define DO_3OP(NAME, FUNC, TYPE) \\\n+void HELPER(NAME)(void *vd, void *vn, void *vm, \\\n+ float_status * stat, uint32_t desc) \\\n+{ \\\n+ intptr_t i, oprsz = simd_oprsz(desc); \\\n+ TYPE *d = vd, *n = vn, *m = vm; \\\n+ for (i = 0; i < oprsz / sizeof(TYPE); i++) { \\\n+ d[i] = FUNC(n[i], m[i], stat); \\\n+ } \\\n+ clear_tail(d, oprsz, simd_maxsz(desc)); \\\n+}\n+\n+#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \\\n+void HELPER(NAME)(void *vd, void *vn, void *vm, \\\n+ float_status * stat, uint32_t desc) \\\n+{ \\\n+ ARMVectorReg scratch; \\\n+ intptr_t oprsz = simd_oprsz(desc); \\\n+ intptr_t half = oprsz / sizeof(TYPE) / 2; \\\n+ TYPE *d = vd, *n = vn, *m = vm; \\\n+ if (unlikely(d == m)) { \\\n+ m = memcpy(&scratch, m, oprsz); \\\n+ } \\\n+ for (intptr_t i = 0; i < half; ++i) { \\\n+ d[H(i)] = FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); \\\n+ } \\\n+ for (intptr_t i = 0; i < half; ++i) { \\\n+ d[H(i + half)] = FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); \\\n+ } \\\n+ clear_tail(d, oprsz, simd_maxsz(desc)); \\\n+}\n+\n+#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) \\\n+void HELPER(NAME)(void *vd, void *vn, void *vm, \\\n+ float_status * stat, uint32_t desc) \\\n+{ \\\n+ intptr_t i, j, oprsz = simd_oprsz(desc); \\\n+ intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \\\n+ intptr_t idx = simd_data(desc); \\\n+ TYPE *d = vd, *n = vn, *m = vm; \\\n+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \\\n+ TYPE mm = m[H(i + idx)]; \\\n+ for (j = 0; j < segment; j++) { \\\n+ d[i + j] = ADD(d[i + j], MUL(n[i + j], mm, stat), stat); \\\n+ } \\\n+ } \\\n+ clear_tail(d, oprsz, simd_maxsz(desc)); \\\n+}\n+\n #endif /* TARGET_ARM_VEC_INTERNAL_H */\ndiff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c\nindex 1223b843bf1..91e98d28aea 100644\n--- a/target/arm/tcg/vec_helper.c\n+++ b/target/arm/tcg/vec_helper.c\n@@ -20,9 +20,6 @@\n #include \"qemu/osdep.h\"\n #include \"cpu.h\"\n #include \"helper.h\"\n-#include \"helper-a64.h\"\n-#include \"helper-sme.h\"\n-#include \"helper-sve.h\"\n #include \"tcg/tcg-gvec-desc.h\"\n #include \"fpu/softfloat.h\"\n #include \"qemu/int128.h\"\n@@ -1458,18 +1455,6 @@ static float32 float32_rsqrts_nf(float32 op1, float32 op2, float_status *stat)\n return float32_div(op1, float32_two, stat);\n }\n \n-#define DO_3OP(NAME, FUNC, TYPE) \\\n-void HELPER(NAME)(void *vd, void *vn, void *vm, \\\n- float_status *stat, uint32_t desc) \\\n-{ \\\n- intptr_t i, oprsz = simd_oprsz(desc); \\\n- TYPE *d = vd, *n = vn, *m = vm; \\\n- for (i = 0; i < oprsz / sizeof(TYPE); i++) { \\\n- d[i] = FUNC(n[i], m[i], stat); \\\n- } \\\n- clear_tail(d, oprsz, simd_maxsz(desc)); \\\n-}\n-\n DO_3OP(gvec_fadd_b16, bfloat16_add, float16)\n DO_3OP(gvec_fadd_h, float16_add, float16)\n DO_3OP(gvec_fadd_s, float32_add, float32)\n@@ -1541,49 +1526,6 @@ DO_3OP(gvec_recps_nf_s, float32_recps_nf, float32)\n DO_3OP(gvec_rsqrts_nf_h, float16_rsqrts_nf, float16)\n DO_3OP(gvec_rsqrts_nf_s, float32_rsqrts_nf, float32)\n \n-#ifdef TARGET_AARCH64\n-DO_3OP(gvec_fdiv_h, float16_div, float16)\n-DO_3OP(gvec_fdiv_s, float32_div, float32)\n-DO_3OP(gvec_fdiv_d, float64_div, float64)\n-\n-DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16)\n-DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32)\n-DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64)\n-\n-DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)\n-DO_3OP(gvec_recps_s, helper_recpsf_f32, float32)\n-DO_3OP(gvec_recps_d, helper_recpsf_f64, float64)\n-\n-DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16)\n-DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32)\n-DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)\n-\n-DO_3OP(gvec_ah_recps_h, helper_recpsf_ah_f16, float16)\n-DO_3OP(gvec_ah_recps_s, helper_recpsf_ah_f32, float32)\n-DO_3OP(gvec_ah_recps_d, helper_recpsf_ah_f64, float64)\n-\n-DO_3OP(gvec_ah_rsqrts_h, helper_rsqrtsf_ah_f16, float16)\n-DO_3OP(gvec_ah_rsqrts_s, helper_rsqrtsf_ah_f32, float32)\n-DO_3OP(gvec_ah_rsqrts_d, helper_rsqrtsf_ah_f64, float64)\n-\n-DO_3OP(gvec_ah_fmax_h, helper_vfp_ah_maxh, float16)\n-DO_3OP(gvec_ah_fmax_s, helper_vfp_ah_maxs, float32)\n-DO_3OP(gvec_ah_fmax_d, helper_vfp_ah_maxd, float64)\n-\n-DO_3OP(gvec_ah_fmin_h, helper_vfp_ah_minh, float16)\n-DO_3OP(gvec_ah_fmin_s, helper_vfp_ah_mins, float32)\n-DO_3OP(gvec_ah_fmin_d, helper_vfp_ah_mind, float64)\n-\n-DO_3OP(gvec_fmax_b16, bfloat16_max, bfloat16)\n-DO_3OP(gvec_fmin_b16, bfloat16_min, bfloat16)\n-DO_3OP(gvec_fmaxnum_b16, bfloat16_maxnum, bfloat16)\n-DO_3OP(gvec_fminnum_b16, bfloat16_minnum, bfloat16)\n-DO_3OP(gvec_ah_fmax_b16, helper_sme2_ah_fmax_b16, bfloat16)\n-DO_3OP(gvec_ah_fmin_b16, helper_sme2_ah_fmin_b16, bfloat16)\n-\n-#endif\n-#undef DO_3OP\n-\n /* Non-fused multiply-add (unlike float16_muladd etc, which are fused) */\n static float16 float16_muladd_nf(float16 dest, float16 op1, float16 op2,\n float_status *stat)\n@@ -1769,23 +1711,6 @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8)\n \n #undef DO_MLA_IDX\n \n-#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) \\\n-void HELPER(NAME)(void *vd, void *vn, void *vm, \\\n- float_status *stat, uint32_t desc) \\\n-{ \\\n- intptr_t i, j, oprsz = simd_oprsz(desc); \\\n- intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \\\n- intptr_t idx = simd_data(desc); \\\n- TYPE *d = vd, *n = vn, *m = vm; \\\n- for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \\\n- TYPE mm = m[H(i + idx)]; \\\n- for (j = 0; j < segment; j++) { \\\n- d[i + j] = ADD(d[i + j], MUL(n[i + j], mm, stat), stat); \\\n- } \\\n- } \\\n- clear_tail(d, oprsz, simd_maxsz(desc)); \\\n-}\n-\n #define nop(N, M, S) (M)\n \n DO_FMUL_IDX(gvec_fmul_idx_b16, nop, bfloat16_mul, float16, H2)\n@@ -1793,14 +1718,6 @@ DO_FMUL_IDX(gvec_fmul_idx_h, nop, float16_mul, float16, H2)\n DO_FMUL_IDX(gvec_fmul_idx_s, nop, float32_mul, float32, H4)\n DO_FMUL_IDX(gvec_fmul_idx_d, nop, float64_mul, float64, H8)\n \n-#ifdef TARGET_AARCH64\n-\n-DO_FMUL_IDX(gvec_fmulx_idx_h, nop, helper_advsimd_mulxh, float16, H2)\n-DO_FMUL_IDX(gvec_fmulx_idx_s, nop, helper_vfp_mulxs, float32, H4)\n-DO_FMUL_IDX(gvec_fmulx_idx_d, nop, helper_vfp_mulxd, float64, H8)\n-\n-#endif\n-\n #undef nop\n \n /*\n@@ -1812,8 +1729,6 @@ DO_FMUL_IDX(gvec_fmla_nf_idx_s, float32_add, float32_mul, float32, H4)\n DO_FMUL_IDX(gvec_fmls_nf_idx_h, float16_sub, float16_mul, float16, H2)\n DO_FMUL_IDX(gvec_fmls_nf_idx_s, float32_sub, float32_mul, float32, H4)\n \n-#undef DO_FMUL_IDX\n-\n #define DO_FMLA_IDX(NAME, TYPE, H, NEGX, NEGF) \\\n void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \\\n float_status *stat, uint32_t desc) \\\n@@ -2530,31 +2445,6 @@ void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)\n clear_tail(d, 16, simd_maxsz(desc));\n }\n \n-#ifdef TARGET_AARCH64\n-void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)\n-{\n- int shift = simd_data(desc) * 8;\n- intptr_t i, opr_sz = simd_oprsz(desc);\n- uint64_t *d = vd, *n = vn, *m = vm;\n-\n- for (i = 0; i < opr_sz / 8; ++i) {\n- d[i] = clmul_8x4_even(n[i] >> shift, m[i] >> shift);\n- }\n-}\n-\n-void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc)\n-{\n- intptr_t sel = H4(simd_data(desc));\n- intptr_t i, opr_sz = simd_oprsz(desc);\n- uint32_t *n = vn, *m = vm;\n- uint64_t *d = vd;\n-\n- for (i = 0; i < opr_sz / 8; ++i) {\n- d[i] = clmul_32(n[2 * i + sel], m[2 * i + sel]);\n- }\n-}\n-#endif\n-\n #define DO_CMP0(NAME, TYPE, OP) \\\n void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \\\n { \\\n@@ -2628,26 +2518,6 @@ DO_ABA(gvec_uaba_d, uint64_t)\n \n #undef DO_ABA\n \n-#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \\\n-void HELPER(NAME)(void *vd, void *vn, void *vm, \\\n- float_status *stat, uint32_t desc) \\\n-{ \\\n- ARMVectorReg scratch; \\\n- intptr_t oprsz = simd_oprsz(desc); \\\n- intptr_t half = oprsz / sizeof(TYPE) / 2; \\\n- TYPE *d = vd, *n = vn, *m = vm; \\\n- if (unlikely(d == m)) { \\\n- m = memcpy(&scratch, m, oprsz); \\\n- } \\\n- for (intptr_t i = 0; i < half; ++i) { \\\n- d[H(i)] = FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); \\\n- } \\\n- for (intptr_t i = 0; i < half; ++i) { \\\n- d[H(i + half)] = FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); \\\n- } \\\n- clear_tail(d, oprsz, simd_maxsz(desc)); \\\n-}\n-\n DO_3OP_PAIR(gvec_faddp_h, float16_add, float16, H2)\n DO_3OP_PAIR(gvec_faddp_s, float32_add, float32, H4)\n DO_3OP_PAIR(gvec_faddp_d, float64_add, float64, )\n@@ -2668,19 +2538,7 @@ DO_3OP_PAIR(gvec_fminnump_h, float16_minnum, float16, H2)\n DO_3OP_PAIR(gvec_fminnump_s, float32_minnum, float32, H4)\n DO_3OP_PAIR(gvec_fminnump_d, float64_minnum, float64, )\n \n-#ifdef TARGET_AARCH64\n-DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2)\n-DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4)\n-DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, )\n-\n-DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2)\n-DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4)\n-DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, )\n-#endif\n-\n-#undef DO_3OP_PAIR\n-\n-#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \\\n+#define DO_3OP_PAIR_NO_STATUS(NAME, FUNC, TYPE, H) \\\n void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \\\n { \\\n ARMVectorReg scratch; \\\n@@ -2700,29 +2558,29 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \\\n }\n \n #define ADD(A, B) (A + B)\n-DO_3OP_PAIR(gvec_addp_b, ADD, uint8_t, H1)\n-DO_3OP_PAIR(gvec_addp_h, ADD, uint16_t, H2)\n-DO_3OP_PAIR(gvec_addp_s, ADD, uint32_t, H4)\n-DO_3OP_PAIR(gvec_addp_d, ADD, uint64_t, )\n+DO_3OP_PAIR_NO_STATUS(gvec_addp_b, ADD, uint8_t, H1)\n+DO_3OP_PAIR_NO_STATUS(gvec_addp_h, ADD, uint16_t, H2)\n+DO_3OP_PAIR_NO_STATUS(gvec_addp_s, ADD, uint32_t, H4)\n+DO_3OP_PAIR_NO_STATUS(gvec_addp_d, ADD, uint64_t, /**/)\n #undef ADD\n \n-DO_3OP_PAIR(gvec_smaxp_b, MAX, int8_t, H1)\n-DO_3OP_PAIR(gvec_smaxp_h, MAX, int16_t, H2)\n-DO_3OP_PAIR(gvec_smaxp_s, MAX, int32_t, H4)\n+DO_3OP_PAIR_NO_STATUS(gvec_smaxp_b, MAX, int8_t, H1)\n+DO_3OP_PAIR_NO_STATUS(gvec_smaxp_h, MAX, int16_t, H2)\n+DO_3OP_PAIR_NO_STATUS(gvec_smaxp_s, MAX, int32_t, H4)\n \n-DO_3OP_PAIR(gvec_umaxp_b, MAX, uint8_t, H1)\n-DO_3OP_PAIR(gvec_umaxp_h, MAX, uint16_t, H2)\n-DO_3OP_PAIR(gvec_umaxp_s, MAX, uint32_t, H4)\n+DO_3OP_PAIR_NO_STATUS(gvec_umaxp_b, MAX, uint8_t, H1)\n+DO_3OP_PAIR_NO_STATUS(gvec_umaxp_h, MAX, uint16_t, H2)\n+DO_3OP_PAIR_NO_STATUS(gvec_umaxp_s, MAX, uint32_t, H4)\n \n-DO_3OP_PAIR(gvec_sminp_b, MIN, int8_t, H1)\n-DO_3OP_PAIR(gvec_sminp_h, MIN, int16_t, H2)\n-DO_3OP_PAIR(gvec_sminp_s, MIN, int32_t, H4)\n+DO_3OP_PAIR_NO_STATUS(gvec_sminp_b, MIN, int8_t, H1)\n+DO_3OP_PAIR_NO_STATUS(gvec_sminp_h, MIN, int16_t, H2)\n+DO_3OP_PAIR_NO_STATUS(gvec_sminp_s, MIN, int32_t, H4)\n \n-DO_3OP_PAIR(gvec_uminp_b, MIN, uint8_t, H1)\n-DO_3OP_PAIR(gvec_uminp_h, MIN, uint16_t, H2)\n-DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4)\n+DO_3OP_PAIR_NO_STATUS(gvec_uminp_b, MIN, uint8_t, H1)\n+DO_3OP_PAIR_NO_STATUS(gvec_uminp_h, MIN, uint16_t, H2)\n+DO_3OP_PAIR_NO_STATUS(gvec_uminp_s, MIN, uint32_t, H4)\n \n-#undef DO_3OP_PAIR\n+#undef DO_3OP_PAIR_NO_STATUS\n \n #define DO_VCVT_FIXED(NAME, FUNC, TYPE) \\\n void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \\\n@@ -2797,53 +2655,6 @@ DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32_t)\n \n #undef DO_VRINT_RMODE\n \n-#ifdef TARGET_AARCH64\n-void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc)\n-{\n- const uint8_t *indices = vm;\n- size_t oprsz = simd_oprsz(desc);\n- uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5);\n- bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1);\n- uint32_t table_len = desc >> (SIMD_DATA_SHIFT + 6);\n- union {\n- uint8_t b[16];\n- uint64_t d[2];\n- } result;\n-\n- /*\n- * We must construct the final result in a temp, lest the output\n- * overlaps the input table. For TBL, begin with zero; for TBX,\n- * begin with the original register contents. Note that we always\n- * copy 16 bytes here to avoid an extra branch; clearing the high\n- * bits of the register for oprsz == 8 is handled below.\n- */\n- if (is_tbx) {\n- memcpy(&result, vd, 16);\n- } else {\n- memset(&result, 0, 16);\n- }\n-\n- for (size_t i = 0; i < oprsz; ++i) {\n- uint32_t index = indices[H1(i)];\n-\n- if (index < table_len) {\n- /*\n- * Convert index (a byte offset into the virtual table\n- * which is a series of 128-bit vectors concatenated)\n- * into the correct register element, bearing in mind\n- * that the table can wrap around from V31 to V0.\n- */\n- const uint8_t *table = (const uint8_t *)\n- aa64_vfp_qreg(env, (rn + (index >> 4)) % 32);\n- result.b[H1(i)] = table[H1(index % 16)];\n- }\n- }\n-\n- memcpy(vd, &result, 16);\n- clear_tail(vd, oprsz, simd_maxsz(desc));\n-}\n-#endif\n-\n /*\n * NxN -> N highpart multiply\n *\ndiff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c\nnew file mode 100644\nindex 00000000000..249a257177e\n--- /dev/null\n+++ b/target/arm/tcg/vec_helper64.c\n@@ -0,0 +1,142 @@\n+/*\n+ * ARM AdvSIMD / SVE Vector Operations\n+ *\n+ * Copyright (c) 2026 Linaro\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"cpu.h\"\n+#include \"helper.h\"\n+#include \"helper-a64.h\"\n+#include \"helper-sme.h\"\n+#include \"helper-sve.h\"\n+#include \"tcg/tcg-gvec-desc.h\"\n+#include \"fpu/softfloat.h\"\n+#include \"qemu/int128.h\"\n+#include \"crypto/clmul.h\"\n+#include \"vec_internal.h\"\n+\n+DO_3OP(gvec_fdiv_h, float16_div, float16)\n+DO_3OP(gvec_fdiv_s, float32_div, float32)\n+DO_3OP(gvec_fdiv_d, float64_div, float64)\n+\n+DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16)\n+DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32)\n+DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64)\n+\n+DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)\n+DO_3OP(gvec_recps_s, helper_recpsf_f32, float32)\n+DO_3OP(gvec_recps_d, helper_recpsf_f64, float64)\n+\n+DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16)\n+DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32)\n+DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)\n+\n+DO_3OP(gvec_ah_recps_h, helper_recpsf_ah_f16, float16)\n+DO_3OP(gvec_ah_recps_s, helper_recpsf_ah_f32, float32)\n+DO_3OP(gvec_ah_recps_d, helper_recpsf_ah_f64, float64)\n+\n+DO_3OP(gvec_ah_rsqrts_h, helper_rsqrtsf_ah_f16, float16)\n+DO_3OP(gvec_ah_rsqrts_s, helper_rsqrtsf_ah_f32, float32)\n+DO_3OP(gvec_ah_rsqrts_d, helper_rsqrtsf_ah_f64, float64)\n+\n+DO_3OP(gvec_ah_fmax_h, helper_vfp_ah_maxh, float16)\n+DO_3OP(gvec_ah_fmax_s, helper_vfp_ah_maxs, float32)\n+DO_3OP(gvec_ah_fmax_d, helper_vfp_ah_maxd, float64)\n+\n+DO_3OP(gvec_ah_fmin_h, helper_vfp_ah_minh, float16)\n+DO_3OP(gvec_ah_fmin_s, helper_vfp_ah_mins, float32)\n+DO_3OP(gvec_ah_fmin_d, helper_vfp_ah_mind, float64)\n+\n+DO_3OP(gvec_fmax_b16, bfloat16_max, bfloat16)\n+DO_3OP(gvec_fmin_b16, bfloat16_min, bfloat16)\n+DO_3OP(gvec_fmaxnum_b16, bfloat16_maxnum, bfloat16)\n+DO_3OP(gvec_fminnum_b16, bfloat16_minnum, bfloat16)\n+DO_3OP(gvec_ah_fmax_b16, helper_sme2_ah_fmax_b16, bfloat16)\n+DO_3OP(gvec_ah_fmin_b16, helper_sme2_ah_fmin_b16, bfloat16)\n+\n+#define nop(N, M, S) (M)\n+\n+DO_FMUL_IDX(gvec_fmulx_idx_h, nop, helper_advsimd_mulxh, float16, H2)\n+DO_FMUL_IDX(gvec_fmulx_idx_s, nop, helper_vfp_mulxs, float32, H4)\n+DO_FMUL_IDX(gvec_fmulx_idx_d, nop, helper_vfp_mulxd, float64, H8)\n+\n+#undef nop\n+\n+void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ int shift = simd_data(desc) * 8;\n+ intptr_t i, opr_sz = simd_oprsz(desc);\n+ uint64_t *d = vd, *n = vn, *m = vm;\n+\n+ for (i = 0; i < opr_sz / 8; ++i) {\n+ d[i] = clmul_8x4_even(n[i] >> shift, m[i] >> shift);\n+ }\n+}\n+\n+void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ intptr_t sel = H4(simd_data(desc));\n+ intptr_t i, opr_sz = simd_oprsz(desc);\n+ uint32_t *n = vn, *m = vm;\n+ uint64_t *d = vd;\n+\n+ for (i = 0; i < opr_sz / 8; ++i) {\n+ d[i] = clmul_32(n[2 * i + sel], m[2 * i + sel]);\n+ }\n+}\n+\n+DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2)\n+DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4)\n+DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, /**/)\n+\n+DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2)\n+DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4)\n+DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, /**/)\n+\n+void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc)\n+{\n+ const uint8_t *indices = vm;\n+ size_t oprsz = simd_oprsz(desc);\n+ uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5);\n+ bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1);\n+ uint32_t table_len = desc >> (SIMD_DATA_SHIFT + 6);\n+ union {\n+ uint8_t b[16];\n+ uint64_t d[2];\n+ } result;\n+\n+ /*\n+ * We must construct the final result in a temp, lest the output\n+ * overlaps the input table. For TBL, begin with zero; for TBX,\n+ * begin with the original register contents. Note that we always\n+ * copy 16 bytes here to avoid an extra branch; clearing the high\n+ * bits of the register for oprsz == 8 is handled below.\n+ */\n+ if (is_tbx) {\n+ memcpy(&result, vd, 16);\n+ } else {\n+ memset(&result, 0, 16);\n+ }\n+\n+ for (size_t i = 0; i < oprsz; ++i) {\n+ uint32_t index = indices[H1(i)];\n+\n+ if (index < table_len) {\n+ /*\n+ * Convert index (a byte offset into the virtual table\n+ * which is a series of 128-bit vectors concatenated)\n+ * into the correct register element, bearing in mind\n+ * that the table can wrap around from V31 to V0.\n+ */\n+ const uint8_t *table = (const uint8_t *)\n+ aa64_vfp_qreg(env, (rn + (index >> 4)) % 32);\n+ result.b[H1(i)] = table[H1(index % 16)];\n+ }\n+ }\n+\n+ memcpy(vd, &result, 16);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build\nindex 08ac5ec9906..3b501df7425 100644\n--- a/target/arm/tcg/meson.build\n+++ b/target/arm/tcg/meson.build\n@@ -33,7 +33,6 @@ arm_ss.add(files(\n 'm_helper.c',\n 'mve_helper.c',\n 'op_helper.c',\n- 'vec_helper.c',\n ))\n \n arm_ss.add(when: 'TARGET_AARCH64', if_true: files(\n@@ -47,6 +46,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(\n 'pauth_helper.c',\n 'sme_helper.c',\n 'sve_helper.c',\n+ 'vec_helper64.c',\n ))\n \n arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))\n@@ -66,11 +66,13 @@ arm_common_system_ss.add(files(\n 'psci.c',\n 'tlb_helper.c',\n 'tlb-insns.c',\n+ 'vec_helper.c',\n 'vfp_helper.c',\n ))\n arm_user_ss.add(files(\n 'hflags.c',\n 'neon_helper.c',\n 'tlb_helper.c',\n+ 'vec_helper.c',\n 'vfp_helper.c',\n ))\n", "prefixes": [ "v3", "09/12" ] }