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GET /api/patches/2195359/?format=api
{ "id": 2195359, "url": "http://patchwork.ozlabs.org/api/patches/2195359/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210201540.1405424-13-pierrick.bouvier@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210201540.1405424-13-pierrick.bouvier@linaro.org>", "list_archive_url": null, "date": "2026-02-10T20:15:40", "name": "[v3,12/12] include/tcg/tcg-op.h: eradicate TARGET_INSN_START_EXTRA_WORDS", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9c9d8627404b6cbe75a3bda79296af2f853c34a5", "submitter": { "id": 85798, "url": "http://patchwork.ozlabs.org/api/people/85798/?format=api", "name": "Pierrick Bouvier", "email": "pierrick.bouvier@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210201540.1405424-13-pierrick.bouvier@linaro.org/mbox/", "series": [ { "id": 491737, "url": "http://patchwork.ozlabs.org/api/series/491737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491737", "date": "2026-02-10T20:15:31", "name": "target/arm: single-binary", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/491737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195359/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195359/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=wx1ZNTpu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x62b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This commit removes TARGET_INSN_START_EXTRA_WORDS and force all arch to\ncall the same version of tcg_gen_insn_start, with additional 0 arguments\nif needed. Since all arch have a single call site (in translate.c), this\nis as good documentation as having a single define.\n\nThe notable exception is target/arm, which has two different translate\nfiles for 32/64 bits. Since it's the only one, we accept to have two\ncall sites for this.\n\nAs well, we update parameter type to use uint64_t instead of\ntarget_ulong, so it can be called from common code.\n\nSigned-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n---\n include/tcg/tcg-op-common.h | 8 ++++++++\n include/tcg/tcg-op.h | 29 -----------------------------\n target/alpha/cpu-param.h | 2 --\n target/arm/cpu-param.h | 7 -------\n target/avr/cpu-param.h | 2 --\n target/hexagon/cpu-param.h | 2 --\n target/hppa/cpu-param.h | 2 --\n target/i386/cpu-param.h | 2 --\n target/loongarch/cpu-param.h | 2 --\n target/m68k/cpu-param.h | 2 --\n target/microblaze/cpu-param.h | 2 --\n target/mips/cpu-param.h | 2 --\n target/or1k/cpu-param.h | 2 --\n target/ppc/cpu-param.h | 2 --\n target/riscv/cpu-param.h | 7 -------\n target/rx/cpu-param.h | 2 --\n target/s390x/cpu-param.h | 2 --\n target/sh4/cpu-param.h | 2 --\n target/sparc/cpu-param.h | 2 --\n target/tricore/cpu-param.h | 2 --\n target/xtensa/cpu-param.h | 2 --\n target/alpha/translate.c | 4 ++--\n target/avr/translate.c | 2 +-\n target/hexagon/translate.c | 2 +-\n target/i386/tcg/translate.c | 2 +-\n target/loongarch/tcg/translate.c | 2 +-\n target/m68k/translate.c | 2 +-\n target/microblaze/translate.c | 2 +-\n target/or1k/translate.c | 2 +-\n target/ppc/translate.c | 2 +-\n target/rx/translate.c | 2 +-\n target/sh4/translate.c | 4 ++--\n target/sparc/translate.c | 2 +-\n target/tricore/translate.c | 2 +-\n target/xtensa/translate.c | 2 +-\n 35 files changed, 24 insertions(+), 93 deletions(-)", "diff": "diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h\nindex f752ef440b2..e02f209c093 100644\n--- a/include/tcg/tcg-op-common.h\n+++ b/include/tcg/tcg-op-common.h\n@@ -30,6 +30,14 @@ TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t off, const char *name);\n TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *name);\n \n /* Generic ops. */\n+static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1,\n+ uint64_t a2)\n+{\n+ TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);\n+ tcg_set_insn_start_param(op, 0, pc);\n+ tcg_set_insn_start_param(op, 1, a1);\n+ tcg_set_insn_start_param(op, 2, a2);\n+}\n \n void gen_set_label(TCGLabel *l);\n void tcg_gen_br(TCGLabel *l);\ndiff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h\nindex ee379994e76..7024be938e6 100644\n--- a/include/tcg/tcg-op.h\n+++ b/include/tcg/tcg-op.h\n@@ -28,35 +28,6 @@\n # error Mismatch with insn-start-words.h\n #endif\n \n-#if TARGET_INSN_START_EXTRA_WORDS == 0\n-static inline void tcg_gen_insn_start(target_ulong pc)\n-{\n- TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);\n- tcg_set_insn_start_param(op, 0, pc);\n- tcg_set_insn_start_param(op, 1, 0);\n- tcg_set_insn_start_param(op, 2, 0);\n-}\n-#elif TARGET_INSN_START_EXTRA_WORDS == 1\n-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)\n-{\n- TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);\n- tcg_set_insn_start_param(op, 0, pc);\n- tcg_set_insn_start_param(op, 1, a1);\n- tcg_set_insn_start_param(op, 2, 0);\n-}\n-#elif TARGET_INSN_START_EXTRA_WORDS == 2\n-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,\n- target_ulong a2)\n-{\n- TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);\n- tcg_set_insn_start_param(op, 0, pc);\n- tcg_set_insn_start_param(op, 1, a1);\n- tcg_set_insn_start_param(op, 2, a2);\n-}\n-#else\n-#error Unhandled TARGET_INSN_START_EXTRA_WORDS value\n-#endif\n-\n #if TARGET_LONG_BITS == 32\n typedef TCGv_i32 TCGv;\n #define tcg_temp_new() tcg_temp_new_i32()\ndiff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h\nindex a799f42db31..c9da620ab3e 100644\n--- a/target/alpha/cpu-param.h\n+++ b/target/alpha/cpu-param.h\n@@ -24,6 +24,4 @@\n # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)\n #endif\n \n-#define TARGET_INSN_START_EXTRA_WORDS 0\n-\n #endif\ndiff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h\nindex 8b46c7c5708..7de0099cbfa 100644\n--- a/target/arm/cpu-param.h\n+++ b/target/arm/cpu-param.h\n@@ -32,11 +32,4 @@\n # define TARGET_PAGE_BITS_LEGACY 10\n #endif /* !CONFIG_USER_ONLY */\n \n-/*\n- * ARM-specific extra insn start words:\n- * 1: Conditional execution bits\n- * 2: Partial exception syndrome for data aborts\n- */\n-#define TARGET_INSN_START_EXTRA_WORDS 2\n-\n #endif\ndiff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h\nindex f74bfc25804..ea7887919a7 100644\n--- a/target/avr/cpu-param.h\n+++ b/target/avr/cpu-param.h\n@@ -25,6 +25,4 @@\n #define TARGET_PHYS_ADDR_SPACE_BITS 24\n #define TARGET_VIRT_ADDR_SPACE_BITS 24\n \n-#define TARGET_INSN_START_EXTRA_WORDS 0\n-\n #endif\ndiff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h\nindex 635d509e743..45ee7b46409 100644\n--- a/target/hexagon/cpu-param.h\n+++ b/target/hexagon/cpu-param.h\n@@ -23,6 +23,4 @@\n #define TARGET_PHYS_ADDR_SPACE_BITS 36\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n-#define TARGET_INSN_START_EXTRA_WORDS 0\n-\n #endif\ndiff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h\nindex 9bf7ac76d0c..e0b2c7c9157 100644\n--- a/target/hppa/cpu-param.h\n+++ b/target/hppa/cpu-param.h\n@@ -19,6 +19,4 @@\n \n #define TARGET_PAGE_BITS 12\n \n-#define TARGET_INSN_START_EXTRA_WORDS 2\n-\n #endif\ndiff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h\nindex ebb844bcc83..909bc027923 100644\n--- a/target/i386/cpu-param.h\n+++ b/target/i386/cpu-param.h\n@@ -22,6 +22,4 @@\n #endif\n #define TARGET_PAGE_BITS 12\n \n-#define TARGET_INSN_START_EXTRA_WORDS 1\n-\n #endif\ndiff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h\nindex 58cc45a377e..071567712b3 100644\n--- a/target/loongarch/cpu-param.h\n+++ b/target/loongarch/cpu-param.h\n@@ -13,6 +13,4 @@\n \n #define TARGET_PAGE_BITS 12\n \n-#define TARGET_INSN_START_EXTRA_WORDS 0\n-\n #endif\ndiff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h\nindex 256a2b5f8b2..7afbf6d302d 100644\n--- a/target/m68k/cpu-param.h\n+++ b/target/m68k/cpu-param.h\n@@ -17,6 +17,4 @@\n #define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n-#define TARGET_INSN_START_EXTRA_WORDS 1\n-\n #endif\ndiff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h\nindex e0a37945136..6a0714bb3d7 100644\n--- a/target/microblaze/cpu-param.h\n+++ b/target/microblaze/cpu-param.h\n@@ -27,6 +27,4 @@\n /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */\n #define TARGET_PAGE_BITS 12\n \n-#define TARGET_INSN_START_EXTRA_WORDS 1\n-\n #endif\ndiff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h\nindex 58f450827f7..a71e7383d24 100644\n--- a/target/mips/cpu-param.h\n+++ b/target/mips/cpu-param.h\n@@ -20,6 +20,4 @@\n #endif\n #define TARGET_PAGE_BITS 12\n \n-#define TARGET_INSN_START_EXTRA_WORDS 2\n-\n #endif\ndiff --git a/target/or1k/cpu-param.h b/target/or1k/cpu-param.h\nindex b4f57bbe692..3011bf5fcca 100644\n--- a/target/or1k/cpu-param.h\n+++ b/target/or1k/cpu-param.h\n@@ -12,6 +12,4 @@\n #define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n-#define TARGET_INSN_START_EXTRA_WORDS 1\n-\n #endif\ndiff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h\nindex e4ed9080ee9..ca7602d8983 100644\n--- a/target/ppc/cpu-param.h\n+++ b/target/ppc/cpu-param.h\n@@ -37,6 +37,4 @@\n # define TARGET_PAGE_BITS 12\n #endif\n \n-#define TARGET_INSN_START_EXTRA_WORDS 0\n-\n #endif\ndiff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h\nindex cfdc67c258c..039e877891a 100644\n--- a/target/riscv/cpu-param.h\n+++ b/target/riscv/cpu-param.h\n@@ -17,13 +17,6 @@\n #endif\n #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */\n \n-/*\n- * RISC-V-specific extra insn start words:\n- * 1: Original instruction opcode\n- * 2: more information about instruction\n- */\n-#define TARGET_INSN_START_EXTRA_WORDS 2\n-\n /*\n * The current MMU Modes are:\n * - U mode 0b000\ndiff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h\nindex 84934f3bcaf..ef1970a09e9 100644\n--- a/target/rx/cpu-param.h\n+++ b/target/rx/cpu-param.h\n@@ -24,6 +24,4 @@\n #define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n-#define TARGET_INSN_START_EXTRA_WORDS 0\n-\n #endif\ndiff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h\nindex abfae3bedfb..a5f798eeae7 100644\n--- a/target/s390x/cpu-param.h\n+++ b/target/s390x/cpu-param.h\n@@ -12,6 +12,4 @@\n #define TARGET_PHYS_ADDR_SPACE_BITS 64\n #define TARGET_VIRT_ADDR_SPACE_BITS 64\n \n-#define TARGET_INSN_START_EXTRA_WORDS 2\n-\n #endif\ndiff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h\nindex f328715ee86..2b6e11dd0ac 100644\n--- a/target/sh4/cpu-param.h\n+++ b/target/sh4/cpu-param.h\n@@ -16,6 +16,4 @@\n # define TARGET_VIRT_ADDR_SPACE_BITS 32\n #endif\n \n-#define TARGET_INSN_START_EXTRA_WORDS 1\n-\n #endif\ndiff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h\nindex 45eea9d6bac..6e8e2a51469 100644\n--- a/target/sparc/cpu-param.h\n+++ b/target/sparc/cpu-param.h\n@@ -21,6 +21,4 @@\n # define TARGET_VIRT_ADDR_SPACE_BITS 32\n #endif\n \n-#define TARGET_INSN_START_EXTRA_WORDS 1\n-\n #endif\ndiff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h\nindex eb33a67c419..790242ef3d2 100644\n--- a/target/tricore/cpu-param.h\n+++ b/target/tricore/cpu-param.h\n@@ -12,6 +12,4 @@\n #define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n-#define TARGET_INSN_START_EXTRA_WORDS 0\n-\n #endif\ndiff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h\nindex 7a0c22c9005..06d85218b84 100644\n--- a/target/xtensa/cpu-param.h\n+++ b/target/xtensa/cpu-param.h\n@@ -16,6 +16,4 @@\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n #endif\n \n-#define TARGET_INSN_START_EXTRA_WORDS 0\n-\n #endif\ndiff --git a/target/alpha/translate.c b/target/alpha/translate.c\nindex 4442462891e..4d22d7d5a45 100644\n--- a/target/alpha/translate.c\n+++ b/target/alpha/translate.c\n@@ -2899,9 +2899,9 @@ static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n if (ctx->pcrel) {\n- tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK);\n+ tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK, 0, 0);\n } else {\n- tcg_gen_insn_start(dcbase->pc_next);\n+ tcg_gen_insn_start(dcbase->pc_next, 0, 0);\n }\n }\n \ndiff --git a/target/avr/translate.c b/target/avr/translate.c\nindex 78ae83df219..649dd4b0112 100644\n--- a/target/avr/translate.c\n+++ b/target/avr/translate.c\n@@ -2689,7 +2689,7 @@ static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)\n {\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- tcg_gen_insn_start(ctx->npc);\n+ tcg_gen_insn_start(ctx->npc, 0, 0);\n }\n \n static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex e88e19cc1af..1c9ab29bd12 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -978,7 +978,7 @@ static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n {\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- tcg_gen_insn_start(ctx->base.pc_next);\n+ tcg_gen_insn_start(ctx->base.pc_next, 0, 0);\n }\n \n static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx)\ndiff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c\nindex 7186517239c..14210d569f7 100644\n--- a/target/i386/tcg/translate.c\n+++ b/target/i386/tcg/translate.c\n@@ -3501,7 +3501,7 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n if (tb_cflags(dcbase->tb) & CF_PCREL) {\n pc_arg &= ~TARGET_PAGE_MASK;\n }\n- tcg_gen_insn_start(pc_arg, dc->cc_op);\n+ tcg_gen_insn_start(pc_arg, dc->cc_op, 0);\n }\n \n static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\ndiff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c\nindex 30f375b33f0..b9ed13d19c6 100644\n--- a/target/loongarch/tcg/translate.c\n+++ b/target/loongarch/tcg/translate.c\n@@ -159,7 +159,7 @@ static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)\n {\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- tcg_gen_insn_start(ctx->base.pc_next);\n+ tcg_gen_insn_start(ctx->base.pc_next, 0, 0);\n }\n \n /*\ndiff --git a/target/m68k/translate.c b/target/m68k/translate.c\nindex a0309939012..abc1c79f3cd 100644\n--- a/target/m68k/translate.c\n+++ b/target/m68k/translate.c\n@@ -6041,7 +6041,7 @@ static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)\n static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n {\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n- tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);\n+ tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0);\n }\n \n static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\ndiff --git a/target/microblaze/translate.c b/target/microblaze/translate.c\nindex 0be3c98dc17..2af67beecec 100644\n--- a/target/microblaze/translate.c\n+++ b/target/microblaze/translate.c\n@@ -1630,7 +1630,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs)\n {\n DisasContext *dc = container_of(dcb, DisasContext, base);\n \n- tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);\n+ tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK, 0);\n }\n \n static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)\ndiff --git a/target/or1k/translate.c b/target/or1k/translate.c\nindex ce2dc466dc7..de81dc6ef8d 100644\n--- a/target/or1k/translate.c\n+++ b/target/or1k/translate.c\n@@ -1552,7 +1552,7 @@ static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n \n tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)\n- | (dc->base.num_insns > 1 ? 2 : 0));\n+ | (dc->base.num_insns > 1 ? 2 : 0), 0);\n }\n \n static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)\ndiff --git a/target/ppc/translate.c b/target/ppc/translate.c\nindex e9acfa239ec..a09a6df93fd 100644\n--- a/target/ppc/translate.c\n+++ b/target/ppc/translate.c\n@@ -6575,7 +6575,7 @@ static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)\n \n static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)\n {\n- tcg_gen_insn_start(dcbase->pc_next);\n+ tcg_gen_insn_start(dcbase->pc_next, 0, 0);\n }\n \n static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)\ndiff --git a/target/rx/translate.c b/target/rx/translate.c\nindex 26d41548294..a245b9db8fe 100644\n--- a/target/rx/translate.c\n+++ b/target/rx/translate.c\n@@ -2217,7 +2217,7 @@ static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)\n {\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- tcg_gen_insn_start(ctx->base.pc_next);\n+ tcg_gen_insn_start(ctx->base.pc_next, 0, 0);\n }\n \n static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)\ndiff --git a/target/sh4/translate.c b/target/sh4/translate.c\nindex b3ae0a3814c..b1057727c55 100644\n--- a/target/sh4/translate.c\n+++ b/target/sh4/translate.c\n@@ -2181,7 +2181,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)\n * tb->icount * insn_start.\n */\n for (i = 1; i < max_insns; ++i) {\n- tcg_gen_insn_start(pc + i * 2, ctx->envflags);\n+ tcg_gen_insn_start(pc + i * 2, ctx->envflags, 0);\n ctx->base.insn_start = tcg_last_op();\n }\n }\n@@ -2241,7 +2241,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)\n {\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags);\n+ tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags, 0);\n }\n \n static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)\ndiff --git a/target/sparc/translate.c b/target/sparc/translate.c\nindex 57b50ff8b9a..7e8558dbbd8 100644\n--- a/target/sparc/translate.c\n+++ b/target/sparc/translate.c\n@@ -5735,7 +5735,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)\n g_assert_not_reached();\n }\n }\n- tcg_gen_insn_start(dc->pc, npc);\n+ tcg_gen_insn_start(dc->pc, npc, 0);\n }\n \n static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)\ndiff --git a/target/tricore/translate.c b/target/tricore/translate.c\nindex 18d8726af6d..0eaf7a82f87 100644\n--- a/target/tricore/translate.c\n+++ b/target/tricore/translate.c\n@@ -8410,7 +8410,7 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n {\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- tcg_gen_insn_start(ctx->base.pc_next);\n+ tcg_gen_insn_start(ctx->base.pc_next, 0, 0);\n }\n \n static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env)\ndiff --git a/target/xtensa/translate.c b/target/xtensa/translate.c\nindex bb8d2ed86cf..5e3707d3fdf 100644\n--- a/target/xtensa/translate.c\n+++ b/target/xtensa/translate.c\n@@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)\n \n static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n {\n- tcg_gen_insn_start(dcbase->pc_next);\n+ tcg_gen_insn_start(dcbase->pc_next, 0, 0);\n }\n \n static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n", "prefixes": [ "v3", "12/12" ] }