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GET /api/patches/2195353/?format=api
{ "id": 2195353, "url": "http://patchwork.ozlabs.org/api/patches/2195353/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210201540.1405424-12-pierrick.bouvier@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210201540.1405424-12-pierrick.bouvier@linaro.org>", "list_archive_url": null, "date": "2026-02-10T20:15:39", "name": "[v3,11/12] target/arm/tcg/translate.h: replace target_long with int64_t", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f3c3ba9494af4aa76ac48903433be754ab3d2472", "submitter": { "id": 85798, "url": "http://patchwork.ozlabs.org/api/people/85798/?format=api", "name": "Pierrick Bouvier", "email": "pierrick.bouvier@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210201540.1405424-12-pierrick.bouvier@linaro.org/mbox/", "series": [ { "id": 491737, "url": "http://patchwork.ozlabs.org/api/series/491737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491737", "date": "2026-02-10T20:15:31", "name": "target/arm: single-binary", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/491737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195353/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195353/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=irrrB2zI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::642;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x642.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "target_long is used to represent a pc diff. Checked all call sites to\nmake sure we were already passing signed values, so extending works as\nexpected.\n\nUse vaddr for pc_curr and pc_save.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n---\n target/arm/tcg/translate-a32.h | 2 +-\n target/arm/tcg/translate.h | 12 ++++++------\n target/arm/tcg/translate.c | 18 +++++++++---------\n 3 files changed, 16 insertions(+), 16 deletions(-)", "diff": "diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h\nindex 0b1fa57965c..a8df364171b 100644\n--- a/target/arm/tcg/translate-a32.h\n+++ b/target/arm/tcg/translate-a32.h\n@@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);\n TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);\n void gen_set_cpsr(TCGv_i32 var, uint32_t mask);\n void gen_set_condexec(DisasContext *s);\n-void gen_update_pc(DisasContext *s, target_long diff);\n+void gen_update_pc(DisasContext *s, int64_t diff);\n void gen_lookup_tb(DisasContext *s);\n long vfp_reg_offset(bool dp, unsigned reg);\n long neon_full_reg_offset(unsigned reg);\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex 2c8358dd7fa..3e3094a463e 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -27,8 +27,8 @@ typedef struct DisasLabel {\n typedef struct DisasDelayException {\n struct DisasDelayException *next;\n TCGLabel *lab;\n- target_long pc_curr;\n- target_long pc_save;\n+ vaddr pc_curr;\n+ vaddr pc_save;\n int condexec_mask;\n int condexec_cond;\n uint32_t excp;\n@@ -359,14 +359,14 @@ static inline int curr_insn_len(DisasContext *s)\n \n #ifdef TARGET_AARCH64\n void a64_translate_init(void);\n-void gen_a64_update_pc(DisasContext *s, target_long diff);\n+void gen_a64_update_pc(DisasContext *s, int64_t diff);\n extern const TranslatorOps aarch64_translator_ops;\n #else\n static inline void a64_translate_init(void)\n {\n }\n \n-static inline void gen_a64_update_pc(DisasContext *s, target_long diff)\n+static inline void gen_a64_update_pc(DisasContext *s, int64_t diff)\n {\n }\n #endif\n@@ -377,9 +377,9 @@ void arm_gen_test_cc(int cc, TCGLabel *label);\n MemOp pow2_align(unsigned i);\n void unallocated_encoding(DisasContext *s);\n void gen_exception_internal(int excp);\n-void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,\n+void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp,\n uint32_t syn, uint32_t target_el);\n-void gen_exception_insn(DisasContext *s, target_long pc_diff,\n+void gen_exception_insn(DisasContext *s, int64_t pc_diff,\n int excp, uint32_t syn);\n TCGLabel *delay_exception_el(DisasContext *s, int excp,\n uint32_t syn, uint32_t target_el);\ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 982c83ef42a..42b2785fb06 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -250,12 +250,12 @@ static inline int get_a32_user_mem_index(DisasContext *s)\n }\n \n /* The pc_curr difference for an architectural jump. */\n-static target_long jmp_diff(DisasContext *s, target_long diff)\n+static int64_t jmp_diff(DisasContext *s, int64_t diff)\n {\n return diff + (s->thumb ? 4 : 8);\n }\n \n-static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff)\n+static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int64_t diff)\n {\n assert(s->pc_save != -1);\n if (tb_cflags(s->base.tb) & CF_PCREL) {\n@@ -735,7 +735,7 @@ void gen_set_condexec(DisasContext *s)\n }\n }\n \n-void gen_update_pc(DisasContext *s, target_long diff)\n+void gen_update_pc(DisasContext *s, int64_t diff)\n {\n gen_pc_plus_diff(s, cpu_R[15], diff);\n s->pc_save = s->pc_curr + diff;\n@@ -1055,7 +1055,7 @@ static void gen_exception(int excp, uint32_t syndrome)\n tcg_constant_i32(syndrome));\n }\n \n-static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff,\n+static void gen_exception_insn_el_v(DisasContext *s, int64_t pc_diff,\n int excp, uint32_t syn, TCGv_i32 tcg_el)\n {\n if (s->aarch64) {\n@@ -1068,14 +1068,14 @@ static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff,\n s->base.is_jmp = DISAS_NORETURN;\n }\n \n-void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,\n+void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp,\n uint32_t syn, uint32_t target_el)\n {\n gen_exception_insn_el_v(s, pc_diff, excp, syn,\n tcg_constant_i32(target_el));\n }\n \n-void gen_exception_insn(DisasContext *s, target_long pc_diff,\n+void gen_exception_insn(DisasContext *s, int64_t pc_diff,\n int excp, uint32_t syn)\n {\n if (s->aarch64) {\n@@ -1310,7 +1310,7 @@ static void gen_goto_ptr(void)\n * cpu_loop_exec. Any live exit_requests will be processed as we\n * enter the next TB.\n */\n-static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long diff)\n+static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t diff)\n {\n if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) {\n /*\n@@ -1337,7 +1337,7 @@ static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long diff)\n }\n \n /* Jump, specifying which TB number to use if we gen_goto_tb() */\n-static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno)\n+static void gen_jmp_tb(DisasContext *s, int64_t diff, int tbno)\n {\n if (unlikely(s->ss_active)) {\n /* An indirect jump so that we still trigger the debug exception. */\n@@ -1380,7 +1380,7 @@ static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno)\n }\n }\n \n-static inline void gen_jmp(DisasContext *s, target_long diff)\n+static inline void gen_jmp(DisasContext *s, int64_t diff)\n {\n gen_jmp_tb(s, diff, 0);\n }\n", "prefixes": [ "v3", "11/12" ] }