Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2195301/?format=api
{ "id": 2195301, "url": "http://patchwork.ozlabs.org/api/patches/2195301/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210172231.1465275-1-sathyanarayanan.kuppuswamy@linux.intel.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210172231.1465275-1-sathyanarayanan.kuppuswamy@linux.intel.com>", "list_archive_url": null, "date": "2026-02-10T17:22:31", "name": "[v1] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ee7586f81b7c6bdce1b64b390ac0947f13667fe9", "submitter": { "id": 66129, "url": "http://patchwork.ozlabs.org/api/people/66129/?format=api", "name": "Kuppuswamy Sathyanarayanan", "email": "sathyanarayanan.kuppuswamy@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210172231.1465275-1-sathyanarayanan.kuppuswamy@linux.intel.com/mbox/", "series": [ { "id": 491716, "url": "http://patchwork.ozlabs.org/api/series/491716/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491716", "date": "2026-02-10T17:22:31", "name": "[v1] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491716/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195301/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195301/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47110-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=VZKMdPYi;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-47110-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"VZKMdPYi\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=198.175.65.15", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linux.intel.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9T0P0nYFz1xwG\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 11 Feb 2026 04:22:45 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 32D8D3009F3E\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 17:22:41 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 4123B303CAB;\n\tTue, 10 Feb 2026 17:22:38 +0000 (UTC)", "from mgamail.intel.com (mgamail.intel.com [198.175.65.15])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D46830B529;\n\tTue, 10 Feb 2026 17:22:35 +0000 (UTC)", "from orviesa006.jf.intel.com ([10.64.159.146])\n by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 10 Feb 2026 09:22:36 -0800", "from skuppusw-desk2.jf.intel.com ([10.165.154.101])\n by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 10 Feb 2026 09:22:36 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770744158; cv=none;\n b=Jz2HhF90mTz6XUXKQpPvE/ymD6320Mu634me5VVaPwWux8ZBOySwx3L/9uBAS6oiskj7xtGJnW+yx0kpjoyZ/QvxYNcS5hLDjxVFaAfNu72iqBj1vv1ylGM9EbVRfZMf9j/rBASP0TKbfTl2KvHjUqITCeiMidwiEiVv3qXwEpI=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770744158; c=relaxed/simple;\n\tbh=VVlNz7tYeQ5WIseRbGYbp+7DNMt/gMdrva10TSLvSXM=;\n\th=From:To:Cc:Subject:Date:Message-ID:MIME-Version;\n b=g9eOrIVapKz7odM+q/yRbVbvyJTBTmgLn1BLdj7Ajvd6dMiy0lYiqj1I3UP71xULSR+3CZVKqBGv2okGpED4pmHMhqLoC8iH6scDY/0AyGEUQ2NLXMAE0Wvgrfxcfdv3bxXMH3GvHhlv6RaxdngEwtOlHxpfAosDZ+LnFZ5cMnk=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com;\n spf=pass smtp.mailfrom=linux.intel.com;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=VZKMdPYi; arc=none smtp.client-ip=198.175.65.15", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1770744156; x=1802280156;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=VVlNz7tYeQ5WIseRbGYbp+7DNMt/gMdrva10TSLvSXM=;\n b=VZKMdPYiSMmhfUmnYsJN4qpf+DJaP4kuCEWaIFTil3QZvhvOLP48IlKY\n Ob8jMJhqit1IDG3d6tXKVIEfasKwkzX7OCsayNe5aY3FdNQJf/uZAdHZA\n 3QetnpNgBYvb53Ldf/aAC9HdF90YOFpZfImGz+uPBZA+4LMwMkLIwEFuL\n 77X0l9++aWqlzr/KaYEvRhSsIwziZdIPVaue6/Yj/ih/E1jvMweqfvwea\n t3gXZuHy8HgNn4TsemS3Gyyi7uxdpT6ykc2lOSDQ3D46XPZVeWXL673BI\n yYmjV2BbNmlrF8yAILQevriwFjb4Nak06V3VV0UzRxTR6wtIwyq+VvPzv\n A==;", "X-CSE-ConnectionGUID": [ "TN9esrLvS+Ka+63kICjh3Q==", "KfNcJ/zoT9CFxk6Yvuddhw==" ], "X-CSE-MsgGUID": [ "ZqCZ2CdDQ1++cTKWpxjzYQ==", "lNvkrqX2Ree5ScvOaQd6pw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11697\"; a=\"75505383\"", "E=Sophos;i=\"6.21,283,1763452800\";\n d=\"scan'208\";a=\"75505383\"", "E=Sophos;i=\"6.21,283,1763452800\";\n d=\"scan'208\";a=\"211081698\"" ], "X-ExtLoop1": "1", "From": "Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>", "Cc": "Lukas Wunner <lukas@wunner.de>,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v1] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable\n PME status", "Date": "Tue, 10 Feb 2026 09:22:31 -0800", "Message-ID": "\n <20260210172231.1465275-1-sathyanarayanan.kuppuswamy@linux.intel.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "On Intel Catlow Lake platforms, PCH PCIe root ports do not reliably\nupdate PME status registers (PME Status and PME Requester_ID in the\nRoot Status register) during D3hot to D0 transitions, even though PME\ninterrupts are delivered correctly.\n\nThis issue manifests during PCIe hotplug operations as follows:\n\n1. After a hot-remove event, the PCIe port transitions to D3hot and\n the hotplug interrupt enable (HPIE) flag is disabled as the port\n enters low power state.\n\n2. When a hot-add occurs while the port is in D3hot, a PME interrupt\n fires as expected to wake the port.\n\n3. However, the PME interrupt handler finds the PME_Status and\n PME_Requester_ID registers unpopulated, preventing identification\n of which device triggered the PME. The handler returns IRQ_NONE,\n leaving the port in D3hot.\n\n4. Because the port remains in D3hot with HPIE disabled, the hotplug\n driver ignores the hot-add event, resulting in the newly inserted\n device not being recognized.\n\nThe PME interrupt delivery mechanism itself works correctly;\ninterrupts arrive reliably. The problem is purely the missing status\nregister updates. Verification via IOSF-SideBand (IOSF-SB) backdoor\nreads confirms that these registers remain empty when the PME\ninterrupt fires. Neither BIOS nor kernel code is clearing these\nregisters.\n\nThis issue is present in all steppings of Catlow Lake PCH and affects\ncustomers in production deployments. A public hardware errata document\nis not yet available. While the document is being published, we need a\nquirk to address the issue for existing customers.\n\nAlternative approaches were considered to avoid modifying the pciehp\ndriver. We attempted to keep these ports in D0 state by calling\npm_runtime_disable() in the quirk. Although this approach works for\nmost cases, it fails to provide wakeup when the system enters suspend\nstate. Another option of modifying the PME configuration to force\npci_target_state() to select D0 also did not help, as runtime PM\nstill transitions the port to D3hot.\n\nAdd a PCI quirk (PCI_DEV_FLAGS_NO_PME_WAKEUP) for affected Catlow\nLake PCH PCIe root ports that allows the hotplug interrupt handler to\nprocess events regardless of the port power state, bypassing the\nbroken PME-based wakeup dependency.\n\nThe quirk is applied only to Catlow PCH PCIe root ports (device IDs\n0x7a30 through 0x7a4b). Catlow CPU PCIe ports are not affected as\nthey are not hotplug-capable. Systems with reliable PME signaling\ncontinue to operate normally.\n\nSigned-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>\n---\n drivers/pci/hotplug/pciehp_hpc.c | 4 ++-\n drivers/pci/quirks.c | 45 ++++++++++++++++++++++++++++++++\n include/linux/pci.h | 2 ++\n 3 files changed, 50 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c\nindex bcc51b26d03d..e5036bb79a08 100644\n--- a/drivers/pci/hotplug/pciehp_hpc.c\n+++ b/drivers/pci/hotplug/pciehp_hpc.c\n@@ -631,7 +631,9 @@ static irqreturn_t pciehp_isr(int irq, void *dev_id)\n \t * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).\n \t */\n \tif (pdev->current_state == PCI_D3cold ||\n-\t (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))\n+\t (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) &&\n+\t !pciehp_poll_mode &&\n+\t !(pdev->dev_flags & PCI_DEV_FLAGS_NO_PME_WAKEUP)))\n \t\treturn IRQ_NONE;\n \n \t/*\ndiff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 280cd50d693b..b22eb8554ab0 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -6340,3 +6340,48 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev)\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout);\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout);\n #endif\n+\n+/*\n+ * When a PCIe port is in D3hot, the hotplug driver depends on PME\n+ * to wake the port back to D0 and then process any hotplug-related\n+ * state changes. On Intel Catlow Lake platforms, PCH PCIe root ports\n+ * do not reliably update PME state during D3hot to D0 transitions.\n+ *\n+ * Apply a quirk to disable PME-based wakeup requirements for these\n+ * specific ports, allowing the hotplug driver to handle events\n+ * independently of the port power state.\n+ */\n+static void quirk_intel_catlow_pcie_no_pme_wakeup(struct pci_dev *dev)\n+{\n+\tdev->dev_flags |= PCI_DEV_FLAGS_NO_PME_WAKEUP;\n+\tpci_info(dev, \"Catlow PCH port: PME unreliable, bypassing PME-based wakeup for hotplug\\n\");\n+}\n+/* Apply quirk to Catlow Lake PCH root ports (0x7a30 - 0x7a4b) */\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a30, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a31, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a32, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a33, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a34, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a35, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a36, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a37, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a38, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a39, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3a, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3b, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3c, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3d, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3e, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a3f, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a40, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a41, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a42, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a43, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a44, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a45, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a46, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a47, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a48, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a49, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a4a, quirk_intel_catlow_pcie_no_pme_wakeup);\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x7a4b, quirk_intel_catlow_pcie_no_pme_wakeup);\ndiff --git a/include/linux/pci.h b/include/linux/pci.h\nindex b5cc0c2b9906..e4a95b36e4a0 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -248,6 +248,8 @@ enum pci_dev_flags {\n \tPCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),\n \t/* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */\n \tPCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13),\n+\t/* Device does not reliably update PME status to wakeup from D3 to D0 */\n+\tPCI_DEV_FLAGS_NO_PME_WAKEUP = (__force pci_dev_flags_t) (1 << 14),\n };\n \n enum pci_irq_reroute_variant {\n", "prefixes": [ "v1" ] }