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GET /api/patches/2195222/?format=api
{ "id": 2195222, "url": "http://patchwork.ozlabs.org/api/patches/2195222/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260210151459.2348758-15-raymondmaoca@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210151459.2348758-15-raymondmaoca@gmail.com>", "list_archive_url": null, "date": "2026-02-10T15:14:57", "name": "[v2,14/16] power: pmic: add support for Spacemit P1 PMIC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0dac621473dddb991378d456f219b893e4fe8692", "submitter": { "id": 91989, "url": "http://patchwork.ozlabs.org/api/people/91989/?format=api", "name": "Raymond Mao", "email": "raymondmaoca@gmail.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260210151459.2348758-15-raymondmaoca@gmail.com/mbox/", "series": [ { "id": 491690, "url": "http://patchwork.ozlabs.org/api/series/491690/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491690", "date": "2026-02-10T15:14:43", "name": "Add board support for Spacemit K1 SoC in SPL", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491690/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195222/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195222/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=MZjKL36X;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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It contains voltage\nregulators, GPIOs and Watchdog.\n\nSigned-off-by: Raymond Mao <raymond.mao@riscstar.com>\nSigned-off-by: Guodong Xu <guodong.xu@riscstar.com>\n---\n drivers/power/pmic/Kconfig | 17 +++\n drivers/power/pmic/Makefile | 1 +\n drivers/power/pmic/pmic_spacemit_p1.c | 94 +++++++++++++++\n include/power/spacemit_p1.h | 163 ++++++++++++++++++++++++++\n 4 files changed, 275 insertions(+)\n create mode 100644 drivers/power/pmic/pmic_spacemit_p1.c\n create mode 100644 include/power/spacemit_p1.h", "diff": "diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig\nindex b1a5b1c2a1f..19a0c4a77dd 100644\n--- a/drivers/power/pmic/Kconfig\n+++ b/drivers/power/pmic/Kconfig\n@@ -433,6 +433,23 @@ config PMIC_RAA215300\n \t support and several voltage regulators. For now, this driver simply\n \t allows register access and will bind the sysreset driver\n \t (CONFIG_SYSRESET_RAA215300) if it is enabled.\n+\n+config PMIC_SPACEMIT_P1\n+\tbool \"Enable driver for Spacemit P1 power management chip\"\n+\tdepends on DM_PMIC\n+\thelp\n+\t The P1 PMIC integrates multiple functions including\n+\t voltage regulators, a watchdog timer, GPIO interfaces, and a\n+\t real-time clock.\n+\n+config SPL_PMIC_SPACEMIT_P1\n+\tbool \"Enable driver for Spacemit P1 power management chip in SPL\"\n+\tdepends on SPL_DM_PMIC\n+\thelp\n+\t The P1 PMIC integrates multiple functions including\n+\t voltage regulators, a watchdog timer, GPIO interfaces, and a\n+\t real-time clock.\n+\n endif\n \n config PMIC_TPS65217\ndiff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile\nindex 6bebffb05a6..dfe60223f00 100644\n--- a/drivers/power/pmic/Makefile\n+++ b/drivers/power/pmic/Makefile\n@@ -39,6 +39,7 @@ obj-$(CONFIG_PMIC_TPS65941) += tps65941.o\n obj-$(CONFIG_PMIC_RAA215300) += raa215300.o\n obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o\n obj-$(CONFIG_$(PHASE_)DM_PMIC_CPCAP) += cpcap.o\n+obj-$(CONFIG_$(PHASE_)PMIC_SPACEMIT_P1) += pmic_spacemit_p1.o\n \n ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)\n obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o\ndiff --git a/drivers/power/pmic/pmic_spacemit_p1.c b/drivers/power/pmic/pmic_spacemit_p1.c\nnew file mode 100644\nindex 00000000000..46c5926874c\n--- /dev/null\n+++ b/drivers/power/pmic/pmic_spacemit_p1.c\n@@ -0,0 +1,94 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2025-2026 RISCstar Ltd.\n+ */\n+\n+#include <dm.h>\n+#include <power/pmic.h>\n+#include <power/spacemit_p1.h>\n+\n+static int pmic_p1_reg_count(struct udevice *dev)\n+{\n+\treturn P1_MAX_REGS;\n+}\n+\n+static int pmic_p1_write(struct udevice *dev, uint reg, const u8 *buffer,\n+\t\t\t int len)\n+{\n+\tint ret;\n+\n+\tret = dm_i2c_write(dev, reg, buffer, len);\n+\tif (ret)\n+\t\tpr_err(\"%s write error on register %02x\\n\", dev->name, reg);\n+\n+\treturn ret;\n+}\n+\n+static int pmic_p1_read(struct udevice *dev, uint reg, u8 *buffer,\n+\t\t\tint len)\n+{\n+\tint ret;\n+\n+\tret = dm_i2c_read(dev, reg, buffer, len);\n+\tif (ret)\n+\t\tpr_err(\"%s read error on register %02x\\n\", dev->name, reg);\n+\n+\treturn ret;\n+}\n+\n+static const struct pmic_child_info p1_children_info[] = {\n+\t{ .prefix = \"buck\",\t\t.driver = P1_BUCK_DRIVER },\n+\t{ .prefix = \"aldo\",\t\t.driver = P1_ALDO_DRIVER },\n+\t{ .prefix = \"dldo\",\t\t.driver = P1_DLDO_DRIVER },\n+\t{ },\n+};\n+\n+static int pmic_p1_bind(struct udevice *dev)\n+{\n+\tconst struct pmic_child_info *p1_children_info =\n+\t\t\t(struct pmic_child_info *)dev_get_driver_data(dev);\n+\tofnode regulators_node;\n+\tint children;\n+\n+\tregulators_node = dev_read_subnode(dev, \"regulators\");\n+\tif (!ofnode_valid(regulators_node)) {\n+\t\tdebug(\"%s regulators subnode not found\\n\", dev->name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tchildren = pmic_bind_children(dev, regulators_node,\n+\t\t\t\t p1_children_info);\n+\tif (!children)\n+\t\tdebug(\"%s has no children (regulators)\\n\", dev->name);\n+\n+\treturn 0;\n+}\n+\n+static int pmic_p1_probe(struct udevice *dev)\n+{\n+\treturn 0;\n+}\n+\n+static struct dm_pmic_ops pmic_p1_ops = {\n+\t.reg_count\t= pmic_p1_reg_count,\n+\t.read\t\t= pmic_p1_read,\n+\t.write\t\t= pmic_p1_write,\n+};\n+\n+static const struct udevice_id pmic_p1_match[] = {\n+\t{\n+\t\t.compatible = \"spacemit,p1\",\n+\t\t.data = (ulong)&p1_children_info,\n+\t}, {\n+\t\t/* sentinel */\n+\t}\n+};\n+\n+U_BOOT_DRIVER(pmic_p1) = {\n+\t.name\t\t= \"pmic_p1\",\n+\t.id\t\t= UCLASS_PMIC,\n+\t.of_match\t= pmic_p1_match,\n+\t.bind\t\t= pmic_p1_bind,\n+\t.probe\t\t= pmic_p1_probe,\n+\t.ops\t\t= &pmic_p1_ops,\n+};\ndiff --git a/include/power/spacemit_p1.h b/include/power/spacemit_p1.h\nnew file mode 100644\nindex 00000000000..ef5a45e8cec\n--- /dev/null\n+++ b/include/power/spacemit_p1.h\n@@ -0,0 +1,163 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (C) 2025-2026 RISCstar Ltd.\n+ */\n+\n+#ifndef __SPACEMIT_P1_H_\n+#define __SPACEMIT_P1_H_\n+\n+#define P1_MAX_REGS\t\t\t0xA8\n+\n+#define P1_REG_ID\t\t\t0x0\n+\n+#define P1_ID\t\t\t\t0x2\n+\n+#define P1_REG_BUCK1_CTRL\t\t0x47\n+#define P1_REG_BUCK2_CTRL\t\t0x4a\n+#define P1_REG_BUCK3_CTRL\t\t0x4d\n+#define P1_REG_BUCK4_CTRL\t\t0x50\n+#define P1_REG_BUCK5_CTRL\t\t0x53\n+#define P1_REG_BUCK6_CTRL\t\t0x56\n+\n+#define P1_REG_BUCK1_VSEL\t\t0x48\n+#define P1_REG_BUCK2_VSEL\t\t0x4b\n+#define P1_REG_BUCK3_VSEL\t\t0x4e\n+#define P1_REG_BUCK4_VSEL\t\t0x51\n+#define P1_REG_BUCK5_VSEL\t\t0x54\n+#define P1_REG_BUCK6_VSEL\t\t0x57\n+\n+#define P1_REG_BUCK1_SVSEL\t\t0x49\n+#define P1_REG_BUCK2_SVSEL\t\t0x4c\n+#define P1_REG_BUCK3_SVSEL\t\t0x4f\n+#define P1_REG_BUCK4_SVSEL\t\t0x52\n+#define P1_REG_BUCK5_SVSEL\t\t0x55\n+#define P1_REG_BUCK6_SVSEL\t\t0x58\n+\n+#define P1_BUCK_CTRL(x)\t\t\t(0x47 + ((x) - 1) * 3)\n+#define P1_BUCK_VSEL(x)\t\t\t(0x48 + ((x) - 1) * 3)\n+#define P1_BUCK_SVSEL(x)\t\t(0x49 + ((x) - 1) * 3)\n+\n+#define BUCK_VSEL_MASK\t\t\t0xff\n+#define BUCK_EN_MASK\t\t\t0x1\n+#define BUCK_SVSEL_MASK\t\t\t0xff\n+\n+#define P1_REG_ALDO1_CTRL\t\t0x5b\n+#define P1_REG_ALDO2_CTRL\t\t0x5e\n+#define P1_REG_ALDO3_CTRL\t\t0x61\n+#define P1_REG_ALDO4_CTRL\t\t0x64\n+\n+#define P1_REG_ALDO1_VOLT\t\t0x5c\n+#define P1_REG_ALDO2_VOLT\t\t0x5f\n+#define P1_REG_ALDO3_VOLT\t\t0x62\n+#define P1_REG_ALDO4_VOLT\t\t0x65\n+\n+#define P1_REG_ALDO1_SVOLT\t\t0x5d\n+#define P1_REG_ALDO2_SVOLT\t\t0x60\n+#define P1_REG_ALDO3_SVOLT\t\t0x63\n+#define P1_REG_ALDO4_SVOLT\t\t0x66\n+\n+#define P1_ALDO_CTRL(x)\t\t\t(0x5b + ((x) - 1) * 3)\n+#define P1_ALDO_VOLT(x)\t\t\t(0x5c + ((x) - 1) * 3)\n+#define P1_ALDO_SVOLT(x)\t\t(0x5d + ((x) - 1) * 3)\n+\n+#define ALDO_SVSEL_MASK\t\t\t0x7f\n+#define ALDO_EN_MASK\t\t\t0x1\n+#define ALDO_VSEL_MASK\t\t\t0x7f\n+\n+#define P1_REG_DLDO1_CTRL\t\t0x67\n+#define P1_REG_DLDO2_CTRL\t\t0x6a\n+#define P1_REG_DLDO3_CTRL\t\t0x6d\n+#define P1_REG_DLDO4_CTRL\t\t0x70\n+#define P1_REG_DLDO5_CTRL\t\t0x73\n+#define P1_REG_DLDO6_CTRL\t\t0x76\n+#define P1_REG_DLDO7_CTRL\t\t0x79\n+\n+#define P1_REG_DLDO1_VOLT\t\t0x68\n+#define P1_REG_DLDO2_VOLT\t\t0x6b\n+#define P1_REG_DLDO3_VOLT\t\t0x6e\n+#define P1_REG_DLDO4_VOLT\t\t0x71\n+#define P1_REG_DLDO5_VOLT\t\t0x74\n+#define P1_REG_DLDO6_VOLT\t\t0x77\n+#define P1_REG_DLDO7_VOLT\t\t0x7a\n+\n+#define P1_REG_DLDO1_SVOLT\t\t0x69\n+#define P1_REG_DLDO2_SVOLT\t\t0x6c\n+#define P1_REG_DLDO3_SVOLT\t\t0x6f\n+#define P1_REG_DLDO4_SVOLT\t\t0x72\n+#define P1_REG_DLDO5_SVOLT\t\t0x75\n+#define P1_REG_DLDO6_SVOLT\t\t0x78\n+#define P1_REG_DLDO7_SVOLT\t\t0x7b\n+\n+#define P1_DLDO_CTRL(x)\t\t\t(0x67 + ((x) - 1) * 3)\n+#define P1_DLDO_VOLT(x)\t\t\t(0x68 + ((x) - 1) * 3)\n+#define P1_DLDO_SVOLT(x)\t\t(0x69 + ((x) - 1) * 3)\n+\n+#define DLDO_SVSEL_MASK\t\t\t0x7f\n+#define DLDO_EN_MASK\t\t\t0x1\n+#define DLDO_VSEL_MASK\t\t\t0x7f\n+\n+#define P1_REG_SWITCH_CTRL\t\t0x59\n+#define P1_SWTICH_EN_MASK\t\t0x1\n+\n+#define P1_REG_SWITCH_PWRKEY_EVENT_CTRL\t0x97\n+#define P1_SWITCH_PWRKEY_EVENT_EN_MSK\t0xf\n+\n+#define P1_REG_SWITCH_PWRKEY_INIT_CTRL\t0x9e\n+#define P1_SWITCH_PWRKEY_INT_EN_MSK\t0xf\n+\n+/* Watchdog Timer Registers */\n+#define P1_WDT_CTRL\t\t\t0x44\n+#define P1_PWR_CTRL0\t\t\t0x7C\n+#define P1_PWR_CTRL2\t\t\t0x7E\n+#define P1_PWR_CTRL2_MSK\t\t0xff\n+\n+/* Watchdog Timer Control Bits */\n+#define P1_WDT_CLEAR_STATUS\t\t0x1\n+#define P1_SW_RST\t\t\t0x2\n+#define P1_WDT_RESET_ENABLE\t\t0x80\n+#define P1_WDT_ENABLE\t\t\t0x8\n+#define P1_WDT_TIMEOUT_1S\t\t0x0\n+#define P1_WDT_TIMEOUT_4S\t\t0x1\n+#define P1_WDT_TIMEOUT_8S\t\t0x2\n+#define P1_WDT_TIMEOUT_16S\t\t0x3\n+\n+#define P1_RTC_TICK_CTRL\t\t0x1d\n+#define P1_RTC_TICK_CTRL_MSK\t\t0x7f\n+\n+#define P1_RTC_TICK_EVENT\t\t0x92\n+#define P1_RTC_TICK_EVENT_MSK\t\t0x3f\n+\n+#define P1_RTC_TICK_IRQ\t\t\t0x99\n+#define P1_RTC_TICK_IRQ_MSK\t\t0x3f\n+\n+#define P1_REG_ALIVE\t\t\t0xab\n+#define P1_ALIVE_MSK\t\t\t0x7\n+#define SYS_REBOOT_FLAG_BIT\t\t0x2\n+\n+/* SWITCH ID */\n+enum {\n+\tP1_ID_SWITCH1,\n+\tP1_ID_SWITCH1_PWRKEY_EVENT,\n+\tP1_ID_SWITCH1_PWRKEY_INT,\n+\tP1_ID_SWITCH_RTC_TICK_CTRL,\n+\tP1_ID_SWITCH_RTC_TICK_EVENT,\n+\tP1_ID_SWITCH_RTC_TCK_IRQ,\n+\tP1_ID_SWITCH_POWER_DOWN,\n+\tP1_ID_SWITCH_CHARGING_FLAG,\n+};\n+\n+/* POWERKEY events */\n+enum {\n+\tPWRKEY_RISING_EVENT = 1,\n+\tPWRKEY_FAILING_EVENT = 2,\n+\tPWRKEY_SHORT_PRESS_EVENT = 4,\n+\tPWRKEY_LONG_PRESS_EVENT = 8,\n+};\n+\n+#define P1_BUCK_DRIVER\t\t\t\"p1_buck\"\n+#define P1_ALDO_DRIVER\t\t\t\"p1_aldo\"\n+#define P1_DLDO_DRIVER\t\t\t\"p1_dldo\"\n+#define P1_SWITCH_DRIVER\t\t\"p1_switch\"\n+#define P1_WDT_DRIVER\t\t\t\"p1_wdt\"\n+\n+#endif /* __SPACEMIT_P1_H_ */\n", "prefixes": [ "v2", "14/16" ] }