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GET /api/patches/2195221/?format=api
{ "id": 2195221, "url": "http://patchwork.ozlabs.org/api/patches/2195221/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260210151459.2348758-14-raymondmaoca@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210151459.2348758-14-raymondmaoca@gmail.com>", "list_archive_url": null, "date": "2026-02-10T15:14:56", "name": "[v2,13/16] spacemit: k1: Add DDR firmware support to SPL", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "762439646b9382706c1b8fb97786f94b8562568a", "submitter": { "id": 91989, "url": "http://patchwork.ozlabs.org/api/people/91989/?format=api", "name": "Raymond Mao", "email": "raymondmaoca@gmail.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260210151459.2348758-14-raymondmaoca@gmail.com/mbox/", "series": [ { "id": 491690, "url": "http://patchwork.ozlabs.org/api/series/491690/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491690", "date": "2026-02-10T15:14:43", "name": "Add board support for Spacemit K1 SoC in SPL", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491690/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195221/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195221/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=RrSRzQk+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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The firmware\npath can be specified via the DDR_FW_FILE environment variable. If\nthe firmware is not found, an empty placeholder file is created to\nallow the build to proceed without DDR initialization support.\n\nSigned-off-by: Raymond Mao <raymond.mao@riscstar.com>\nSigned-off-by: Guodong Xu <guodong.xu@riscstar.com>\n---\n arch/riscv/dts/k1-spl.dts | 24 +++++++-\n board/spacemit/k1/Makefile | 20 ++++++\n board/spacemit/k1/spl.c | 122 +++++++++++++++++++++++++++++++++++++\n 3 files changed, 165 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1-spl.dts\nindex 74e9957b83a..e118767e6db 100644\n--- a/arch/riscv/dts/k1-spl.dts\n+++ b/arch/riscv/dts/k1-spl.dts\n@@ -7,7 +7,6 @@\n /dts-v1/;\n \n #include \"k1.dtsi\"\n-#include \"binman.dtsi\"\n \n / {\n \tmodel = \"spacemit k1 spl\";\n@@ -20,6 +19,29 @@\n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n \t};\n+\n+\tbinman {\n+\t\tu-boot-spl-ddr {\n+\t\t\ttype = \"section\";\n+\t\t\tfilename = \"u-boot-spl-ddr.bin\";\n+\t\t\tpad-byte = <0xff>;\n+\n+\t\t\tu-boot-spl {\n+\t\t\t};\n+\n+\t\t\tddr-fw {\n+\t\t\t\ttype = \"blob\";\n+\t\t\t\tfilename = \"ddr_fw.bin\";\n+\t\t\t\talign = <64>;\n+\t\t\t};\n+\n+\t\t\tu-boot-any {\n+\t\t\t\ttype = \"section\";\n+\t\t\t\tsize = <0>;\n+\t\t\t\toffset = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n };\n \n &vctcxo_1m {\ndiff --git a/board/spacemit/k1/Makefile b/board/spacemit/k1/Makefile\nindex f9cbf4b0e06..827b1e507c7 100644\n--- a/board/spacemit/k1/Makefile\n+++ b/board/spacemit/k1/Makefile\n@@ -5,3 +5,23 @@\n \n obj-y := board.o\n obj-$(CONFIG_SPL_BUILD) += spl.o\n+\n+DDR_FW_SRC ?= $(DDR_FW_FILE)\n+FW_TARGET = $(objtree)/ddr_fw.bin\n+\n+$(obj)/spl.o: $(FW_TARGET)\n+\n+$(FW_TARGET):\n+\t@echo \"Preparing DDR firmware...\"\n+\t@if [ -n \"$(DDR_FW_SRC)\" ] && [ -f \"$(DDR_FW_SRC)\" ]; then \\\n+\t\techo \" Copying from: $(DDR_FW_SRC)\"; \\\n+\t\tcp \"$(DDR_FW_SRC)\" $@; \\\n+\telif [ -f $@ ]; then \\\n+\t\techo \" Using existing $@\"; \\\n+\telse \\\n+\t\techo \" Note: No firmware found, creating empty file\"; \\\n+\t\techo \" (Set DDR_FW_FILE to specify firmware location)\"; \\\n+\t\ttouch $@; \\\n+\tfi\n+\n+clean-files += $(FW_TARGET)\ndiff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c\nindex 182e833849d..95b61f5aa90 100644\n--- a/board/spacemit/k1/spl.c\n+++ b/board/spacemit/k1/spl.c\n@@ -4,8 +4,11 @@\n */\n \n #include <asm/io.h>\n+#include <binman.h>\n+#include <binman_sym.h>\n #include <clk.h>\n #include <clk-uclass.h>\n+#include <cpu_func.h>\n #include <configs/k1.h>\n #include <dm/device.h>\n #include <dm/uclass.h>\n@@ -14,6 +17,7 @@\n #include <log.h>\n #include <spl.h>\n #include <tlv_eeprom.h>\n+#include \"tlv_codes.h\"\n \n #define MUX_MODE4\t\t4\n #define EDGE_NONE\t\tBIT(6)\n@@ -26,6 +30,29 @@\n #define MFP_GPIO_84\t\t0xd401e154\n #define MFP_GPIO_85\t\t0xd401e158\n \n+#define DDR_FIRMWARE_BASE\t0xc082d000\n+\n+#define DDR_DEFAULT_CS_NUM 2\n+#define DDR_DEFAULT_TYPE \"LPDDR4X\"\n+#define DDR_DEFAULT_TX_ODT 80\n+#define DDR_DEFAULT_DATA_RATE 2400\n+\n+#define MAGIC_NUM\t\t0xaa55aa55\n+\n+typedef void (*puts_func_t)(const char *s);\n+typedef int (*ddr_init_func_t)(u64 ddr_base, u32 cs_num, u32 data_rate,\n+\t\t\t puts_func_t puts);\n+\n+struct ddr_cfg {\n+\tu32 data_rate;\n+\tu32 cs_num;\n+\tu32 tx_odt;\n+\tu8 type[I2C_BUF_SIZE];\n+};\n+\n+binman_sym_declare(ulong, ddr_fw, image_pos);\n+binman_sym_declare(ulong, ddr_fw, size);\n+\n static void reset_early_init(void)\n {\n \tstruct udevice *dev;\n@@ -119,6 +146,100 @@ void serial_early_init(void)\n \t\tpanic(\"Serial uclass init failed: %d\\n\", ret);\n }\n \n+/* Set default value for DDR chips */\n+static void ddr_cfg_init(struct ddr_cfg *cfg)\n+{\n+\tmemset(cfg, 0, sizeof(struct ddr_cfg));\n+\tcfg->data_rate = DDR_DEFAULT_DATA_RATE;\n+\tcfg->cs_num = DDR_DEFAULT_CS_NUM;\n+\tcfg->tx_odt = DDR_DEFAULT_TX_ODT;\n+\tstrcpy(cfg->type, DDR_DEFAULT_TYPE);\n+}\n+\n+int read_ddr_info(struct ddr_cfg *cfg)\n+{\n+\tu8 eeprom_data[TLV_TOTAL_LEN_MAX], *p;\n+\tstruct tlvinfo_header *tlv_hdr;\n+\tstruct tlvinfo_tlv *tlv_entry;\n+\tu32 size, entry_size;\n+\tint ret, i;\n+\tbool found = false;\n+\n+\tif (!cfg)\n+\t\treturn -EINVAL;\n+\tddr_cfg_init(cfg);\n+\tret = read_tlvinfo_tlv_eeprom(eeprom_data, &tlv_hdr,\n+\t\t\t\t &tlv_entry, i);\n+\tif (ret)\n+\t\treturn ret;\n+\tp = (u8 *)tlv_entry;\n+\tfor (i = 0; i < tlv_hdr->totallen; ) {\n+\t\tswitch (tlv_entry->type) {\n+\t\tcase TLV_CODE_DDR_CSNUM:\n+\t\t\tmemcpy(&cfg->cs_num, &tlv_entry->value[0], 1);\n+\t\t\tfound = true;\n+\t\t\tbreak;\n+\t\tcase TLV_CODE_DDR_TYPE:\n+\t\t\tsize = min((u32)tlv_entry->length, (u32)I2C_BUF_SIZE);\n+\t\t\tmemcpy(&cfg->type[0], &tlv_entry->value[0], size);\n+\t\t\tfound = true;\n+\t\t\tbreak;\n+\t\tcase TLV_CODE_DDR_DATARATE:\n+\t\t\tmemcpy(&cfg->data_rate, &tlv_entry->value[0], 2);\n+\t\t\tfound = true;\n+\t\t\tbreak;\n+\t\tcase TLV_CODE_DDR_TX_ODT:\n+\t\t\tmemcpy(&cfg->tx_odt, &tlv_entry->value[0], 1);\n+\t\t\tfound = true;\n+\t\t\tbreak;\n+\t\tcase TLV_CODE_CRC_32:\n+\t\t\tif (!found)\n+\t\t\t\treturn -ENOENT;\n+\t\t\treturn 0;\n+\t\t}\n+\t\tentry_size = tlv_entry->length + sizeof(struct tlvinfo_tlv);\n+\t\ti += entry_size;\n+\t\tp += entry_size;\n+\t\ttlv_entry = (struct tlvinfo_tlv *)p;\n+\t}\n+\tif (!found)\n+\t\treturn -ENOENT;\n+\treturn 0;\n+}\n+\n+/* Load DDR firmware */\n+void ddr_early_init(void)\n+{\n+\tvoid __iomem *src, *dst;\n+\tulong pos, size;\n+\tstruct ddr_cfg cfg;\n+\tddr_init_func_t ddr_init;\n+\n+\tpos = binman_sym(ulong, ddr_fw, image_pos);\n+\tsize = binman_sym(ulong, ddr_fw, size);\n+\tsrc = (void __iomem *)pos;\n+\tdst = (void __iomem *)(DDR_FIRMWARE_BASE);\n+\tlog_info(\"DDR firmware: [0x%lx]:0x%x, size:0x%lx\\n\", pos, readl(src), size);\n+\tmemcpy((u8 *)dst, (u8 *)src, size);\n+\tsize = round_up(size, 64);\n+\tflush_dcache_range((u32)(u64)dst, (u32)(u64)dst + size);\n+\n+\tread_ddr_info(&cfg);\n+\tddr_init = (ddr_init_func_t)DDR_FIRMWARE_BASE;\n+#ifdef DEBUG\n+\tddr_init(0xc0000000, cfg.cs_num, cfg.data_rate, puts);\n+#else\n+\tddr_init(0xc0000000, cfg.cs_num, cfg.data_rate, NULL);\n+#endif\n+\twritel(MAGIC_NUM, (void __iomem *)0x00000000);\n+\tflush_dcache_range(0, 64);\n+\tinvalidate_dcache_range(0, 64);\n+\tif (readl((void __iomem *)0x00000000) == MAGIC_NUM)\n+\t\tlog_info(\"DDR is ready\\n\");\n+\telse\n+\t\tlog_info(\"DDR isn't invalid\\n\");\n+}\n+\n void board_init_f(ulong dummy)\n {\n \tu8 i2c_buf[I2C_BUF_SIZE];\n@@ -142,6 +263,7 @@ void board_init_f(ulong dummy)\n \t\tlog_info(\"Fail to detect board:%d\\n\", ret);\n \telse\n \t\tlog_info(\"Get board name:%s\\n\", (char *)i2c_buf);\n+\tddr_early_init();\n }\n \n u32 spl_boot_device(void)\n", "prefixes": [ "v2", "13/16" ] }