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GET /api/patches/2195214/?format=api
{ "id": 2195214, "url": "http://patchwork.ozlabs.org/api/patches/2195214/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260210151459.2348758-7-raymondmaoca@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210151459.2348758-7-raymondmaoca@gmail.com>", "list_archive_url": null, "date": "2026-02-10T15:14:49", "name": "[v2,06/16] dts: k1: import dts file from upstream folder", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0ecec4d47c41d110c4ac74535064abf39e7d3302", "submitter": { "id": 91989, "url": "http://patchwork.ozlabs.org/api/people/91989/?format=api", "name": "Raymond Mao", "email": "raymondmaoca@gmail.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260210151459.2348758-7-raymondmaoca@gmail.com/mbox/", "series": [ { "id": 491690, "url": "http://patchwork.ozlabs.org/api/series/491690/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491690", "date": "2026-02-10T15:14:43", "name": "Add board support for Spacemit K1 SoC in SPL", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491690/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195214/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195214/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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<raymondmaoca@gmail.com>", "To": "u-boot@lists.denx.de", "Cc": "uboot@riscstar.com, u-boot-spacemit@groups.io, raymond.mao@riscstar.com,\n rick@andestech.com, ycliang@andestech.com, trini@konsulko.com,\n lukma@denx.de, hs@nabladev.com, jh80.chung@samsung.com, peng.fan@nxp.com,\n xypron.glpk@gmx.de, randolph@andestech.com, dlan@gentoo.org,\n junhui.liu@pigmoral.tech, neil.armstrong@linaro.org,\n quentin.schulz@cherry.de, samuel@sholland.org, raymondmaoca@gmail.com", "Subject": "[PATCH v2 06/16] dts: k1: import dts file from upstream folder", "Date": "Tue, 10 Feb 2026 10:14:49 -0500", "Message-Id": "<20260210151459.2348758-7-raymondmaoca@gmail.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260210151459.2348758-1-raymondmaoca@gmail.com>", "References": "<20260210151459.2348758-1-raymondmaoca@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Raymond Mao <raymond.mao@riscstar.com>\n\nImport K1.dtsi from upstream folder.\n\nSigned-off-by: Raymond Mao <raymond.mao@riscstar.com>\n---\n arch/riscv/dts/k1.dtsi | 562 +++++++++++++++++++++++++++++++++--------\n 1 file changed, 460 insertions(+), 102 deletions(-)", "diff": "diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi\nindex 9c203eb4b79..20f1cb57462 100644\n--- a/arch/riscv/dts/k1.dtsi\n+++ b/arch/riscv/dts/k1.dtsi\n@@ -1,8 +1,11 @@\n-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+// SPDX-License-Identifier: GPL-2.0 OR MIT\n /*\n * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>\n */\n \n+#include <dt-bindings/clock/spacemit,k1-syscon.h>\n+#include <dt-bindings/reset/spacemit-k1-reset.h>\n+\n /dts-v1/;\n / {\n \t#address-cells = <2>;\n@@ -10,18 +13,6 @@\n \tmodel = \"SpacemiT K1\";\n \tcompatible = \"spacemit,k1\";\n \n-\taliases {\n-\t\tserial0 = &uart0;\n-\t\tserial1 = &uart2;\n-\t\tserial2 = &uart3;\n-\t\tserial3 = &uart4;\n-\t\tserial4 = &uart5;\n-\t\tserial5 = &uart6;\n-\t\tserial6 = &uart7;\n-\t\tserial7 = &uart8;\n-\t\tserial8 = &uart9;\n-\t};\n-\n \tcpus {\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n@@ -318,6 +309,36 @@\n \t\t};\n \t};\n \n+\tclocks {\n+\t\tvctcxo_1m: clock-1m {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\tclock-frequency = <1000000>;\n+\t\t\tclock-output-names = \"vctcxo_1m\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\n+\t\tvctcxo_24m: clock-24m {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\tclock-frequency = <24000000>;\n+\t\t\tclock-output-names = \"vctcxo_24m\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\n+\t\tvctcxo_3m: clock-3m {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\tclock-frequency = <3000000>;\n+\t\t\tclock-output-names = \"vctcxo_3m\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\n+\t\tosc_32k: clock-32k {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\tclock-frequency = <32000>;\n+\t\t\tclock-output-names = \"osc_32k\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\t};\n+\n \tsoc: soc {\n \t\tcompatible = \"simple-bus\";\n \t\tinterrupt-parent = <&plic>;\n@@ -326,96 +347,267 @@\n \t\tdma-noncoherent;\n \t\tranges;\n \n-\t\tuart0: serial@d4017000 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017000 0x0 0x100>;\n-\t\t\tinterrupts = <42>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tsyscon_rcpu: system-controller@c0880000 {\n+\t\t\tcompatible = \"spacemit,k1-syscon-rcpu\";\n+\t\t\treg = <0x0 0xc0880000 0x0 0x2048>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\tsyscon_rcpu2: system-controller@c0888000 {\n+\t\t\tcompatible = \"spacemit,k1-syscon-rcpu2\";\n+\t\t\treg = <0x0 0xc0888000 0x0 0x28>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\tsyscon_apbc: system-controller@d4015000 {\n+\t\t\tcompatible = \"spacemit,k1-syscon-apbc\";\n+\t\t\treg = <0x0 0xd4015000 0x0 0x1000>;\n+\t\t\tclocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,\n+\t\t\t\t <&vctcxo_24m>;\n+\t\t\tclock-names = \"osc\", \"vctcxo_1m\", \"vctcxo_3m\",\n+\t\t\t\t \"vctcxo_24m\";\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\tgpio: gpio@d4019000 {\n+\t\t\tcompatible = \"spacemit,k1-gpio\";\n+\t\t\treg = <0x0 0xd4019000 0x0 0x100>;\n+\t\t\tclocks = <&syscon_apbc CLK_GPIO>,\n+\t\t\t\t <&syscon_apbc CLK_GPIO_BUS>;\n+\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <3>;\n+\t\t\tinterrupts = <58>;\n+\t\t\tinterrupt-parent = <&plic>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\tgpio-ranges = <&pinctrl 0 0 0 32>,\n+\t\t\t\t <&pinctrl 1 0 32 32>,\n+\t\t\t\t <&pinctrl 2 0 64 32>,\n+\t\t\t\t <&pinctrl 3 0 96 32>;\n+\t\t};\n+\n+\t\tpwm0: pwm@d401a000 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd401a000 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM0>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm1: pwm@d401a400 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd401a400 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM1>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2: pwm@d401a800 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd401a800 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM2>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM2>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm3: pwm@d401ac00 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd401ac00 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM3>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm4: pwm@d401b000 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd401b000 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM4>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm5: pwm@d401b400 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd401b400 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM5>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM5>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm6: pwm@d401b800 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd401b800 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM6>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM6>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm7: pwm@d401bc00 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd401bc00 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM7>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM7>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpinctrl: pinctrl@d401e000 {\n+\t\t\tcompatible = \"spacemit,k1-pinctrl\";\n+\t\t\treg = <0x0 0xd401e000 0x0 0x400>;\n+\t\t\tclocks = <&syscon_apbc CLK_AIB>,\n+\t\t\t\t <&syscon_apbc CLK_AIB_BUS>;\n+\t\t\tclock-names = \"func\", \"bus\";\n+\t\t};\n+\n+\t\tpwm8: pwm@d4020000 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4020000 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM8>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM8>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm9: pwm@d4020400 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4020400 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM9>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM9>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm10: pwm@d4020800 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4020800 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM10>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM10>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tuart2: serial@d4017100 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017100 0x0 0x100>;\n-\t\t\tinterrupts = <44>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tpwm11: pwm@d4020c00 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4020c00 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM11>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM11>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tuart3: serial@d4017200 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017200 0x0 0x100>;\n-\t\t\tinterrupts = <45>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tpwm12: pwm@d4021000 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4021000 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM12>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM12>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tuart4: serial@d4017300 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017300 0x0 0x100>;\n-\t\t\tinterrupts = <46>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tpwm13: pwm@d4021400 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4021400 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM13>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM13>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tuart5: serial@d4017400 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017400 0x0 0x100>;\n-\t\t\tinterrupts = <47>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tpwm14: pwm@d4021800 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4021800 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM14>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM14>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tuart6: serial@d4017500 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017500 0x0 0x100>;\n-\t\t\tinterrupts = <48>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tpwm15: pwm@d4021c00 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4021c00 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM15>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM15>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tuart7: serial@d4017600 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017600 0x0 0x100>;\n-\t\t\tinterrupts = <49>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tpwm16: pwm@d4022000 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4022000 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM16>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM16>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tuart8: serial@d4017700 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017700 0x0 0x100>;\n-\t\t\tinterrupts = <50>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tpwm17: pwm@d4022400 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4022400 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM17>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM17>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tuart9: serial@d4017800 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xd4017800 0x0 0x100>;\n-\t\t\tinterrupts = <51>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n+\t\tpwm18: pwm@d4022800 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4022800 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM18>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM18>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm19: pwm@d4022c00 {\n+\t\t\tcompatible = \"spacemit,k1-pwm\", \"marvell,pxa910-pwm\";\n+\t\t\treg = <0x0 0xd4022c00 0x0 0x10>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&syscon_apbc CLK_PWM19>;\n+\t\t\tresets = <&syscon_apbc RESET_PWM19>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsyscon_mpmu: system-controller@d4050000 {\n+\t\t\tcompatible = \"spacemit,k1-syscon-mpmu\";\n+\t\t\treg = <0x0 0xd4050000 0x0 0x209c>;\n+\t\t\tclocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,\n+\t\t\t\t <&vctcxo_24m>;\n+\t\t\tclock-names = \"osc\", \"vctcxo_1m\", \"vctcxo_3m\",\n+\t\t\t\t \"vctcxo_24m\";\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#power-domain-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\tpll: clock-controller@d4090000 {\n+\t\t\tcompatible = \"spacemit,k1-pll\";\n+\t\t\treg = <0x0 0xd4090000 0x0 0x1000>;\n+\t\t\tclocks = <&vctcxo_24m>;\n+\t\t\tspacemit,mpmu = <&syscon_mpmu>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsyscon_apmu: system-controller@d4282800 {\n+\t\t\tcompatible = \"spacemit,k1-syscon-apmu\";\n+\t\t\treg = <0x0 0xd4282800 0x0 0x400>;\n+\t\t\tclocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,\n+\t\t\t\t <&vctcxo_24m>;\n+\t\t\tclock-names = \"osc\", \"vctcxo_1m\", \"vctcxo_3m\",\n+\t\t\t\t \"vctcxo_24m\";\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#power-domain-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n \t\tplic: interrupt-controller@e0000000 {\n \t\t\tcompatible = \"spacemit,k1-plic\", \"sifive,plic-1.0.0\";\n \t\t\treg = <0x0 0xe0000000 0x0 0x4000000>;\n@@ -446,35 +638,201 @@\n \t\t\t\t\t <&cpu7_intc 3>, <&cpu7_intc 7>;\n \t\t};\n \n-\t\tsec_uart1: serial@f0612000 {\n-\t\t\tcompatible = \"spacemit,k1-uart\", \"intel,xscale-uart\";\n-\t\t\treg = <0x0 0xf0612000 0x0 0x100>;\n-\t\t\tinterrupts = <43>;\n-\t\t\tclock-frequency = <14857000>;\n-\t\t\treg-shift = <2>;\n-\t\t\treg-io-width = <4>;\n-\t\t\tstatus = \"reserved\"; /* for TEE usage */\n-\t\t};\n-\n-\t\treset: reset-controller@d4050000 {\n-\t\t\tcompatible = \"spacemit,k1-reset\";\n-\t\t\treg = <0x0 0xd4050000 0x0 0x209c>,\n-\t\t\t\t<0x0 0xd4282800 0x0 0x400>,\n-\t\t\t\t<0x0 0xd4015000 0x0 0x1000>,\n-\t\t\t\t<0x0 0xd4090000 0x0 0x1000>,\n-\t\t\t\t<0x0 0xd4282c00 0x0 0x400>,\n-\t\t\t\t<0x0 0xd8440000 0x0 0x98>,\n-\t\t\t\t<0x0 0xc0000000 0x0 0x4280>,\n-\t\t\t\t<0x0 0xf0610000 0x0 0x20>;\n-\t\t\treg-names = \"mpmu\", \"apmu\", \"apbc\", \"apbs\", \"ciu\", \"dciu\", \"ddrc\", \"apbc2\";\n+\t\tsyscon_apbc2: system-controller@f0610000 {\n+\t\t\tcompatible = \"spacemit,k1-syscon-apbc2\";\n+\t\t\treg = <0x0 0xf0610000 0x0 0x20>;\n \t\t\t#reset-cells = <1>;\n-\t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tpinctrl: pinctrl@d401e000 {\n-\t\t\tcompatible = \"spacemit,k1-pinctrl\", \"pinctrl-single\";\n-\t\t\treg = <0x0 0xd401e000 0x0 0x400>;\n-\t\t\tpinctrl-single,register-width = <32>;\n+\t\tcamera-bus {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\tranges;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,\n+\t\t\t\t <0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>;\n+\t\t};\n+\n+\t\tdma-bus {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\tranges;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,\n+\t\t\t\t <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>;\n+\n+\t\t\tuart0: serial@d4017000 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017000 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART0>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART0_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <42>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart2: serial@d4017100 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017100 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART2>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART2_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <44>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart3: serial@d4017200 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017200 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART3>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART3_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <45>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart4: serial@d4017300 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017300 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART4>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART4_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <46>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart5: serial@d4017400 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017400 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART5>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART5_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <47>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart6: serial@d4017500 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017500 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART6>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART6_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <48>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart7: serial@d4017600 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017600 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART7>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART7_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <49>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart8: serial@d4017700 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017700 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART8>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART8_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <50>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart9: serial@d4017800 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xd4017800 0x0 0x100>;\n+\t\t\t\tclocks = <&syscon_apbc CLK_UART9>,\n+\t\t\t\t\t <&syscon_apbc CLK_UART9_BUS>;\n+\t\t\t\tclock-names = \"core\", \"bus\";\n+\t\t\t\tinterrupts = <51>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tsec_uart1: serial@f0612000 {\n+\t\t\t\tcompatible = \"spacemit,k1-uart\",\n+\t\t\t\t\t \"intel,xscale-uart\";\n+\t\t\t\treg = <0x0 0xf0612000 0x0 0x100>;\n+\t\t\t\tinterrupts = <43>;\n+\t\t\t\tclock-frequency = <14857000>;\n+\t\t\t\treg-shift = <2>;\n+\t\t\t\treg-io-width = <4>;\n+\t\t\t\tstatus = \"reserved\"; /* for TEE usage */\n+\t\t\t};\n+\t\t};\n+\n+\t\tmultimedia-bus {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\tranges;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,\n+\t\t\t\t <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>;\n+\t\t};\n+\n+\t\tnetwork-bus {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\tranges;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,\n+\t\t\t\t <0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>;\n+\t\t};\n+\n+\t\tpcie-bus {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\tranges;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,\n+\t\t\t\t <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;\n+\t\t};\n+\n+\t\tstorage-bus {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\tranges;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;\n+\n+\t\t\temmc: mmc@d4281000 {\n+\t\t\t\tcompatible = \"spacemit,k1-sdhci\";\n+\t\t\t\treg = <0x0 0xd4281000 0x0 0x200>;\n+\t\t\t\tclocks = <&syscon_apmu CLK_SDH_AXI>,\n+\t\t\t\t\t <&syscon_apmu CLK_SDH2>;\n+\t\t\t\tclock-names = \"core\", \"io\";\n+\t\t\t\tinterrupts = <101>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n \t\t};\n \t};\n };\n", "prefixes": [ "v2", "06/16" ] }