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GET /api/patches/2195201/?format=api
{ "id": 2195201, "url": "http://patchwork.ozlabs.org/api/patches/2195201/?format=api", "web_url": "http://patchwork.ozlabs.org/project/buildroot/patch/20260210142845.1736028-1-thomas.richard@bootlin.com/", "project": { "id": 27, "url": "http://patchwork.ozlabs.org/api/projects/27/?format=api", "name": "Buildroot development", "link_name": "buildroot", "list_id": "buildroot.buildroot.org", "list_email": "buildroot@buildroot.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210142845.1736028-1-thomas.richard@bootlin.com>", "list_archive_url": null, "date": "2026-02-10T14:28:45", "name": "[1/1] board/stmicroelectronics/stm32mp135f-dk: fix silent crash in U-Boot", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "fff4bf648ad94dfd14a97e2a493b7bb622849e54", "submitter": { "id": 87375, "url": "http://patchwork.ozlabs.org/api/people/87375/?format=api", "name": "Thomas Richard", "email": "thomas.richard@bootlin.com" }, "delegate": { "id": 89618, "url": "http://patchwork.ozlabs.org/api/users/89618/?format=api", "username": "juju", "first_name": "Julien", "last_name": "Olivain", "email": "juju@cotds.org" }, "mbox": "http://patchwork.ozlabs.org/project/buildroot/patch/20260210142845.1736028-1-thomas.richard@bootlin.com/mbox/", "series": [ { "id": 491686, "url": "http://patchwork.ozlabs.org/api/series/491686/?format=api", "web_url": "http://patchwork.ozlabs.org/project/buildroot/list/?series=491686", "date": "2026-02-10T14:28:45", "name": "[1/1] board/stmicroelectronics/stm32mp135f-dk: fix silent crash in U-Boot", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491686/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195201/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195201/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<buildroot-bounces@buildroot.org>", "X-Original-To": [ "incoming-buildroot@patchwork.ozlabs.org", "buildroot@buildroot.org" ], "Delivered-To": [ "patchwork-incoming-buildroot@legolas.ozlabs.org", "buildroot@buildroot.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=buildroot.org header.i=@buildroot.org\n header.a=rsa-sha256 header.s=default header.b=o9w9/lTP;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=buildroot.org\n (client-ip=2605:bc80:3010::138; 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client-ip=185.171.202.116;\n helo=smtpout-04.galae.net; envelope-from=thomas.richard@bootlin.com;\n receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp4.osuosl.org 907BA40A77", "To": "buildroot@buildroot.org", "Cc": "Marleen Vos <marleen.vos@mind.be>,\n Thomas Richard <thomas.richard@bootlin.com>", "Date": "Tue, 10 Feb 2026 15:28:45 +0100", "Message-ID": "<20260210142845.1736028-1-thomas.richard@bootlin.com>", "X-Mailer": "git-send-email 2.51.0", "MIME-Version": "1.0", "X-Last-TLS-Session-Version": "TLSv1.3", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=bootlin.com; s=dkim;\n t=1770733754; h=from:subject:date:message-id:to:cc:mime-version:\n content-transfer-encoding; bh=CltvNgUqE+CT0IAvolmsKYRDAjcPdhxuW9KcWTjsBCw=;\n b=ubcMBy+iCCCIBTrAHFPpM/yVu5EleYQ52kaByNY8kyMU7OVATLcNtabGRGGcOfjny2EXUU\n brYIAVh7KdYzPj94uqNGqcBzWHBkRWfMvO2whKSaSJCUEnDObzP42MMOkfUe9931fozGoB\n r1TYzaZXL3HCioG6l0YyxaGhaj+XuGoe2a+aud8/SNapE2ERg5JrcZ/lf2HhDgK9hOdRJe\n 4lfiFQsCaI0rmufHgzvRjz/Bix2D6ZSHbJfbfasyy1QWQA/HeOTkHhfcGHnEKIxFUwtPAl\n 5EN6g7kAo4L9ctdxZJkZmpO5OCeS6zU3gZ3OPqp525QG0tfZXkDHBdMIudjVrg==", "X-Mailman-Original-Authentication-Results": [ "smtp4.osuosl.org;\n dmarc=pass (p=reject dis=none)\n header.from=bootlin.com", "smtp4.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=ubcMBy+i" ], "Subject": "[Buildroot] [PATCH 1/1] board/stmicroelectronics/stm32mp135f-dk:\n fix silent crash in U-Boot", "X-BeenThere": "buildroot@buildroot.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Discussion and development of buildroot <buildroot.buildroot.org>", "List-Unsubscribe": "<https://lists.buildroot.org/mailman/options/buildroot>,\n <mailto:buildroot-request@buildroot.org?subject=unsubscribe>", "List-Archive": "<http://lists.buildroot.org/pipermail/buildroot/>", "List-Post": "<mailto:buildroot@buildroot.org>", "List-Help": "<mailto:buildroot-request@buildroot.org?subject=help>", "List-Subscribe": "<https://lists.buildroot.org/mailman/listinfo/buildroot>,\n <mailto:buildroot-request@buildroot.org?subject=subscribe>", "From": "Thomas Richard via buildroot <buildroot@buildroot.org>", "Reply-To": "Thomas Richard <thomas.richard@bootlin.com>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "buildroot-bounces@buildroot.org", "Sender": "\"buildroot\" <buildroot-bounces@buildroot.org>" }, "content": "Backport upstream patches to fix a silent crash in U-Boot on\nSTM32MP135F-DK.\n\nSigned-off-by: Thomas Richard <thomas.richard@bootlin.com>\n---\n ...d-SCMI-clocks-in-rcc-node-for-stm32m.patch | 57 +\n ...te-clock-management-for-STM32MP13-25.patch | 1546 +++++++++++++++++\n 2 files changed, 1603 insertions(+)\n create mode 100644 board/stmicroelectronics/common/stm32mp1xx/patches/uboot/001-ARM-dts-stm32-Add-SCMI-clocks-in-rcc-node-for-stm32m.patch\n create mode 100644 board/stmicroelectronics/common/stm32mp1xx/patches/uboot/002-clk-stm32-Update-clock-management-for-STM32MP13-25.patch", "diff": "diff --git a/board/stmicroelectronics/common/stm32mp1xx/patches/uboot/001-ARM-dts-stm32-Add-SCMI-clocks-in-rcc-node-for-stm32m.patch b/board/stmicroelectronics/common/stm32mp1xx/patches/uboot/001-ARM-dts-stm32-Add-SCMI-clocks-in-rcc-node-for-stm32m.patch\nnew file mode 100644\nindex 0000000000..a1550476f1\n--- /dev/null\n+++ b/board/stmicroelectronics/common/stm32mp1xx/patches/uboot/001-ARM-dts-stm32-Add-SCMI-clocks-in-rcc-node-for-stm32m.patch\n@@ -0,0 +1,57 @@\n+From 7795c5ec6a608a104cf41331cbd387d39f7f6f49 Mon Sep 17 00:00:00 2001\n+From: Patrice Chotard <patrice.chotard@foss.st.com>\n+Date: Fri, 16 Jan 2026 19:57:26 +0100\n+Subject: [PATCH] ARM: dts: stm32: Add SCMI clocks in rcc node for\n+ stm32mp131.dtsi\n+\n+Add SCMI clocks. These clocks are used as parent clocks and are\n+referenced by their rcc's node position in clk-stm32mp13.c\n+\n+Fixes: fdb1bffe2827 (\"clk: scmi: Postpone clock name resolution\")\n+Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>\n+Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>\n+---\n+ arch/arm/dts/stm32mp13-u-boot.dtsi | 27 +++++++++++++++++++++++++++\n+ 1 file changed, 27 insertions(+)\n+\n+diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi\n+index ad63d5027b2..623c796cc79 100644\n+--- a/arch/arm/dts/stm32mp13-u-boot.dtsi\n++++ b/arch/arm/dts/stm32mp13-u-boot.dtsi\n+@@ -186,6 +186,33 @@\n+ };\n+ \n+ &rcc {\n++\tclocks = <&scmi_clk CK_SCMI_HSE>,\n++\t\t <&scmi_clk CK_SCMI_HSI>,\n++\t\t <&scmi_clk CK_SCMI_CSI>,\n++\t\t <&scmi_clk CK_SCMI_LSE>,\n++\t\t <&scmi_clk CK_SCMI_LSI>,\n++\t\t <&scmi_clk CK_SCMI_HSE_DIV2>,\n++\t\t <&scmi_clk CK_SCMI_PLL2_Q>,\n++\t\t <&scmi_clk CK_SCMI_PLL2_R>,\n++\t\t <&scmi_clk CK_SCMI_PLL3_P>,\n++\t\t <&scmi_clk CK_SCMI_PLL3_Q>,\n++\t\t <&scmi_clk CK_SCMI_PLL3_R>,\n++\t\t <&scmi_clk CK_SCMI_PLL4_P>,\n++\t\t <&scmi_clk CK_SCMI_PLL4_Q>,\n++\t\t <&scmi_clk CK_SCMI_PLL4_R>,\n++\t\t <&scmi_clk CK_SCMI_MPU>,\n++\t\t <&scmi_clk CK_SCMI_AXI>,\n++\t\t <&scmi_clk CK_SCMI_MLAHB>,\n++\t\t <&scmi_clk CK_SCMI_CKPER>,\n++\t\t <&scmi_clk CK_SCMI_PCLK1>,\n++\t\t <&scmi_clk CK_SCMI_PCLK2>,\n++\t\t <&scmi_clk CK_SCMI_PCLK3>,\n++\t\t <&scmi_clk CK_SCMI_PCLK4>,\n++\t\t <&scmi_clk CK_SCMI_PCLK5>,\n++\t\t <&scmi_clk CK_SCMI_PCLK6>,\n++\t\t <&scmi_clk CK_SCMI_CKTIMG1>,\n++\t\t <&scmi_clk CK_SCMI_CKTIMG2>,\n++\t\t <&scmi_clk CK_SCMI_CKTIMG3>;\n+ \tbootph-all;\n+ };\n+ \n+-- \n+2.51.0\n+\ndiff --git a/board/stmicroelectronics/common/stm32mp1xx/patches/uboot/002-clk-stm32-Update-clock-management-for-STM32MP13-25.patch b/board/stmicroelectronics/common/stm32mp1xx/patches/uboot/002-clk-stm32-Update-clock-management-for-STM32MP13-25.patch\nnew file mode 100644\nindex 0000000000..e9c2c7b1f5\n--- /dev/null\n+++ b/board/stmicroelectronics/common/stm32mp1xx/patches/uboot/002-clk-stm32-Update-clock-management-for-STM32MP13-25.patch\n@@ -0,0 +1,1546 @@\n+From 213f927a59288bbaa4b141c593424c3b205b5e6c Mon Sep 17 00:00:00 2001\n+From: Patrice Chotard <patrice.chotard@foss.st.com>\n+Date: Fri, 16 Jan 2026 19:57:27 +0100\n+Subject: [PATCH] clk: stm32: Update clock management for STM32MP13/25\n+\n+During clock's registration, clock's name are used to establish parent -\n+child relation. On STM32MP13 and STM32MP25, most of SCMI clocks are parent\n+clocks.\n+\n+Since commit fdb1bffe2827 (\"clk: scmi: Postpone clock name resolution\"),\n+all scmi clocks are named by default \"scmi-%zu\" until they are enabled,\n+it breaks clocks registration and boot process for STM32MP13/25\n+platforms.\n+\n+Rework the STM32 core clock driver and STM32MP13/25 clock description\n+to use clock index instead of their real name.\n+\n+Introduce struct clk_parent_data which allows to identify parent clock\n+either by index or by name. Name is only used for particular clocks\n+provided by IP which are clock provider as i2s/i2s_ckin, usb0/ck_usbo_48m,\n+and ltdc/ck_ker_ltdc.\n+\n+STM32_GATE() and STM32_COMPOSITE_NOMUX macros are updated in order to\n+use parent clock index.\n+\n+As STM32MP13 supports both SPL and SCMI boot, keep using an array\n+with clock's name for SPL.\n+\n+Fixes: fdb1bffe2827 (\"clk: scmi: Postpone clock name resolution\")\n+Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>\n+Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>\n+---\n+ drivers/clk/stm32/clk-stm32-core.c | 116 ++++++--\n+ drivers/clk/stm32/clk-stm32-core.h | 42 ++-\n+ drivers/clk/stm32/clk-stm32mp13.c | 417 ++++++++++++++++++++---------\n+ drivers/clk/stm32/clk-stm32mp25.c | 405 +++++++++++++++++-----------\n+ 4 files changed, 671 insertions(+), 309 deletions(-)\n+\n+diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c\n+index 858f122db1a..cd6bdee5412 100644\n+--- a/drivers/clk/stm32/clk-stm32-core.c\n++++ b/drivers/clk/stm32/clk-stm32-core.c\n+@@ -11,6 +11,8 @@\n+ #include <log.h>\n+ #include <asm/io.h>\n+ #include <dm/device_compat.h>\n++#include <dm/devres.h>\n++#include <dm/uclass-internal.h>\n+ #include <linux/clk-provider.h>\n+ #include \"clk-stm32-core.h\"\n+ \n+@@ -34,8 +36,8 @@ int stm32_rcc_init(struct udevice *dev,\n+ \t\treturn -ENOMEM;\n+ \n+ \tpriv->gate_cpt = cpt;\n+-\n+-\tpriv->data = clock_data;\n++\tpriv->clock_data = clock_data;\n++\tpriv->match_data = data;\n+ \n+ \tfor (i = 0; i < data->num_clocks; i++) {\n+ \t\tconst struct clock_config *cfg = &data->tab_clocks[i];\n+@@ -57,9 +59,58 @@ int stm32_rcc_init(struct udevice *dev,\n+ \treturn 0;\n+ }\n+ \n+-ulong clk_stm32_get_rate_by_name(const char *name)\n++static int clk_stm32_resolve_clk_name(struct udevice *dev, int idx, const char **name)\n+ {\n+-\tstruct udevice *dev;\n++#ifdef CONFIG_TFABOOT\n++\tstruct ofnode_phandle_args args;\n++\tstruct udevice *clk_udevice;\n++\tstruct udevice *child;\n++\tint ret;\n++\n++\tret = dev_read_phandle_with_args(dev, \"clocks\", \"#clock-cells\", 0, idx, &args);\n++\tif (ret) {\n++\t\tdev_err(dev, \"%s: dev_read_phandle_with_args failed: err=%d\\n\",\n++\t\t\t__func__, ret);\n++\t\treturn ret;\n++\t}\n++\n++\tret = uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &clk_udevice);\n++\tif (ret)\n++\t\treturn ret;\n++\n++\tif (args.args_count) {\n++\t\tdevice_foreach_child(child, clk_udevice) {\n++\t\t\tstruct clk *clkp;\n++\n++\t\t\tclkp = dev_get_clk_ptr(child);\n++\t\t\tif (clk_get_id(clkp) == args.args[0])\n++\t\t\t\tbreak;\n++\n++\t\t\tclk_udevice = child;\n++\t\t}\n++\t\t*name = child->name;\n++\t} else {\n++\t\t*name = clk_udevice->name;\n++\t}\n++#else\n++\tstruct stm32mp_rcc_priv *priv = dev_get_priv(dev);\n++\t*name = priv->match_data->get_clock_name(idx);\n++\n++\tif (!*name)\n++\t\treturn -ENOENT;\n++#endif\n++\n++\treturn 0;\n++}\n++\n++ulong clk_stm32_get_rate_by_index(struct udevice *dev, int index)\n++{\n++\tconst char *name;\n++\tint ret;\n++\n++\tret = clk_stm32_resolve_clk_name(dev, index, &name);\n++\tif (ret)\n++\t\treturn ret;\n+ \n+ \tif (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {\n+ \t\tstruct clk *clk = dev_get_clk_ptr(dev);\n+@@ -171,7 +222,7 @@ static int clk_stm32_gate_enable(struct clk *clk)\n+ \tstruct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk);\n+ \tstruct stm32mp_rcc_priv *priv = stm32_gate->priv;\n+ \n+-\tclk_stm32_gate_set_state(priv->base, priv->data, priv->gate_cpt,\n++\tclk_stm32_gate_set_state(priv->base, priv->clock_data, priv->gate_cpt,\n+ \t\t\t\t stm32_gate->gate_id, 1);\n+ \n+ \treturn 0;\n+@@ -182,7 +233,7 @@ static int clk_stm32_gate_disable(struct clk *clk)\n+ \tstruct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk);\n+ \tstruct stm32mp_rcc_priv *priv = stm32_gate->priv;\n+ \n+-\tclk_stm32_gate_set_state(priv->base, priv->data, priv->gate_cpt,\n++\tclk_stm32_gate_set_state(priv->base, priv->clock_data, priv->gate_cpt,\n+ \t\t\t\t stm32_gate->gate_id, 0);\n+ \n+ \treturn 0;\n+@@ -209,6 +260,7 @@ struct clk *clk_stm32_gate_register(struct udevice *dev,\n+ \tstruct stm32_clk_gate_cfg *clk_cfg = cfg->clock_cfg;\n+ \tstruct clk_stm32_gate *stm32_gate;\n+ \tstruct clk *clk;\n++\tconst char *parent_name;\n+ \tint ret;\n+ \n+ \tstm32_gate = kzalloc(sizeof(*stm32_gate), GFP_KERNEL);\n+@@ -221,8 +273,17 @@ struct clk *clk_stm32_gate_register(struct udevice *dev,\n+ \tclk = &stm32_gate->clk;\n+ \tclk->flags = cfg->flags;\n+ \n++\tif (cfg->parent_data->name) {\n++\t\tparent_name = cfg->parent_data->name;\n++\t} else {\n++\t\tret = clk_stm32_resolve_clk_name(dev, cfg->parent_data->index,\n++\t\t\t\t\t\t &parent_name);\n++\t\tif (ret)\n++\t\t\treturn ERR_PTR(ret);\n++\t}\n++\n+ \tret = clk_register(clk, UBOOT_DM_CLK_STM32_GATE,\n+-\t\t\t cfg->name, cfg->parent_name);\n++\t\t\t cfg->name, parent_name);\n+ \tif (ret) {\n+ \t\tkfree(stm32_gate);\n+ \t\treturn ERR_PTR(ret);\n+@@ -236,7 +297,7 @@ clk_stm32_register_composite(struct udevice *dev,\n+ \t\t\t const struct clock_config *cfg)\n+ {\n+ \tstruct stm32_clk_composite_cfg *composite = cfg->clock_cfg;\n+-\tconst char *const *parent_names;\n++\tconst char **parent_names = NULL;\n+ \tint num_parents;\n+ \tstruct clk *clk = ERR_PTR(-ENOMEM);\n+ \tstruct clk_mux *mux = NULL;\n+@@ -249,7 +310,8 @@ clk_stm32_register_composite(struct udevice *dev,\n+ \tstruct clk *div_clk = NULL;\n+ \tconst struct clk_ops *div_ops = NULL;\n+ \tstruct stm32mp_rcc_priv *priv = dev_get_priv(dev);\n+-\tconst struct clk_stm32_clock_data *data = priv->data;\n++\tconst struct clk_stm32_clock_data *data = priv->clock_data;\n++\tint i, ret;\n+ \n+ \tif (composite->mux_id != NO_STM32_MUX) {\n+ \t\tconst struct stm32_mux_cfg *mux_cfg;\n+@@ -260,27 +322,50 @@ clk_stm32_register_composite(struct udevice *dev,\n+ \n+ \t\tmux_cfg = &data->muxes[composite->mux_id];\n+ \n++\t\tparent_names = devm_kcalloc(dev, mux_cfg->num_parents,\n++\t\t\t\t\t sizeof(char *), GFP_KERNEL);\n++\t\tif (!parent_names)\n++\t\t\tgoto fail;\n++\n+ \t\tmux->reg = priv->base + mux_cfg->reg_off;\n+ \t\tmux->shift = mux_cfg->shift;\n+ \t\tmux->mask = BIT(mux_cfg->width) - 1;\n+ \t\tmux->num_parents = mux_cfg->num_parents;\n+ \t\tmux->flags = 0;\n+-\t\tmux->parent_names = mux_cfg->parent_names;\n+ \n++\t\tfor (i = 0; i < mux_cfg->num_parents; i++) {\n++\t\t\tif (mux_cfg->parent_data[i].name) {\n++\t\t\t\tparent_names[i] = mux_cfg->parent_data[i].name;\n++\t\t\t} else {\n++\t\t\t\tret = clk_stm32_resolve_clk_name(dev,\n++\t\t\t\t\t\t\t\t mux_cfg->parent_data[i].index,\n++\t\t\t\t\t\t\t\t &parent_names[i]);\n++\t\t\t\tif (ret)\n++\t\t\t\t\treturn ERR_CAST(clk);\n++\t\t\t}\n++\t\t}\n++\n++\t\tmux->parent_names = (const char * const*)parent_names;\n+ \t\tmux_clk = &mux->clk;\n+ \t\tmux_ops = &clk_mux_ops;\n+-\n+-\t\tparent_names = mux_cfg->parent_names;\n+ \t\tnum_parents = mux_cfg->num_parents;\n+ \t} else {\n+-\t\tparent_names = &cfg->parent_name;\n++\t\tparent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);\n++\t\tif (!parent_names)\n++\t\t\tgoto fail;\n++\n++\t\tret = clk_stm32_resolve_clk_name(dev, cfg->parent_data->index,\n++\t\t\t\t\t\t parent_names);\n++\t\tif (ret)\n++\t\t\treturn ERR_CAST(clk);\n++\n+ \t\tnum_parents = 1;\n+ \t}\n+ \n+ \tif (composite->div_id != NO_STM32_DIV) {\n+ \t\tconst struct stm32_div_cfg *div_cfg;\n+ \n+-\t\tdiv = kzalloc(sizeof(*div), GFP_KERNEL);\n++\t\tdiv = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);\n+ \t\tif (!div)\n+ \t\t\tgoto fail;\n+ \n+@@ -310,7 +395,7 @@ clk_stm32_register_composite(struct udevice *dev,\n+ \t}\n+ \n+ \tclk = clk_register_composite(dev, cfg->name,\n+-\t\t\t\t parent_names, num_parents,\n++\t\t\t\t (const char * const *)parent_names, num_parents,\n+ \t\t\t\t mux_clk, mux_ops,\n+ \t\t\t\t div_clk, div_ops,\n+ \t\t\t\t gate_clk, gate_ops,\n+@@ -321,6 +406,7 @@ clk_stm32_register_composite(struct udevice *dev,\n+ \treturn clk;\n+ \n+ fail:\n++\tkfree(parent_names);\n+ \tkfree(gate);\n+ \tkfree(div);\n+ \tkfree(mux);\n+diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h\n+index baf2a996ef3..3134e33aa6c 100644\n+--- a/drivers/clk/stm32/clk-stm32-core.h\n++++ b/drivers/clk/stm32/clk-stm32-core.h\n+@@ -6,10 +6,20 @@\n+ \n+ struct stm32_clock_match_data;\n+ \n++/**\n++ * struct clk_parent_data - clk parent information\n++ * @name: globally unique parent name\n++ * @index: parent index local to provider registering clk\n++ */\n++struct clk_parent_data {\n++\tconst char\t*name;\n++\tint\t\tindex;\n++};\n++\n+ /**\n+ * struct stm32_mux_cfg - multiplexer configuration\n+ *\n+- * @parent_names:\tarray of string names for all possible parents\n++ * @parent_data:\tarray of parent information for all possible parent\n+ * @num_parents:\tnumber of possible parents\n+ * @reg_off:\t\tregister controlling multiplexer\n+ * @shift:\t\tshift to multiplexer bit field\n+@@ -19,7 +29,7 @@ struct stm32_clock_match_data;\n+ *\t\t\tindex\n+ */\n+ struct stm32_mux_cfg {\n+-\tconst char * const *parent_names;\n++\tconst struct clk_parent_data *parent_data;\n+ \tu8 num_parents;\n+ \tu32 reg_off;\n+ \tu8 shift;\n+@@ -81,7 +91,7 @@ struct stm32_composite_cfg {\n+ *\n+ * @id:\t\t\tbinding id of the clock\n+ * @name:\t\tclock name\n+- * @parent_name:\tname of the clock parent\n++ * @parent_data:\tparent information\n+ * @flags:\t\tframework-specific flags\n+ * @sec_id:\t\tsecure id (use to known if the clock is secured or not)\n+ * @clock_cfg:\t\tspecific clock data configuration\n+@@ -91,7 +101,7 @@ struct stm32_composite_cfg {\n+ struct clock_config {\n+ \tunsigned long id;\n+ \tconst char *name;\n+-\tconst char *parent_name;\n++\tconst struct clk_parent_data *parent_data;\n+ \tunsigned long flags;\n+ \tint sec_id;\n+ \tvoid *clock_cfg;\n+@@ -129,6 +139,7 @@ struct stm32_clock_match_data {\n+ \tconst struct clk_stm32_clock_data *clock_data;\n+ \tint (*check_security)(struct udevice *dev, void __iomem *base,\n+ \t\t\t const struct clock_config *cfg);\n++\tconst char *(*get_clock_name)(u8 index);\n+ };\n+ \n+ /**\n+@@ -143,7 +154,8 @@ struct stm32_clock_match_data {\n+ struct stm32mp_rcc_priv {\n+ \tvoid __iomem *base;\n+ \tu8 *gate_cpt;\n+-\tconst struct clk_stm32_clock_data *data;\n++\tconst struct clk_stm32_clock_data *clock_data;\n++\tconst struct stm32_clock_match_data *match_data;\n+ \tstruct clk osc_clk[6];\n+ };\n+ \n+@@ -224,12 +236,14 @@ struct stm32_clk_gate_cfg {\n+ \n+ #define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \\\n+ { \\\n+-\t.id\t\t= _id, \\\n+-\t.sec_id\t\t= _sec_id, \\\n+-\t.name\t\t= _name, \\\n+-\t.parent_name\t= _parent, \\\n+-\t.flags\t\t= _flags, \\\n+-\t.clock_cfg\t= &(struct stm32_clk_gate_cfg) { \\\n++\t.id\t\t\t= _id, \\\n++\t.sec_id\t\t\t= _sec_id, \\\n++\t.name\t\t\t= _name, \\\n++\t.parent_data\t\t= &(struct clk_parent_data) { \\\n++\t\t.index\t\t= _parent, \\\n++\t}, \\\n++\t.flags\t\t\t= _flags, \\\n++\t.clock_cfg\t\t= &(struct stm32_clk_gate_cfg) { \\\n+ \t\t.gate_id\t= _gate_id, \\\n+ \t}, \\\n+ \t.setup\t\t= clk_stm32_gate_register, \\\n+@@ -261,7 +275,9 @@ struct stm32_clk_composite_cfg {\n+ { \\\n+ \t.id\t\t= _id, \\\n+ \t.name\t\t= _name, \\\n+-\t.parent_name\t= _parent, \\\n++\t.parent_data\t\t= &(struct clk_parent_data) { \\\n++\t\t.index\t\t= _parent, \\\n++\t}, \\\n+ \t.sec_id\t\t= _sec_id, \\\n+ \t.flags\t\t= _flags, \\\n+ \t.clock_cfg\t= &(struct stm32_clk_composite_cfg) { \\\n+@@ -274,4 +290,4 @@ struct stm32_clk_composite_cfg {\n+ \n+ extern const struct clk_ops stm32_clk_ops;\n+ \n+-ulong clk_stm32_get_rate_by_name(const char *name);\n++ulong clk_stm32_get_rate_by_index(struct udevice *dev, int index);\n+diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c\n+index 18e9ab364b4..39ec06a9556 100644\n+--- a/drivers/clk/stm32/clk-stm32mp13.c\n++++ b/drivers/clk/stm32/clk-stm32mp13.c\n+@@ -31,123 +31,248 @@\n+ \n+ DECLARE_GLOBAL_DATA_PTR;\n+ \n+-static const char * const adc12_src[] = {\n+-\t\"pll4_r\", \"ck_per\", \"pll3_q\"\n++ /* must match scmi clock order found in DT */\n++enum {\n++\tIDX_HSE,\n++\tIDX_HSI,\n++\tIDX_CSI,\n++\tIDX_LSE,\n++\tIDX_LSI,\n++\tIDX_HSE_DIV2,\n++\tIDX_PLL2_Q,\n++\tIDX_PLL2_R,\n++\tIDX_PLL3_P,\n++\tIDX_PLL3_Q,\n++\tIDX_PLL3_R,\n++\tIDX_PLL4_P,\n++\tIDX_PLL4_Q,\n++\tIDX_PLL4_R,\n++\tIDX_MPU,\n++\tIDX_AXI,\n++\tIDX_MLAHB,\n++\tIDX_CKPER,\n++\tIDX_PCLK1,\n++\tIDX_PCLK2,\n++\tIDX_PCLK3,\n++\tIDX_PCLK4,\n++\tIDX_PCLK5,\n++\tIDX_PCLK6,\n++\tIDX_CKTIMG1,\n++\tIDX_CKTIMG2,\n++\tIDX_CKTIMG3,\n++\tIDX_PARENT_NB,\n+ };\n+ \n+-static const char * const dcmipp_src[] = {\n+-\t\"ck_axi\", \"pll2_q\", \"pll4_p\", \"ck_per\",\n++static const struct clk_parent_data adc12_src[] = {\n++\t{ .index = IDX_PLL4_R },\n++\t{ .index = IDX_CKPER },\n++\t{ .index = IDX_PLL3_Q },\n+ };\n+ \n+-static const char * const eth12_src[] = {\n+-\t\"pll4_p\", \"pll3_q\"\n++static const struct clk_parent_data dcmipp_src[] = {\n++\t{ .index = IDX_AXI },\n++\t{ .index = IDX_PLL2_Q },\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_CKPER },\n+ };\n+ \n+-static const char * const fdcan_src[] = {\n+-\t\"ck_hse\", \"pll3_q\", \"pll4_q\", \"pll4_r\"\n++static const struct clk_parent_data eth12_src[] = {\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_PLL3_Q },\n+ };\n+ \n+-static const char * const fmc_src[] = {\n+-\t\"ck_axi\", \"pll3_r\", \"pll4_p\", \"ck_per\"\n++static const struct clk_parent_data fdcan_src[] = {\n++\t{ .index = IDX_HSE },\n++\t{ .index = IDX_PLL3_Q },\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_PLL4_R },\n+ };\n+ \n+-static const char * const i2c12_src[] = {\n+-\t\"pclk1\", \"pll4_r\", \"ck_hsi\", \"ck_csi\"\n++static const struct clk_parent_data fmc_src[] = {\n++\t{ .index = IDX_AXI },\n++\t{ .index = IDX_PLL3_R },\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_CKPER },\n+ };\n+ \n+-static const char * const i2c345_src[] = {\n+-\t\"pclk6\", \"pll4_r\", \"ck_hsi\", \"ck_csi\"\n++static const struct clk_parent_data i2c12_src[] = {\n++\t{ .index = IDX_PCLK1 },\n++\t{ .index = IDX_PLL4_R },\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_CSI },\n+ };\n+ \n+-static const char * const lptim1_src[] = {\n+-\t\"pclk1\", \"pll4_p\", \"pll3_q\", \"ck_lse\", \"ck_lsi\", \"ck_per\"\n++static const struct clk_parent_data i2c345_src[] = {\n++\t{ .index = IDX_PCLK6 },\n++\t{ .index = IDX_PLL4_R },\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_CSI },\n+ };\n+ \n+-static const char * const lptim23_src[] = {\n+-\t\"pclk3\", \"pll4_q\", \"ck_per\", \"ck_lse\", \"ck_lsi\"\n++static const struct clk_parent_data lptim1_src[] = {\n++\t{ .index = IDX_PCLK1 },\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_PLL3_Q },\n++\t{ .index = IDX_LSE },\n++\t{ .index = IDX_LSI },\n++\t{ .index = IDX_CKPER },\n+ };\n+ \n+-static const char * const lptim45_src[] = {\n+-\t\"pclk3\", \"pll4_p\", \"pll3_q\", \"ck_lse\", \"ck_lsi\", \"ck_per\"\n++static const struct clk_parent_data lptim23_src[] = {\n++\t{ .index = IDX_PCLK3 },\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_CKPER },\n++\t{ .index = IDX_LSE },\n++\t{ .index = IDX_LSI },\n+ };\n+ \n+-static const char * const mco1_src[] = {\n+-\t\"ck_hsi\", \"ck_hse\", \"ck_csi\", \"ck_lsi\", \"ck_lse\"\n++static const struct clk_parent_data lptim45_src[] = {\n++\t{ .index = IDX_PCLK3 },\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_PLL3_Q },\n++\t{ .index = IDX_LSE },\n++\t{ .index = IDX_LSI },\n++\t{ .index = IDX_CKPER },\n+ };\n+ \n+-static const char * const mco2_src[] = {\n+-\t\"ck_mpu\", \"ck_axi\", \"ck_mlahb\", \"pll4_p\", \"ck_hse\", \"ck_hsi\"\n++static const struct clk_parent_data mco1_src[] = {\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_HSE },\n++\t{ .index = IDX_CSI },\n++\t{ .index = IDX_LSI },\n++\t{ .index = IDX_LSE },\n+ };\n+ \n+-static const char * const qspi_src[] = {\n+-\t\"ck_axi\", \"pll3_r\", \"pll4_p\", \"ck_per\"\n++static const struct clk_parent_data mco2_src[] = {\n++\t{ .index = IDX_MPU },\n++\t{ .index = IDX_AXI },\n++\t{ .index = IDX_MLAHB },\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_HSE },\n++\t{ .index = IDX_HSI },\n+ };\n+ \n+-static const char * const rng1_src[] = {\n+-\t\"ck_csi\", \"pll4_r\", \"reserved\", \"ck_lsi\"\n++static const struct clk_parent_data qspi_src[] = {\n++\t{ .index = IDX_AXI },\n++\t{ .index = IDX_PLL3_R },\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_CKPER },\n+ };\n+ \n+-static const char * const saes_src[] = {\n+-\t\"ck_axi\", \"ck_per\", \"pll4_r\", \"ck_lsi\"\n++static const struct clk_parent_data rng1_src[] = {\n++\t{ .index = IDX_CSI },\n++\t{ .index = IDX_PLL4_R },\n++\t{ .name = \"reserved\" },\n++\t{ .index = IDX_LSI },\n+ };\n+ \n+-static const char * const sai1_src[] = {\n+-\t\"pll4_q\", \"pll3_q\", \"i2s_ckin\", \"ck_per\", \"pll3_r\"\n++static const struct clk_parent_data saes_src[] = {\n++\t{ .index = IDX_AXI },\n++\t{ .index = IDX_CKPER },\n++\t{ .index = IDX_PLL4_R },\n++\t{ .index = IDX_LSI },\n+ };\n+ \n+-static const char * const sai2_src[] = {\n+-\t\"pll4_q\", \"pll3_q\", \"i2s_ckin\", \"ck_per\", \"spdif_ck_symb\", \"pll3_r\"\n++static const struct clk_parent_data sai1_src[] = {\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_PLL3_Q },\n++\t{ .name = \"i2s_ckin\" },\n++\t{ .index = IDX_CKPER },\n++\t{ .index = IDX_PLL3_R },\n+ };\n+ \n+-static const char * const sdmmc12_src[] = {\n+-\t\"ck_axi\", \"pll3_r\", \"pll4_p\", \"ck_hsi\"\n++static const struct clk_parent_data sai2_src[] = {\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_PLL3_Q },\n++\t{ .name = \"i2s_ckin\" },\n++\t{ .index = IDX_CKPER },\n++\t{ .name = \"spdif_ck_symb\" },\n++\t{ .index = IDX_PLL3_R },\n+ };\n+ \n+-static const char * const spdif_src[] = {\n+-\t\"pll4_p\", \"pll3_q\", \"ck_hsi\"\n++static const struct clk_parent_data sdmmc12_src[] = {\n++\t{ .index = IDX_AXI },\n++\t{ .index = IDX_PLL3_R },\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_HSI },\n+ };\n+ \n+-static const char * const spi123_src[] = {\n+-\t\"pll4_p\", \"pll3_q\", \"i2s_ckin\", \"ck_per\", \"pll3_r\"\n++static const struct clk_parent_data spdif_src[] = {\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_PLL3_Q },\n++\t{ .index = IDX_HSI },\n+ };\n+ \n+-static const char * const spi4_src[] = {\n+-\t\"pclk6\", \"pll4_q\", \"ck_hsi\", \"ck_csi\", \"ck_hse\", \"i2s_ckin\"\n++static const struct clk_parent_data spi123_src[] = {\n++\t{ .index = IDX_PLL4_P },\n++\t{ .index = IDX_PLL3_Q },\n++\t{ .name = \"i2s_ckin\" },\n++\t{ .index = IDX_CKPER },\n++\t{ .index = IDX_PLL3_R },\n+ };\n+ \n+-static const char * const spi5_src[] = {\n+-\t\"pclk6\", \"pll4_q\", \"ck_hsi\", \"ck_csi\", \"ck_hse\"\n++static const struct clk_parent_data spi4_src[] = {\n++\t{ .index = IDX_PCLK6 },\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_CSI },\n++\t{ .index = IDX_HSE },\n++\t{ .name = \"i2s_ckin\" },\n+ };\n+ \n+-static const char * const stgen_src[] = {\n+-\t\"ck_hsi\", \"ck_hse\"\n++static const struct clk_parent_data spi5_src[] = {\n++\t{ .index = IDX_PCLK6 },\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_CSI },\n++\t{ .index = IDX_HSE },\n+ };\n+ \n+-static const char * const usart12_src[] = {\n+-\t\"pclk6\", \"pll3_q\", \"ck_hsi\", \"ck_csi\", \"pll4_q\", \"ck_hse\"\n++static const struct clk_parent_data stgen_src[] = {\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_HSE },\n+ };\n+ \n+-static const char * const usart34578_src[] = {\n+-\t\"pclk1\", \"pll4_q\", \"ck_hsi\", \"ck_csi\", \"ck_hse\"\n++static const struct clk_parent_data usart12_src[] = {\n++\t{ .index = IDX_PCLK6 },\n++\t{ .index = IDX_PLL3_Q },\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_CSI },\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_HSE },\n+ };\n+ \n+-static const char * const usart6_src[] = {\n+-\t\"pclk2\", \"pll4_q\", \"ck_hsi\", \"ck_csi\", \"ck_hse\"\n++static const struct clk_parent_data usart34578_src[] = {\n++\t{ .index = IDX_PCLK1 },\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_CSI },\n++\t{ .index = IDX_HSE },\n+ };\n+ \n+-static const char * const usbo_src[] = {\n+-\t\"pll4_r\", \"ck_usbo_48m\"\n++static const struct clk_parent_data usart6_src[] = {\n++\t{ .index = IDX_PCLK2 },\n++\t{ .index = IDX_PLL4_Q },\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_CSI },\n++\t{ .index = IDX_HSE },\n+ };\n+ \n+-static const char * const usbphy_src[] = {\n+-\t\"ck_hse\", \"pll4_r\", \"clk-hse-div2\"\n++static const struct clk_parent_data usbo_src[] = {\n++\t{ .index = IDX_PLL4_R },\n++\t{ .name = \"ck_usbo_48m\" },\n+ };\n+ \n++static const struct clk_parent_data usbphy_src[] = {\n++\t{ .index = IDX_HSE },\n++\t{ .index = IDX_PLL4_R },\n++\t{ .index = IDX_HSE_DIV2 },\n++};\n+ \n+ #define MUX_CFG(id, src, _offset, _shift, _witdh) \\\n+ \t[id] = { \\\n+ \t\t.num_parents\t= ARRAY_SIZE(src), \\\n+-\t\t.parent_names\t= (src), \\\n++\t\t.parent_data\t= (src), \\\n+ \t\t.reg_off\t= (_offset), \\\n+ \t\t.shift\t\t= (_shift), \\\n+ \t\t.width\t\t= (_witdh), \\\n+@@ -602,73 +727,73 @@ static const struct clk_stm32_security stm32mp13_security[] = {\n+ \n+ static const struct clock_config stm32mp13_clock_cfg[] = {\n+ #ifndef CONFIG_XPL_BUILD\n+-\tTIMER(TIM2_K, \"tim2_k\", \"timg1_ck\", 0, GATE_TIM2, SECF_NONE),\n+-\tTIMER(TIM3_K, \"tim3_k\", \"timg1_ck\", 0, GATE_TIM3, SECF_NONE),\n+-\tTIMER(TIM4_K, \"tim4_k\", \"timg1_ck\", 0, GATE_TIM4, SECF_NONE),\n+-\tTIMER(TIM5_K, \"tim5_k\", \"timg1_ck\", 0, GATE_TIM5, SECF_NONE),\n+-\tTIMER(TIM6_K, \"tim6_k\", \"timg1_ck\", 0, GATE_TIM6, SECF_NONE),\n+-\tTIMER(TIM7_K, \"tim7_k\", \"timg1_ck\", 0, GATE_TIM7, SECF_NONE),\n+-\tTIMER(TIM1_K, \"tim1_k\", \"timg2_ck\", 0, GATE_TIM1, SECF_NONE),\n+-\tTIMER(TIM8_K, \"tim8_k\", \"timg2_ck\", 0, GATE_TIM8, SECF_NONE),\n+-\tTIMER(TIM12_K, \"tim12_k\", \"timg3_ck\", 0, GATE_TIM12, SECF_TIM12),\n+-\tTIMER(TIM13_K, \"tim13_k\", \"timg3_ck\", 0, GATE_TIM13, SECF_TIM13),\n+-\tTIMER(TIM14_K, \"tim14_k\", \"timg3_ck\", 0, GATE_TIM14, SECF_TIM14),\n+-\tTIMER(TIM15_K, \"tim15_k\", \"timg3_ck\", 0, GATE_TIM15, SECF_TIM15),\n+-\tTIMER(TIM16_K, \"tim16_k\", \"timg3_ck\", 0, GATE_TIM16, SECF_TIM16),\n+-\tTIMER(TIM17_K, \"tim17_k\", \"timg3_ck\", 0, GATE_TIM17, SECF_TIM17),\n++\tTIMER(TIM2_K, \"tim2_k\", IDX_CKTIMG1, 0, GATE_TIM2, SECF_NONE),\n++\tTIMER(TIM3_K, \"tim3_k\", IDX_CKTIMG1, 0, GATE_TIM3, SECF_NONE),\n++\tTIMER(TIM4_K, \"tim4_k\", IDX_CKTIMG1, 0, GATE_TIM4, SECF_NONE),\n++\tTIMER(TIM5_K, \"tim5_k\", IDX_CKTIMG1, 0, GATE_TIM5, SECF_NONE),\n++\tTIMER(TIM6_K, \"tim6_k\", IDX_CKTIMG1, 0, GATE_TIM6, SECF_NONE),\n++\tTIMER(TIM7_K, \"tim7_k\", IDX_CKTIMG1, 0, GATE_TIM7, SECF_NONE),\n++\tTIMER(TIM1_K, \"tim1_k\", IDX_CKTIMG2, 0, GATE_TIM1, SECF_NONE),\n++\tTIMER(TIM8_K, \"tim8_k\", IDX_CKTIMG2, 0, GATE_TIM8, SECF_NONE),\n++\tTIMER(TIM12_K, \"tim12_k\", IDX_CKTIMG3, 0, GATE_TIM12, SECF_TIM12),\n++\tTIMER(TIM13_K, \"tim13_k\", IDX_CKTIMG3, 0, GATE_TIM13, SECF_TIM13),\n++\tTIMER(TIM14_K, \"tim14_k\", IDX_CKTIMG3, 0, GATE_TIM14, SECF_TIM14),\n++\tTIMER(TIM15_K, \"tim15_k\", IDX_CKTIMG3, 0, GATE_TIM15, SECF_TIM15),\n++\tTIMER(TIM16_K, \"tim16_k\", IDX_CKTIMG3, 0, GATE_TIM16, SECF_TIM16),\n++\tTIMER(TIM17_K, \"tim17_k\", IDX_CKTIMG3, 0, GATE_TIM17, SECF_TIM17),\n+ #endif\n+ \n+ \t/* Peripheral clocks */\n+-\tPCLK(SYSCFG, \"syscfg\", \"pclk3\", 0, GATE_SYSCFG, SECF_NONE),\n+-\tPCLK(VREF, \"vref\", \"pclk3\", 0, GATE_VREF, SECF_VREF),\n++\tPCLK(SYSCFG, \"syscfg\", IDX_PCLK3, 0, GATE_SYSCFG, SECF_NONE),\n++\tPCLK(VREF, \"vref\", IDX_PCLK3, 0, GATE_VREF, SECF_VREF),\n+ #ifndef CONFIG_XPL_BUILD\n+-\tPCLK(PMBCTRL, \"pmbctrl\", \"pclk3\", 0, GATE_PMBCTRL, SECF_NONE),\n+-\tPCLK(HDP, \"hdp\", \"pclk3\", 0, GATE_HDP, SECF_NONE),\n++\tPCLK(PMBCTRL, \"pmbctrl\", IDX_PCLK3, 0, GATE_PMBCTRL, SECF_NONE),\n++\tPCLK(HDP, \"hdp\", IDX_PCLK3, 0, GATE_HDP, SECF_NONE),\n+ #endif\n+-\tPCLK(IWDG2, \"iwdg2\", \"pclk4\", 0, GATE_IWDG2APB, SECF_NONE),\n+-\tPCLK(STGENRO, \"stgenro\", \"pclk4\", 0, GATE_STGENRO, SECF_STGENRO),\n+-\tPCLK(TZPC, \"tzpc\", \"pclk5\", 0, GATE_TZC, SECF_TZC),\n+-\tPCLK(IWDG1, \"iwdg1\", \"pclk5\", 0, GATE_IWDG1APB, SECF_IWDG1),\n+-\tPCLK(BSEC, \"bsec\", \"pclk5\", 0, GATE_BSEC, SECF_BSEC),\n++\tPCLK(IWDG2, \"iwdg2\", IDX_PCLK4, 0, GATE_IWDG2APB, SECF_NONE),\n++\tPCLK(STGENRO, \"stgenro\", IDX_PCLK4, 0, GATE_STGENRO, SECF_STGENRO),\n++\tPCLK(TZPC, \"tzpc\", IDX_PCLK5, 0, GATE_TZC, SECF_TZC),\n++\tPCLK(IWDG1, \"iwdg1\", IDX_PCLK5, 0, GATE_IWDG1APB, SECF_IWDG1),\n++\tPCLK(BSEC, \"bsec\", IDX_PCLK5, 0, GATE_BSEC, SECF_BSEC),\n+ #ifndef CONFIG_XPL_BUILD\n+-\tPCLK(DMA1, \"dma1\", \"ck_mlahb\", 0, GATE_DMA1, SECF_NONE),\n+-\tPCLK(DMA2, \"dma2\", \"ck_mlahb\", 0, GATE_DMA2, SECF_NONE),\n+-\tPCLK(DMAMUX1, \"dmamux1\", \"ck_mlahb\", 0, GATE_DMAMUX1, SECF_NONE),\n+-\tPCLK(DMAMUX2, \"dmamux2\", \"ck_mlahb\", 0, GATE_DMAMUX2, SECF_DMAMUX2),\n+-\tPCLK(ADC1, \"adc1\", \"ck_mlahb\", 0, GATE_ADC1, SECF_ADC1),\n+-\tPCLK(ADC2, \"adc2\", \"ck_mlahb\", 0, GATE_ADC2, SECF_ADC2),\n++\tPCLK(DMA1, \"dma1\", IDX_MLAHB, 0, GATE_DMA1, SECF_NONE),\n++\tPCLK(DMA2, \"dma2\", IDX_MLAHB, 0, GATE_DMA2, SECF_NONE),\n++\tPCLK(DMAMUX1, \"dmamux1\", IDX_MLAHB, 0, GATE_DMAMUX1, SECF_NONE),\n++\tPCLK(DMAMUX2, \"dmamux2\", IDX_MLAHB, 0, GATE_DMAMUX2, SECF_DMAMUX2),\n++\tPCLK(ADC1, \"adc1\", IDX_MLAHB, 0, GATE_ADC1, SECF_ADC1),\n++\tPCLK(ADC2, \"adc2\", IDX_MLAHB, 0, GATE_ADC2, SECF_ADC2),\n+ #endif\n+-\tPCLK(GPIOA, \"gpioa\", \"pclk4\", 0, GATE_GPIOA, SECF_NONE),\n+-\tPCLK(GPIOB, \"gpiob\", \"pclk4\", 0, GATE_GPIOB, SECF_NONE),\n+-\tPCLK(GPIOC, \"gpioc\", \"pclk4\", 0, GATE_GPIOC, SECF_NONE),\n+-\tPCLK(GPIOD, \"gpiod\", \"pclk4\", 0, GATE_GPIOD, SECF_NONE),\n+-\tPCLK(GPIOE, \"gpioe\", \"pclk4\", 0, GATE_GPIOE, SECF_NONE),\n+-\tPCLK(GPIOF, \"gpiof\", \"pclk4\", 0, GATE_GPIOF, SECF_NONE),\n+-\tPCLK(GPIOG, \"gpiog\", \"pclk4\", 0, GATE_GPIOG, SECF_NONE),\n+-\tPCLK(GPIOH, \"gpioh\", \"pclk4\", 0, GATE_GPIOH, SECF_NONE),\n+-\tPCLK(GPIOI, \"gpioi\", \"pclk4\", 0, GATE_GPIOI, SECF_NONE),\n+-\tPCLK(TSC, \"tsc\", \"pclk4\", 0, GATE_TSC, SECF_TZC),\n+-\tPCLK(PKA, \"pka\", \"ck_axi\", 0, GATE_PKA, SECF_PKA),\n+-\tPCLK(CRYP1, \"cryp1\", \"ck_axi\", 0, GATE_CRYP1, SECF_CRYP1),\n+-\tPCLK(HASH1, \"hash1\", \"ck_axi\", 0, GATE_HASH1, SECF_HASH1),\n+-\tPCLK(BKPSRAM, \"bkpsram\", \"ck_axi\", 0, GATE_BKPSRAM, SECF_BKPSRAM),\n+-\tPCLK(MDMA, \"mdma\", \"ck_axi\", 0, GATE_MDMA, SECF_NONE),\n++\tPCLK(GPIOA, \"gpioa\", IDX_PCLK4, 0, GATE_GPIOA, SECF_NONE),\n++\tPCLK(GPIOB, \"gpiob\", IDX_PCLK4, 0, GATE_GPIOB, SECF_NONE),\n++\tPCLK(GPIOC, \"gpioc\", IDX_PCLK4, 0, GATE_GPIOC, SECF_NONE),\n++\tPCLK(GPIOD, \"gpiod\", IDX_PCLK4, 0, GATE_GPIOD, SECF_NONE),\n++\tPCLK(GPIOE, \"gpioe\", IDX_PCLK4, 0, GATE_GPIOE, SECF_NONE),\n++\tPCLK(GPIOF, \"gpiof\", IDX_PCLK4, 0, GATE_GPIOF, SECF_NONE),\n++\tPCLK(GPIOG, \"gpiog\", IDX_PCLK4, 0, GATE_GPIOG, SECF_NONE),\n++\tPCLK(GPIOH, \"gpioh\", IDX_PCLK4, 0, GATE_GPIOH, SECF_NONE),\n++\tPCLK(GPIOI, \"gpioi\", IDX_PCLK4, 0, GATE_GPIOI, SECF_NONE),\n++\tPCLK(TSC, \"tsc\", IDX_PCLK4, 0, GATE_TSC, SECF_TZC),\n++\tPCLK(PKA, \"pka\", IDX_AXI, 0, GATE_PKA, SECF_PKA),\n++\tPCLK(CRYP1, \"cryp1\", IDX_AXI, 0, GATE_CRYP1, SECF_CRYP1),\n++\tPCLK(HASH1, \"hash1\", IDX_AXI, 0, GATE_HASH1, SECF_HASH1),\n++\tPCLK(BKPSRAM, \"bkpsram\", IDX_AXI, 0, GATE_BKPSRAM, SECF_BKPSRAM),\n++\tPCLK(MDMA, \"mdma\", IDX_AXI, 0, GATE_MDMA, SECF_NONE),\n+ #ifndef CONFIG_XPL_BUILD\n+-\tPCLK(ETH1TX, \"eth1tx\", \"ck_axi\", 0, GATE_ETH1TX, SECF_ETH1TX),\n+-\tPCLK(ETH1RX, \"eth1rx\", \"ck_axi\", 0, GATE_ETH1RX, SECF_ETH1RX),\n+-\tPCLK(ETH1MAC, \"eth1mac\", \"ck_axi\", 0, GATE_ETH1MAC, SECF_ETH1MAC),\n+-\tPCLK(ETH2TX, \"eth2tx\", \"ck_axi\", 0, GATE_ETH2TX, SECF_ETH2TX),\n+-\tPCLK(ETH2RX, \"eth2rx\", \"ck_axi\", 0, GATE_ETH2RX, SECF_ETH2RX),\n+-\tPCLK(ETH2MAC, \"eth2mac\", \"ck_axi\", 0, GATE_ETH2MAC, SECF_ETH2MAC),\n++\tPCLK(ETH1TX, \"eth1tx\", IDX_AXI, 0, GATE_ETH1TX, SECF_ETH1TX),\n++\tPCLK(ETH1RX, \"eth1rx\", IDX_AXI, 0, GATE_ETH1RX, SECF_ETH1RX),\n++\tPCLK(ETH1MAC, \"eth1mac\", IDX_AXI, 0, GATE_ETH1MAC, SECF_ETH1MAC),\n++\tPCLK(ETH2TX, \"eth2tx\", IDX_AXI, 0, GATE_ETH2TX, SECF_ETH2TX),\n++\tPCLK(ETH2RX, \"eth2rx\", IDX_AXI, 0, GATE_ETH2RX, SECF_ETH2RX),\n++\tPCLK(ETH2MAC, \"eth2mac\", IDX_AXI, 0, GATE_ETH2MAC, SECF_ETH2MAC),\n+ #endif\n+-\tPCLK(CRC1, \"crc1\", \"ck_axi\", 0, GATE_CRC1, SECF_NONE),\n++\tPCLK(CRC1, \"crc1\", IDX_AXI, 0, GATE_CRC1, SECF_NONE),\n+ #ifndef CONFIG_XPL_BUILD\n+-\tPCLK(USBH, \"usbh\", \"ck_axi\", 0, GATE_USBH, SECF_NONE),\n++\tPCLK(USBH, \"usbh\", IDX_AXI, 0, GATE_USBH, SECF_NONE),\n+ #endif\n+-\tPCLK(DDRPERFM, \"ddrperfm\", \"pclk4\", 0, GATE_DDRPERFM, SECF_NONE),\n++\tPCLK(DDRPERFM, \"ddrperfm\", IDX_PCLK4, 0, GATE_DDRPERFM, SECF_NONE),\n+ #ifndef CONFIG_XPL_BUILD\n+-\tPCLK(ETH1STP, \"eth1stp\", \"ck_axi\", 0, GATE_ETH1STP, SECF_ETH1STP),\n+-\tPCLK(ETH2STP, \"eth2stp\", \"ck_axi\", 0, GATE_ETH2STP, SECF_ETH2STP),\n++\tPCLK(ETH1STP, \"eth1stp\", IDX_AXI, 0, GATE_ETH1STP, SECF_ETH1STP),\n++\tPCLK(ETH2STP, \"eth2stp\", IDX_AXI, 0, GATE_ETH2STP, SECF_ETH2STP),\n+ #endif\n+ \n+ \t/* Kernel clocks */\n+@@ -728,11 +853,11 @@ static const struct clock_config stm32mp13_clock_cfg[] = {\n+ \tKCLK(ETH2CK_K, \"eth2ck_k\", 0, GATE_ETH2CK, MUX_ETH2, SECF_ETH2CK),\n+ \tKCLK(SAES_K, \"saes_k\", 0, GATE_SAES, MUX_SAES, SECF_SAES),\n+ \n+-\tSTM32_GATE(DFSDM_K, \"dfsdm_k\", \"ck_mlahb\", 0, GATE_DFSDM, SECF_NONE),\n+-\tSTM32_GATE(LTDC_PX, \"ltdc_px\", \"pll4_q\", CLK_SET_RATE_PARENT,\n++\tSTM32_GATE(DFSDM_K, \"dfsdm_k\", IDX_MLAHB, 0, GATE_DFSDM, SECF_NONE),\n++\tSTM32_GATE(LTDC_PX, \"ltdc_px\", IDX_PLL4_Q, CLK_SET_RATE_PARENT,\n+ \t\t GATE_LTDC, SECF_NONE),\n+ \n+-\tSTM32_GATE(DTS_K, \"dts_k\", \"ck_lse\", 0, GATE_DTS, SECF_NONE),\n++\tSTM32_GATE(DTS_K, \"dts_k\", IDX_LSE, 0, GATE_DTS, SECF_NONE),\n+ #endif\n+ \n+ \tSTM32_COMPOSITE(ETH1PTP_K, \"eth1ptp_k\", CLK_OPS_PARENT_ENABLE |\n+@@ -753,23 +878,23 @@ static const struct clock_config stm32mp13_clock_cfg[] = {\n+ \t\t\tGATE_MCO2, MUX_MCO2, DIV_MCO2),\n+ \n+ \t/* Debug clocks */\n+-\tSTM32_GATE(CK_DBG, \"ck_sys_dbg\", \"ck_axi\", CLK_IGNORE_UNUSED,\n++\tSTM32_GATE(CK_DBG, \"ck_sys_dbg\", IDX_AXI, CLK_IGNORE_UNUSED,\n+ \t\t GATE_DBGCK, SECF_NONE),\n+ \n+-\tSTM32_COMPOSITE_NOMUX(CK_TRACE, \"ck_trace\", \"ck_axi\",\n++\tSTM32_COMPOSITE_NOMUX(CK_TRACE, \"ck_trace\", IDX_AXI,\n+ \t\t\t CLK_OPS_PARENT_ENABLE, SECF_NONE,\n+ \t\t\t GATE_TRACECK, DIV_TRACE),\n+ \n+ #ifdef CONFIG_XPL_BUILD\n+-\tSTM32_GATE(AXIDCG, \"axidcg\", \"ck_axi\", CLK_IGNORE_UNUSED,\n++\tSTM32_GATE(AXIDCG, \"axidcg\", IDX_AXI, CLK_IGNORE_UNUSED,\n+ \t\t GATE_AXIDCG, SECF_NONE),\n+-\tSTM32_GATE(DDRC1, \"ddrc1\", \"ck_axi\", CLK_IGNORE_UNUSED,\n++\tSTM32_GATE(DDRC1, \"ddrc1\", IDX_AXI, CLK_IGNORE_UNUSED,\n+ \t\t GATE_DDRC1, SECF_NONE),\n+-\tSTM32_GATE(DDRPHYC, \"ddrphyc\", \"pll2_r\", CLK_IGNORE_UNUSED,\n++\tSTM32_GATE(DDRPHYC, \"ddrphyc\", IDX_PLL2_R, CLK_IGNORE_UNUSED,\n+ \t\t GATE_DDRPHYC, SECF_NONE),\n+-\tSTM32_GATE(DDRCAPB, \"ddrcapb\", \"pclk4\", CLK_IGNORE_UNUSED,\n++\tSTM32_GATE(DDRCAPB, \"ddrcapb\", IDX_PCLK4, CLK_IGNORE_UNUSED,\n+ \t\t GATE_DDRCAPB, SECF_NONE),\n+-\tSTM32_GATE(DDRPHYCAPB, \"ddrphycapb\", \"pclk4\", CLK_IGNORE_UNUSED,\n++\tSTM32_GATE(DDRPHYCAPB, \"ddrphycapb\", IDX_PCLK4, CLK_IGNORE_UNUSED,\n+ \t\t GATE_DDRPHYCAPB, SECF_NONE),\n+ #endif\n+ };\n+@@ -790,6 +915,44 @@ static int stm32mp13_check_security(struct udevice *dev, void __iomem *base,\n+ \n+ \treturn secured;\n+ }\n++#else\n++static char * const stm32mp13_clk_parent_name[IDX_PARENT_NB] = {\n++\t[IDX_HSE] = \"ck_hse\",\n++\t[IDX_HSI] = \"ck_hsi\",\n++\t[IDX_CSI] = \"ck_csi\",\n++\t[IDX_LSE] = \"ck_lse\",\n++\t[IDX_LSI] = \"ck_lsi\",\n++\t[IDX_HSE_DIV2] = \"clk-hse-div2\",\n++\t[IDX_PLL2_Q] = \"pll2_q\",\n++\t[IDX_PLL2_R] = \"pll2_r\",\n++\t[IDX_PLL3_P] = \"pll3_p\",\n++\t[IDX_PLL3_Q] = \"pll3_q\",\n++\t[IDX_PLL3_R] = \"pll3_r\",\n++\t[IDX_PLL4_P] = \"pll4_p\",\n++\t[IDX_PLL4_Q] = \"pll4_q\",\n++\t[IDX_PLL4_R] = \"pll4_r\",\n++\t[IDX_MPU] = \"ck_mpu\",\n++\t[IDX_AXI] = \"ck_axi\",\n++\t[IDX_MLAHB] = \"ck_mlahb\",\n++\t[IDX_CKPER] = \"ck_per\",\n++\t[IDX_PCLK1] = \"pclk1\",\n++\t[IDX_PCLK2] = \"pclk2\",\n++\t[IDX_PCLK3] = \"pclk3\",\n++\t[IDX_PCLK4] = \"pclk4\",\n++\t[IDX_PCLK5] = \"pclk5\",\n++\t[IDX_PCLK6] = \"pclk6\",\n++\t[IDX_CKTIMG1] = \"tim1_k\",\n++\t[IDX_CKTIMG2] = \"tim2_k\",\n++\t[IDX_CKTIMG3] = \"tim3_k\",\n++};\n++\n++static const char *stm32mp13_get_clock_name(u8 index)\n++{\n++\tif (index >= IDX_PARENT_NB)\n++\t\treturn NULL;\n++\n++\treturn stm32mp13_clk_parent_name[index];\n++}\n+ #endif\n+ \n+ static const struct stm32_clock_match_data stm32mp13_data = {\n+@@ -803,6 +966,8 @@ static const struct stm32_clock_match_data stm32mp13_data = {\n+ \t},\n+ #ifdef CONFIG_TFABOOT\n+ \t.check_security = stm32mp13_check_security,\n++#else\n++\t.get_clock_name = stm32mp13_get_clock_name,\n+ #endif\n+ };\n+ \n+@@ -2004,11 +2169,11 @@ static int stm32mp1_clk_probe(struct udevice *dev)\n+ \tif (err)\n+ \t\treturn err;\n+ \n+-\tgd->cpu_clk = clk_stm32_get_rate_by_name(\"ck_mpu\");\n+-\tgd->bus_clk = clk_stm32_get_rate_by_name(\"ck_axi\");\n++\tgd->cpu_clk = clk_stm32_get_rate_by_index(dev, IDX_MPU);\n++\tgd->bus_clk = clk_stm32_get_rate_by_index(dev, IDX_AXI);\n+ \n+ \t/* DDRPHYC father */\n+-\tgd->mem_clk = clk_stm32_get_rate_by_name(\"pll2_r\");\n++\tgd->mem_clk = clk_stm32_get_rate_by_index(dev, IDX_PLL2_R);\n+ \n+ #ifndef CONFIG_XPL_BUILD\n+ \tif (IS_ENABLED(CONFIG_DISPLAY_CPUINFO)) {\n+@@ -2019,7 +2184,7 @@ static int stm32mp1_clk_probe(struct udevice *dev)\n+ \t\t\tlog_info(\"- MPU : %s MHz\\n\", strmhz(buf, gd->cpu_clk));\n+ \t\t\tlog_info(\"- AXI : %s MHz\\n\", strmhz(buf, gd->bus_clk));\n+ \t\t\tlog_info(\"- PER : %s MHz\\n\",\n+-\t\t\t\t strmhz(buf, clk_stm32_get_rate_by_name(\"ck_per\")));\n++\t\t\t\t strmhz(buf, clk_stm32_get_rate_by_index(dev, IDX_CKPER)));\n+ \t\t\tlog_info(\"- DDR : %s MHz\\n\", strmhz(buf, gd->mem_clk));\n+ \t\t}\n+ \t}\n+diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c\n+index b487f33b6c7..93ee38ed59e 100644\n+--- a/drivers/clk/stm32/clk-stm32mp25.c\n++++ b/drivers/clk/stm32/clk-stm32mp25.c\n+@@ -43,48 +43,143 @@\n+ #define SEC_RIFRCC(_id)\t\t(STM32MP25_RIFRCC_##_id##_ID)\n+ #define SEC_RIFSC(_id)\t\t((_id) | SEC_RIFSC_FLAG)\n+ \n+-static const char * const adc12_src[] = {\n+-\t\"ck_flexgen_46\", \"ck_icn_ls_mcu\"\n++/* must match scmi clock order found in DT */\n++enum {\n++\tIDX_HSE,\n++\tIDX_HSI,\n++\tIDX_MSI,\n++\tIDX_LSE,\n++\tIDX_LSI,\n++\tIDX_HSE_DIV2,\n++\tIDX_ICN_HS_MCU,\n++\tIDX_ICN_LS_MCU,\n++\tIDX_ICN_SDMMC,\n++\tIDX_ICN_DDR,\n++\tIDX_ICN_DISPLAY,\n++\tIDX_ICN_HSL,\n++\tIDX_ICN_NIC,\n++\tIDX_ICN_VID,\n++\tIDX_FLEXGEN_07,\n++\tIDX_FLEXGEN_08,\n++\tIDX_FLEXGEN_09,\n++\tIDX_FLEXGEN_10,\n++\tIDX_FLEXGEN_11,\n++\tIDX_FLEXGEN_12,\n++\tIDX_FLEXGEN_13,\n++\tIDX_FLEXGEN_14,\n++\tIDX_FLEXGEN_15,\n++\tIDX_FLEXGEN_16,\n++\tIDX_FLEXGEN_17,\n++\tIDX_FLEXGEN_18,\n++\tIDX_FLEXGEN_19,\n++\tIDX_FLEXGEN_20,\n++\tIDX_FLEXGEN_21,\n++\tIDX_FLEXGEN_22,\n++\tIDX_FLEXGEN_23,\n++\tIDX_FLEXGEN_24,\n++\tIDX_FLEXGEN_25,\n++\tIDX_FLEXGEN_26,\n++\tIDX_FLEXGEN_27,\n++\tIDX_FLEXGEN_28,\n++\tIDX_FLEXGEN_29,\n++\tIDX_FLEXGEN_30,\n++\tIDX_FLEXGEN_31,\n++\tIDX_FLEXGEN_32,\n++\tIDX_FLEXGEN_33,\n++\tIDX_FLEXGEN_34,\n++\tIDX_FLEXGEN_35,\n++\tIDX_FLEXGEN_36,\n++\tIDX_FLEXGEN_37,\n++\tIDX_FLEXGEN_38,\n++\tIDX_FLEXGEN_39,\n++\tIDX_FLEXGEN_40,\n++\tIDX_FLEXGEN_41,\n++\tIDX_FLEXGEN_42,\n++\tIDX_FLEXGEN_43,\n++\tIDX_FLEXGEN_44,\n++\tIDX_FLEXGEN_45,\n++\tIDX_FLEXGEN_46,\n++\tIDX_FLEXGEN_47,\n++\tIDX_FLEXGEN_48,\n++\tIDX_FLEXGEN_49,\n++\tIDX_FLEXGEN_50,\n++\tIDX_FLEXGEN_51,\n++\tIDX_FLEXGEN_52,\n++\tIDX_FLEXGEN_53,\n++\tIDX_FLEXGEN_54,\n++\tIDX_FLEXGEN_55,\n++\tIDX_FLEXGEN_56,\n++\tIDX_FLEXGEN_57,\n++\tIDX_FLEXGEN_58,\n++\tIDX_FLEXGEN_59,\n++\tIDX_FLEXGEN_60,\n++\tIDX_FLEXGEN_61,\n++\tIDX_FLEXGEN_62,\n++\tIDX_FLEXGEN_63,\n++\tIDX_ICN_APB1,\n++\tIDX_ICN_APB2,\n++\tIDX_ICN_APB3,\n++\tIDX_ICN_APB4,\n++\tIDX_ICN_APBDBG,\n++\tIDX_TIMG1,\n++\tIDX_TIMG2,\n++\tIDX_PLL3,\n++\tDSI_TXBYTE,\n+ };\n+ \n+-static const char * const adc3_src[] = {\n+-\t\"ck_flexgen_47\", \"ck_icn_ls_mcu\", \"ck_flexgen_46\"\n++static const struct clk_parent_data adc12_src[] = {\n++\t{ .index = IDX_FLEXGEN_46 },\n++\t{ .index = IDX_ICN_LS_MCU },\n+ };\n+ \n+-static const char * const usb2phy1_src[] = {\n+-\t\"ck_flexgen_57\", \"hse_div2_ck\"\n++static const struct clk_parent_data adc3_src[] = {\n++\t{ .index = IDX_FLEXGEN_47 },\n++\t{ .index = IDX_ICN_LS_MCU },\n++\t{ .index = IDX_FLEXGEN_46 },\n+ };\n+ \n+-static const char * const usb2phy2_src[] = {\n+-\t\"ck_flexgen_58\", \"hse_div2_ck\"\n++static const struct clk_parent_data usb2phy1_src[] = {\n++\t{ .index = IDX_FLEXGEN_57 },\n++\t{ .index = IDX_HSE_DIV2 },\n+ };\n+ \n+-static const char * const usb3pciphy_src[] = {\n+-\t\"ck_flexgen_34\", \"hse_div2_ck\"\n++static const struct clk_parent_data usb2phy2_src[] = {\n++\t{ .index = IDX_FLEXGEN_58 },\n++\t{ .index = IDX_HSE_DIV2 },\n+ };\n+ \n+-static const char * const dsiblane_src[] = {\n+-\t\"txbyteclk\", \"ck_ker_ltdc\"\n++static const struct clk_parent_data usb3pciphy_src[] = {\n++\t{ .index = IDX_FLEXGEN_34 },\n++\t{ .index = IDX_HSE_DIV2 },\n+ };\n+ \n+-static const char * const dsiphy_src[] = {\n+-\t\"ck_flexgen_28\", \"hse_ck\"\n++static const struct clk_parent_data dsiblane_src[] = {\n++\t{ .index = DSI_TXBYTE },\n++\t{ .name = \"ck_ker_ltdc\" },\n+ };\n+ \n+-static const char * const lvdsphy_src[] = {\n+-\t\"ck_flexgen_32\", \"hse_ck\"\n++static const struct clk_parent_data dsiphy_src[] = {\n++\t{ .index = IDX_FLEXGEN_28 },\n++\t{ .index = IDX_HSE },\n+ };\n+ \n+-static const char * const dts_src[] = {\n+-\t\"hsi_ck\", \"hse_ck\", \"msi_ck\"\n++static const struct clk_parent_data lvdsphy_src[] = {\n++\t{ .index = IDX_FLEXGEN_32 },\n++\t{ .index = IDX_HSE },\n+ };\n+ \n+-static const char * const mco1_src[] = {\n+-\t\"ck_flexgen_61\", \"ck_obs0\"\n++static const struct clk_parent_data dts_src[] = {\n++\t{ .index = IDX_HSI },\n++\t{ .index = IDX_HSE },\n++\t{ .index = IDX_MSI },\n+ };\n+ \n+-static const char * const mco2_src[] = {\n+-\t\"ck_flexgen_62\", \"ck_obs1\"\n++static const struct clk_parent_data mco1_src[] = {\n++\t{ .index = IDX_FLEXGEN_61 },\n++};\n++\n++static const struct clk_parent_data mco2_src[] = {\n++\t{ .index = IDX_FLEXGEN_62 },\n+ };\n+ \n+ enum enum_mux_cfg {\n+@@ -104,7 +199,7 @@ enum enum_mux_cfg {\n+ \n+ #define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\\\n+ \t\t.num_parents\t= ARRAY_SIZE(src),\\\n+-\t\t.parent_names\t= src,\\\n++\t\t.parent_data\t= src,\\\n+ \t\t.reg_off\t= (_offset),\\\n+ \t\t.shift\t\t= (_shift),\\\n+ \t\t.width\t\t= (_witdh),\\\n+@@ -443,42 +538,42 @@ static int stm32mp25_check_security(struct udevice *dev, void __iomem *base,\n+ \n+ static const struct clock_config stm32mp25_clock_cfg[] = {\n+ \t/* ADC */\n+-\tSTM32_GATE(CK_BUS_ADC12, \"ck_icn_p_adc12\", \"ck_icn_ls_mcu\", 0, GATE_ADC12,\n++\tSTM32_GATE(CK_BUS_ADC12, \"ck_icn_p_adc12\", IDX_ICN_LS_MCU, 0, GATE_ADC12,\n+ \t\t SEC_RIFSC(58)),\n+ \tSTM32_COMPOSITE_NODIV(CK_KER_ADC12, \"ck_ker_adc12\", 0, SEC_RIFSC(58),\n+ \t\t\t GATE_ADC12, MUX_ADC12),\n+-\tSTM32_GATE(CK_BUS_ADC3, \"ck_icn_p_adc3\", \"ck_icn_ls_mcu\", 0, GATE_ADC3, SEC_RIFSC(59)),\n++\tSTM32_GATE(CK_BUS_ADC3, \"ck_icn_p_adc3\", IDX_ICN_LS_MCU, 0, GATE_ADC3, SEC_RIFSC(59)),\n+ \tSTM32_COMPOSITE_NODIV(CK_KER_ADC3, \"ck_ker_adc3\", 0, SEC_RIFSC(59), GATE_ADC3, MUX_ADC3),\n+ \n+ \t/* ADF */\n+-\tSTM32_GATE(CK_BUS_ADF1, \"ck_icn_p_adf1\", \"ck_icn_ls_mcu\", 0, GATE_ADF1, SEC_RIFSC(55)),\n+-\tSTM32_GATE(CK_KER_ADF1, \"ck_ker_adf1\", \"ck_flexgen_42\", 0, GATE_ADF1, SEC_RIFSC(55)),\n++\tSTM32_GATE(CK_BUS_ADF1, \"ck_icn_p_adf1\", IDX_ICN_LS_MCU, 0, GATE_ADF1, SEC_RIFSC(55)),\n++\tSTM32_GATE(CK_KER_ADF1, \"ck_ker_adf1\", IDX_FLEXGEN_42, 0, GATE_ADF1, SEC_RIFSC(55)),\n+ \n+ \t/* Camera */\n+ \t/* DCMI */\n+-\tSTM32_GATE(CK_BUS_CCI, \"ck_icn_p_cci\", \"ck_icn_ls_mcu\", 0, GATE_CCI, SEC_RIFSC(88)),\n++\tSTM32_GATE(CK_BUS_CCI, \"ck_icn_p_cci\", IDX_ICN_LS_MCU, 0, GATE_CCI, SEC_RIFSC(88)),\n+ \n+ \t/* CSI-HOST */\n+-\tSTM32_GATE(CK_BUS_CSI, \"ck_icn_p_csi\", \"ck_icn_apb4\", 0, GATE_CSI, SEC_RIFSC(86)),\n+-\tSTM32_GATE(CK_KER_CSI, \"ck_ker_csi\", \"ck_flexgen_29\", 0, GATE_CSI, SEC_RIFSC(86)),\n+-\tSTM32_GATE(CK_KER_CSITXESC, \"ck_ker_csitxesc\", \"ck_flexgen_30\", 0, GATE_CSI,\n++\tSTM32_GATE(CK_BUS_CSI, \"ck_icn_p_csi\", IDX_ICN_APB4, 0, GATE_CSI, SEC_RIFSC(86)),\n++\tSTM32_GATE(CK_KER_CSI, \"ck_ker_csi\", IDX_FLEXGEN_29, 0, GATE_CSI, SEC_RIFSC(86)),\n++\tSTM32_GATE(CK_KER_CSITXESC, \"ck_ker_csitxesc\", IDX_FLEXGEN_30, 0, GATE_CSI,\n+ \t\t SEC_RIFSC(86)),\n+ \n+ \t/* CSI-PHY */\n+-\tSTM32_GATE(CK_KER_CSIPHY, \"ck_ker_csiphy\", \"ck_flexgen_31\", 0, GATE_CSI,\n++\tSTM32_GATE(CK_KER_CSIPHY, \"ck_ker_csiphy\", IDX_FLEXGEN_31, 0, GATE_CSI,\n+ \t\t SEC_RIFSC(86)),\n+ \n+ \t/* DCMIPP */\n+-\tSTM32_GATE(CK_BUS_DCMIPP, \"ck_icn_p_dcmipp\", \"ck_icn_apb4\", 0, GATE_DCMIPP,\n++\tSTM32_GATE(CK_BUS_DCMIPP, \"ck_icn_p_dcmipp\", IDX_ICN_APB4, 0, GATE_DCMIPP,\n+ \t\t SEC_RIFSC(87)),\n+ \n+ \t/* CRC */\n+-\tSTM32_GATE(CK_BUS_CRC, \"ck_icn_p_crc\", \"ck_icn_ls_mcu\", 0, GATE_CRC, SEC_RIFSC(109)),\n++\tSTM32_GATE(CK_BUS_CRC, \"ck_icn_p_crc\", IDX_ICN_LS_MCU, 0, GATE_CRC, SEC_RIFSC(109)),\n+ \n+ \t/* CRYP */\n+-\tSTM32_GATE(CK_BUS_CRYP1, \"ck_icn_p_cryp1\", \"ck_icn_ls_mcu\", 0, GATE_CRYP1,\n++\tSTM32_GATE(CK_BUS_CRYP1, \"ck_icn_p_cryp1\", IDX_ICN_LS_MCU, 0, GATE_CRYP1,\n+ \t\t SEC_RIFSC(96)),\n+-\tSTM32_GATE(CK_BUS_CRYP2, \"ck_icn_p_cryp2\", \"ck_icn_ls_mcu\", 0, GATE_CRYP2,\n++\tSTM32_GATE(CK_BUS_CRYP2, \"ck_icn_p_cryp2\", IDX_ICN_LS_MCU, 0, GATE_CRYP2,\n+ \t\t SEC_RIFSC(97)),\n+ \n+ \t/* DBG & TRACE*/\n+@@ -486,17 +581,17 @@ static const struct clock_config stm32mp25_clock_cfg[] = {\n+ \n+ \t/* Display subsystem */\n+ \t/* LTDC */\n+-\tSTM32_GATE(CK_BUS_LTDC, \"ck_icn_p_ltdc\", \"ck_icn_apb4\", 0, GATE_LTDC, SEC_RIFSC(80)),\n+-\tSTM32_GATE(CK_KER_LTDC, \"ck_ker_ltdc\", \"ck_flexgen_27\", CLK_SET_RATE_PARENT, GATE_LTDC,\n++\tSTM32_GATE(CK_BUS_LTDC, \"ck_icn_p_ltdc\", IDX_ICN_APB4, 0, GATE_LTDC, SEC_RIFSC(80)),\n++\tSTM32_GATE(CK_KER_LTDC, \"ck_ker_ltdc\", IDX_FLEXGEN_27, CLK_SET_RATE_PARENT, GATE_LTDC,\n+ \t\t SEC_RIFSC(80)),\n+ \n+ \t/* DSI */\n+-\tSTM32_GATE(CK_BUS_DSI, \"ck_icn_p_dsi\", \"ck_icn_apb4\", 0, GATE_DSI, SEC_RIFSC(81)),\n++\tSTM32_GATE(CK_BUS_DSI, \"ck_icn_p_dsi\", IDX_ICN_APB4, 0, GATE_DSI, SEC_RIFSC(81)),\n+ \tSTM32_COMPOSITE_NODIV(CK_KER_DSIBLANE, \"clk_lanebyte\", 0, SEC_RIFSC(81),\n+ \t\t\t GATE_DSI, MUX_DSIBLANE),\n+ \n+ \t/* LVDS */\n+-\tSTM32_GATE(CK_BUS_LVDS, \"ck_icn_p_lvds\", \"ck_icn_apb4\", 0, GATE_LVDS, SEC_RIFSC(84)),\n++\tSTM32_GATE(CK_BUS_LVDS, \"ck_icn_p_lvds\", IDX_ICN_APB4, 0, GATE_LVDS, SEC_RIFSC(84)),\n+ \n+ \t/* DSI PHY */\n+ \tSTM32_COMPOSITE_NODIV(CK_KER_DSIPHY, \"ck_ker_dsiphy\", 0, SEC_RIFSC(81),\n+@@ -510,88 +605,88 @@ static const struct clock_config stm32mp25_clock_cfg[] = {\n+ \tSTM32_COMPOSITE_NODIV(CK_KER_DTS, \"ck_ker_dts\", 0, SEC_RIFSC(107), GATE_DTS, MUX_DTS),\n+ \n+ \t/* ETHERNET */\n+-\tSTM32_GATE(CK_BUS_ETH1, \"ck_icn_p_eth1\", \"ck_icn_ls_mcu\", 0, GATE_ETH1, SEC_RIFSC(60)),\n+-\tSTM32_GATE(CK_ETH1_STP, \"ck_ker_eth1stp\", \"ck_icn_ls_mcu\", 0, GATE_ETH1STP,\n++\tSTM32_GATE(CK_BUS_ETH1, \"ck_icn_p_eth1\", IDX_ICN_LS_MCU, 0, GATE_ETH1, SEC_RIFSC(60)),\n++\tSTM32_GATE(CK_ETH1_STP, \"ck_ker_eth1stp\", IDX_ICN_LS_MCU, 0, GATE_ETH1STP,\n+ \t\t SEC_RIFSC(60)),\n+-\tSTM32_GATE(CK_KER_ETH1, \"ck_ker_eth1\", \"ck_flexgen_54\", 0, GATE_ETH1, SEC_RIFSC(60)),\n+-\tSTM32_GATE(CK_KER_ETH1, \"ck_ker_eth1ptp\", \"ck_flexgen_56\", 0, GATE_ETH1, SEC_RIFSC(60)),\n+-\tSTM32_GATE(CK_ETH1_MAC, \"ck_ker_eth1mac\", \"ck_icn_ls_mcu\", 0, GATE_ETH1MAC,\n++\tSTM32_GATE(CK_KER_ETH1, \"ck_ker_eth1\", IDX_FLEXGEN_54, 0, GATE_ETH1, SEC_RIFSC(60)),\n++\tSTM32_GATE(CK_KER_ETH1, \"ck_ker_eth1ptp\", IDX_FLEXGEN_56, 0, GATE_ETH1, SEC_RIFSC(60)),\n++\tSTM32_GATE(CK_ETH1_MAC, \"ck_ker_eth1mac\", IDX_ICN_LS_MCU, 0, GATE_ETH1MAC,\n+ \t\t SEC_RIFSC(60)),\n+-\tSTM32_GATE(CK_ETH1_TX, \"ck_ker_eth1tx\", \"ck_icn_ls_mcu\", 0, GATE_ETH1TX, SEC_RIFSC(60)),\n+-\tSTM32_GATE(CK_ETH1_RX, \"ck_ker_eth1rx\", \"ck_icn_ls_mcu\", 0, GATE_ETH1RX, SEC_RIFSC(60)),\n++\tSTM32_GATE(CK_ETH1_TX, \"ck_ker_eth1tx\", IDX_ICN_LS_MCU, 0, GATE_ETH1TX, SEC_RIFSC(60)),\n++\tSTM32_GATE(CK_ETH1_RX, \"ck_ker_eth1rx\", IDX_ICN_LS_MCU, 0, GATE_ETH1RX, SEC_RIFSC(60)),\n+ \n+-\tSTM32_GATE(CK_BUS_ETH2, \"ck_icn_p_eth2\", \"ck_icn_ls_mcu\", 0, GATE_ETH2, SEC_RIFSC(61)),\n+-\tSTM32_GATE(CK_ETH2_STP, \"ck_ker_eth2stp\", \"ck_icn_ls_mcu\", 0, GATE_ETH2STP,\n++\tSTM32_GATE(CK_BUS_ETH2, \"ck_icn_p_eth2\", IDX_ICN_LS_MCU, 0, GATE_ETH2, SEC_RIFSC(61)),\n++\tSTM32_GATE(CK_ETH2_STP, \"ck_ker_eth2stp\", IDX_ICN_LS_MCU, 0, GATE_ETH2STP,\n+ \t\t SEC_RIFSC(61)),\n+-\tSTM32_GATE(CK_KER_ETH2, \"ck_ker_eth2\", \"ck_flexgen_54\", 0, GATE_ETH2, SEC_RIFSC(61)),\n+-\tSTM32_GATE(CK_KER_ETH2, \"ck_ker_eth2ptp\", \"ck_flexgen_56\", 0, GATE_ETH2, SEC_RIFSC(61)),\n+-\tSTM32_GATE(CK_ETH2_MAC, \"ck_ker_eth2mac\", \"ck_icn_ls_mcu\", 0, GATE_ETH2MAC,\n++\tSTM32_GATE(CK_KER_ETH2, \"ck_ker_eth2\", IDX_FLEXGEN_54, 0, GATE_ETH2, SEC_RIFSC(61)),\n++\tSTM32_GATE(CK_KER_ETH2, \"ck_ker_eth2ptp\", IDX_FLEXGEN_56, 0, GATE_ETH2, SEC_RIFSC(61)),\n++\tSTM32_GATE(CK_ETH2_MAC, \"ck_ker_eth2mac\", IDX_ICN_LS_MCU, 0, GATE_ETH2MAC,\n+ \t\t SEC_RIFSC(61)),\n+-\tSTM32_GATE(CK_ETH2_TX, \"ck_ker_eth2tx\", \"ck_icn_ls_mcu\", 0, GATE_ETH2TX, SEC_RIFSC(61)),\n+-\tSTM32_GATE(CK_ETH2_RX, \"ck_ker_eth2rx\", \"ck_icn_ls_mcu\", 0, GATE_ETH2RX, SEC_RIFSC(61)),\n++\tSTM32_GATE(CK_ETH2_TX, \"ck_ker_eth2tx\", IDX_ICN_LS_MCU, 0, GATE_ETH2TX, SEC_RIFSC(61)),\n++\tSTM32_GATE(CK_ETH2_RX, \"ck_ker_eth2rx\", IDX_ICN_LS_MCU, 0, GATE_ETH2RX, SEC_RIFSC(61)),\n+ \n+-\tSTM32_GATE(CK_BUS_ETHSW, \"ck_icn_p_ethsw\", \"ck_icn_ls_mcu\", 0, GATE_ETHSWMAC,\n++\tSTM32_GATE(CK_BUS_ETHSW, \"ck_icn_p_ethsw\", IDX_ICN_LS_MCU, 0, GATE_ETHSWMAC,\n+ \t\t SEC_RIFSC(70)),\n+-\tSTM32_GATE(CK_KER_ETHSW, \"ck_ker_ethsw\", \"ck_flexgen_54\", 0, GATE_ETHSW,\n++\tSTM32_GATE(CK_KER_ETHSW, \"ck_ker_ethsw\", IDX_FLEXGEN_54, 0, GATE_ETHSW,\n+ \t\t SEC_RIFSC(70)),\n+-\tSTM32_GATE(CK_KER_ETHSWREF, \"ck_ker_ethswref\", \"ck_flexgen_60\", 0, GATE_ETHSWREF,\n++\tSTM32_GATE(CK_KER_ETHSWREF, \"ck_ker_ethswref\", IDX_FLEXGEN_60, 0, GATE_ETHSWREF,\n+ \t\t SEC_RIFSC(70)),\n+ \n+ \t/* FDCAN */\n+-\tSTM32_GATE(CK_BUS_FDCAN, \"ck_icn_p_fdcan\", \"ck_icn_apb2\", 0, GATE_FDCAN, SEC_RIFSC(56)),\n+-\tSTM32_GATE(CK_KER_FDCAN, \"ck_ker_fdcan\", \"ck_flexgen_26\", 0, GATE_FDCAN, SEC_RIFSC(56)),\n++\tSTM32_GATE(CK_BUS_FDCAN, \"ck_icn_p_fdcan\", IDX_ICN_APB2, 0, GATE_FDCAN, SEC_RIFSC(56)),\n++\tSTM32_GATE(CK_KER_FDCAN, \"ck_ker_fdcan\", IDX_FLEXGEN_26, 0, GATE_FDCAN, SEC_RIFSC(56)),\n+ \n+ \t/* GPU */\n+-\tSTM32_GATE(CK_BUS_GPU, \"ck_icn_m_gpu\", \"ck_flexgen_59\", 0, GATE_GPU, SEC_RIFSC(79)),\n+-\tSTM32_GATE(CK_KER_GPU, \"ck_ker_gpu\", \"ck_pll3\", 0, GATE_GPU, SEC_RIFSC(79)),\n++\tSTM32_GATE(CK_BUS_GPU, \"ck_icn_m_gpu\", IDX_FLEXGEN_59, 0, GATE_GPU, SEC_RIFSC(79)),\n++\tSTM32_GATE(CK_KER_GPU, \"ck_ker_gpu\", IDX_PLL3, 0, GATE_GPU, SEC_RIFSC(79)),\n+ \n+ \t/* HASH */\n+-\tSTM32_GATE(CK_BUS_HASH, \"ck_icn_p_hash\", \"ck_icn_ls_mcu\", 0, GATE_HASH, SEC_RIFSC(95)),\n++\tSTM32_GATE(CK_BUS_HASH, \"ck_icn_p_hash\", IDX_ICN_LS_MCU, 0, GATE_HASH, SEC_RIFSC(95)),\n+ \n+ \t/* HDP */\n+-\tSTM32_GATE(CK_BUS_HDP, \"ck_icn_p_hdp\", \"ck_icn_apb3\", 0, GATE_HDP, SEC_RIFSC(57)),\n++\tSTM32_GATE(CK_BUS_HDP, \"ck_icn_p_hdp\", IDX_ICN_APB3, 0, GATE_HDP, SEC_RIFSC(57)),\n+ \n+ \t/* I2C */\n+-\tSTM32_GATE(CK_KER_I2C1, \"ck_ker_i2c1\", \"ck_flexgen_12\", 0, GATE_I2C1, SEC_RIFSC(41)),\n+-\tSTM32_GATE(CK_KER_I2C2, \"ck_ker_i2c2\", \"ck_flexgen_12\", 0, GATE_I2C2, SEC_RIFSC(42)),\n+-\tSTM32_GATE(CK_KER_I2C3, \"ck_ker_i2c3\", \"ck_flexgen_13\", 0, GATE_I2C3, SEC_RIFSC(43)),\n+-\tSTM32_GATE(CK_KER_I2C5, \"ck_ker_i2c5\", \"ck_flexgen_13\", 0, GATE_I2C5, SEC_RIFSC(45)),\n+-\tSTM32_GATE(CK_KER_I2C4, \"ck_ker_i2c4\", \"ck_flexgen_14\", 0, GATE_I2C4, SEC_RIFSC(44)),\n+-\tSTM32_GATE(CK_KER_I2C6, \"ck_ker_i2c6\", \"ck_flexgen_14\", 0, GATE_I2C6, SEC_RIFSC(46)),\n+-\tSTM32_GATE(CK_KER_I2C7, \"ck_ker_i2c7\", \"ck_flexgen_15\", 0, GATE_I2C7, SEC_RIFSC(47)),\n+-\tSTM32_GATE(CK_KER_I2C8, \"ck_ker_i2c8\", \"ck_flexgen_38\", 0, GATE_I2C8, SEC_RIFSC(48)),\n++\tSTM32_GATE(CK_KER_I2C1, \"ck_ker_i2c1\", IDX_FLEXGEN_12, 0, GATE_I2C1, SEC_RIFSC(41)),\n++\tSTM32_GATE(CK_KER_I2C2, \"ck_ker_i2c2\", IDX_FLEXGEN_12, 0, GATE_I2C2, SEC_RIFSC(42)),\n++\tSTM32_GATE(CK_KER_I2C3, \"ck_ker_i2c3\", IDX_FLEXGEN_13, 0, GATE_I2C3, SEC_RIFSC(43)),\n++\tSTM32_GATE(CK_KER_I2C5, \"ck_ker_i2c5\", IDX_FLEXGEN_13, 0, GATE_I2C5, SEC_RIFSC(45)),\n++\tSTM32_GATE(CK_KER_I2C4, \"ck_ker_i2c4\", IDX_FLEXGEN_14, 0, GATE_I2C4, SEC_RIFSC(44)),\n++\tSTM32_GATE(CK_KER_I2C6, \"ck_ker_i2c6\", IDX_FLEXGEN_14, 0, GATE_I2C6, SEC_RIFSC(46)),\n++\tSTM32_GATE(CK_KER_I2C7, \"ck_ker_i2c7\", IDX_FLEXGEN_15, 0, GATE_I2C7, SEC_RIFSC(47)),\n++\tSTM32_GATE(CK_KER_I2C8, \"ck_ker_i2c8\", IDX_FLEXGEN_38, 0, GATE_I2C8, SEC_RIFSC(48)),\n+ \n+ \t/* I3C */\n+-\tSTM32_GATE(CK_KER_I3C1, \"ck_ker_i3c1\", \"ck_flexgen_12\", 0, GATE_I3C1, SEC_RIFSC(114)),\n+-\tSTM32_GATE(CK_KER_I3C2, \"ck_ker_i3c2\", \"ck_flexgen_12\", 0, GATE_I3C2, SEC_RIFSC(115)),\n+-\tSTM32_GATE(CK_KER_I3C3, \"ck_ker_i3c3\", \"ck_flexgen_13\", 0, GATE_I3C3, SEC_RIFSC(116)),\n+-\tSTM32_GATE(CK_KER_I3C4, \"ck_ker_i3c4\", \"ck_flexgen_36\", 0, GATE_I3C4, SEC_RIFSC(117)),\n++\tSTM32_GATE(CK_KER_I3C1, \"ck_ker_i3c1\", IDX_FLEXGEN_12, 0, GATE_I3C1, SEC_RIFSC(114)),\n++\tSTM32_GATE(CK_KER_I3C2, \"ck_ker_i3c2\", IDX_FLEXGEN_12, 0, GATE_I3C2, SEC_RIFSC(115)),\n++\tSTM32_GATE(CK_KER_I3C3, \"ck_ker_i3c3\", IDX_FLEXGEN_13, 0, GATE_I3C3, SEC_RIFSC(116)),\n++\tSTM32_GATE(CK_KER_I3C4, \"ck_ker_i3c4\", IDX_FLEXGEN_36, 0, GATE_I3C4, SEC_RIFSC(117)),\n+ \n+ \t/* I2S */\n+-\tSTM32_GATE(CK_BUS_IS2M, \"ck_icn_p_is2m\", \"ck_icn_apb3\", 0, GATE_IS2M, SEC_RIFRCC(IS2M)),\n++\tSTM32_GATE(CK_BUS_IS2M, \"ck_icn_p_is2m\", IDX_ICN_APB3, 0, GATE_IS2M, SEC_RIFRCC(IS2M)),\n+ \n+ \t/* IWDG */\n+-\tSTM32_GATE(CK_BUS_IWDG1, \"ck_icn_p_iwdg1\", \"ck_icn_apb3\", 0, GATE_IWDG1, SEC_RIFSC(98)),\n+-\tSTM32_GATE(CK_BUS_IWDG2, \"ck_icn_p_iwdg2\", \"ck_icn_apb3\", 0, GATE_IWDG2, SEC_RIFSC(99)),\n+-\tSTM32_GATE(CK_BUS_IWDG3, \"ck_icn_p_iwdg3\", \"ck_icn_apb3\", 0, GATE_IWDG3, SEC_RIFSC(100)),\n+-\tSTM32_GATE(CK_BUS_IWDG4, \"ck_icn_p_iwdg4\", \"ck_icn_apb3\", 0, GATE_IWDG4, SEC_RIFSC(101)),\n+-\tSTM32_GATE(CK_BUS_IWDG5, \"ck_icn_p_iwdg5\", \"ck_icn_ls_mcu\", 0, GATE_IWDG5,\n++\tSTM32_GATE(CK_BUS_IWDG1, \"ck_icn_p_iwdg1\", IDX_ICN_APB3, 0, GATE_IWDG1, SEC_RIFSC(98)),\n++\tSTM32_GATE(CK_BUS_IWDG2, \"ck_icn_p_iwdg2\", IDX_ICN_APB3, 0, GATE_IWDG2, SEC_RIFSC(99)),\n++\tSTM32_GATE(CK_BUS_IWDG3, \"ck_icn_p_iwdg3\", IDX_ICN_APB3, 0, GATE_IWDG3, SEC_RIFSC(100)),\n++\tSTM32_GATE(CK_BUS_IWDG4, \"ck_icn_p_iwdg4\", IDX_ICN_APB3, 0, GATE_IWDG4, SEC_RIFSC(101)),\n++\tSTM32_GATE(CK_BUS_IWDG5, \"ck_icn_p_iwdg5\", IDX_ICN_LS_MCU, 0, GATE_IWDG5,\n+ \t\t SEC_RIFSC(102)),\n+ \n+ \t/* LPTIM */\n+-\tSTM32_GATE(CK_KER_LPTIM1, \"ck_ker_lptim1\", \"ck_flexgen_07\", 0, GATE_LPTIM1,\n++\tSTM32_GATE(CK_KER_LPTIM1, \"ck_ker_lptim1\", IDX_FLEXGEN_07, 0, GATE_LPTIM1,\n+ \t\t SEC_RIFSC(17)),\n+-\tSTM32_GATE(CK_KER_LPTIM2, \"ck_ker_lptim2\", \"ck_flexgen_07\", 0, GATE_LPTIM2,\n++\tSTM32_GATE(CK_KER_LPTIM2, \"ck_ker_lptim2\", IDX_FLEXGEN_07, 0, GATE_LPTIM2,\n+ \t\t SEC_RIFSC(18)),\n+-\tSTM32_GATE(CK_KER_LPTIM3, \"ck_ker_lptim3\", \"ck_flexgen_40\", 0, GATE_LPTIM3,\n++\tSTM32_GATE(CK_KER_LPTIM3, \"ck_ker_lptim3\", IDX_FLEXGEN_40, 0, GATE_LPTIM3,\n+ \t\t SEC_RIFSC(19)),\n+-\tSTM32_GATE(CK_KER_LPTIM4, \"ck_ker_lptim4\", \"ck_flexgen_41\", 0, GATE_LPTIM4,\n++\tSTM32_GATE(CK_KER_LPTIM4, \"ck_ker_lptim4\", IDX_FLEXGEN_41, 0, GATE_LPTIM4,\n+ \t\t SEC_RIFSC(20)),\n+-\tSTM32_GATE(CK_KER_LPTIM5, \"ck_ker_lptim5\", \"ck_flexgen_41\", 0, GATE_LPTIM5,\n++\tSTM32_GATE(CK_KER_LPTIM5, \"ck_ker_lptim5\", IDX_FLEXGEN_41, 0, GATE_LPTIM5,\n+ \t\t SEC_RIFSC(21)),\n+ \n+ \t/* LPUART */\n+-\tSTM32_GATE(CK_KER_LPUART1, \"ck_ker_lpuart1\", \"ck_flexgen_39\", 0, GATE_LPUART1,\n++\tSTM32_GATE(CK_KER_LPUART1, \"ck_ker_lpuart1\", IDX_FLEXGEN_39, 0, GATE_LPUART1,\n+ \t\t SEC_RIFSC(40)),\n+ \n+ \t/* MCO1 & MCO2 */\n+@@ -599,102 +694,102 @@ static const struct clock_config stm32mp25_clock_cfg[] = {\n+ \tSTM32_COMPOSITE_NODIV(CK_MCO2, \"ck_mco2\", 0, SEC_RIFRCC(MCO2), GATE_MCO2, MUX_MCO2),\n+ \n+ \t/* MDF */\n+-\tSTM32_GATE(CK_KER_MDF1, \"ck_ker_mdf1\", \"ck_flexgen_23\", 0, GATE_MDF1, SEC_RIFSC(54)),\n++\tSTM32_GATE(CK_KER_MDF1, \"ck_ker_mdf1\", IDX_FLEXGEN_23, 0, GATE_MDF1, SEC_RIFSC(54)),\n+ \n+ \t/* OCTOSPI */\n+-\tSTM32_GATE(CK_BUS_OSPIIOM, \"ck_icn_p_ospiiom\", \"ck_icn_ls_mcu\", 0, GATE_OSPIIOM,\n++\tSTM32_GATE(CK_BUS_OSPIIOM, \"ck_icn_p_ospiiom\", IDX_ICN_LS_MCU, 0, GATE_OSPIIOM,\n+ \t\t SEC_RIFSC(111)),\n+ \n+ \t/* PCIE */\n+-\tSTM32_GATE(CK_BUS_PCIE, \"ck_icn_p_pcie\", \"ck_icn_ls_mcu\", 0, GATE_PCIE, SEC_RIFSC(68)),\n++\tSTM32_GATE(CK_BUS_PCIE, \"ck_icn_p_pcie\", IDX_ICN_LS_MCU, 0, GATE_PCIE, SEC_RIFSC(68)),\n+ \n+ \t/* PKA */\n+-\tSTM32_GATE(CK_BUS_PKA, \"ck_icn_p_pka\", \"ck_icn_ls_mcu\", 0, GATE_PKA, SEC_RIFSC(93)),\n++\tSTM32_GATE(CK_BUS_PKA, \"ck_icn_p_pka\", IDX_ICN_LS_MCU, 0, GATE_PKA, SEC_RIFSC(93)),\n+ \n+ \t/* RNG */\n+-\tSTM32_GATE(CK_BUS_RNG, \"ck_icn_p_rng\", \"ck_icn_ls_mcu\", CLK_IGNORE_UNUSED, GATE_RNG,\n++\tSTM32_GATE(CK_BUS_RNG, \"ck_icn_p_rng\", IDX_ICN_LS_MCU, CLK_IGNORE_UNUSED, GATE_RNG,\n+ \t\t SEC_RIFSC(92)),\n+ \n+ \t/* SAES */\n+-\tSTM32_GATE(CK_BUS_SAES, \"ck_icn_p_saes\", \"ck_icn_ls_mcu\", 0, GATE_SAES, SEC_RIFSC(94)),\n++\tSTM32_GATE(CK_BUS_SAES, \"ck_icn_p_saes\", IDX_ICN_LS_MCU, 0, GATE_SAES, SEC_RIFSC(94)),\n+ \n+ \t/* SAI [1..4] */\n+-\tSTM32_GATE(CK_BUS_SAI1, \"ck_icn_p_sai1\", \"ck_icn_apb2\", 0, GATE_SAI1, SEC_RIFSC(49)),\n+-\tSTM32_GATE(CK_BUS_SAI2, \"ck_icn_p_sai2\", \"ck_icn_apb2\", 0, GATE_SAI2, SEC_RIFSC(50)),\n+-\tSTM32_GATE(CK_BUS_SAI3, \"ck_icn_p_sai3\", \"ck_icn_apb2\", 0, GATE_SAI3, SEC_RIFSC(51)),\n+-\tSTM32_GATE(CK_BUS_SAI4, \"ck_icn_p_sai4\", \"ck_icn_apb2\", 0, GATE_SAI4, SEC_RIFSC(52)),\n+-\tSTM32_GATE(CK_KER_SAI1, \"ck_ker_sai1\", \"ck_flexgen_23\", 0, GATE_SAI1, SEC_RIFSC(49)),\n+-\tSTM32_GATE(CK_KER_SAI2, \"ck_ker_sai2\", \"ck_flexgen_24\", 0, GATE_SAI2, SEC_RIFSC(50)),\n+-\tSTM32_GATE(CK_KER_SAI3, \"ck_ker_sai3\", \"ck_flexgen_25\", 0, GATE_SAI3, SEC_RIFSC(51)),\n+-\tSTM32_GATE(CK_KER_SAI4, \"ck_ker_sai4\", \"ck_flexgen_25\", 0, GATE_SAI4, SEC_RIFSC(52)),\n++\tSTM32_GATE(CK_BUS_SAI1, \"ck_icn_p_sai1\", IDX_ICN_APB2, 0, GATE_SAI1, SEC_RIFSC(49)),\n++\tSTM32_GATE(CK_BUS_SAI2, \"ck_icn_p_sai2\", IDX_ICN_APB2, 0, GATE_SAI2, SEC_RIFSC(50)),\n++\tSTM32_GATE(CK_BUS_SAI3, \"ck_icn_p_sai3\", IDX_ICN_APB2, 0, GATE_SAI3, SEC_RIFSC(51)),\n++\tSTM32_GATE(CK_BUS_SAI4, \"ck_icn_p_sai4\", IDX_ICN_APB2, 0, GATE_SAI4, SEC_RIFSC(52)),\n++\tSTM32_GATE(CK_KER_SAI1, \"ck_ker_sai1\", IDX_FLEXGEN_23, 0, GATE_SAI1, SEC_RIFSC(49)),\n++\tSTM32_GATE(CK_KER_SAI2, \"ck_ker_sai2\", IDX_FLEXGEN_24, 0, GATE_SAI2, SEC_RIFSC(50)),\n++\tSTM32_GATE(CK_KER_SAI3, \"ck_ker_sai3\", IDX_FLEXGEN_25, 0, GATE_SAI3, SEC_RIFSC(51)),\n++\tSTM32_GATE(CK_KER_SAI4, \"ck_ker_sai4\", IDX_FLEXGEN_25, 0, GATE_SAI4, SEC_RIFSC(52)),\n+ \n+ \t/* SDMMC */\n+-\tSTM32_GATE(CK_KER_SDMMC1, \"ck_ker_sdmmc1\", \"ck_flexgen_51\", 0, GATE_SDMMC1,\n++\tSTM32_GATE(CK_KER_SDMMC1, \"ck_ker_sdmmc1\", IDX_FLEXGEN_51, 0, GATE_SDMMC1,\n+ \t\t SEC_RIFSC(76)),\n+-\tSTM32_GATE(CK_KER_SDMMC2, \"ck_ker_sdmmc2\", \"ck_flexgen_52\", 0, GATE_SDMMC2,\n++\tSTM32_GATE(CK_KER_SDMMC2, \"ck_ker_sdmmc2\", IDX_FLEXGEN_52, 0, GATE_SDMMC2,\n+ \t\t SEC_RIFSC(77)),\n+-\tSTM32_GATE(CK_KER_SDMMC3, \"ck_ker_sdmmc3\", \"ck_flexgen_53\", 0, GATE_SDMMC3,\n++\tSTM32_GATE(CK_KER_SDMMC3, \"ck_ker_sdmmc3\", IDX_FLEXGEN_53, 0, GATE_SDMMC3,\n+ \t\t SEC_RIFSC(78)),\n+ \n+ \t/* SERC */\n+-\tSTM32_GATE(CK_BUS_SERC, \"ck_icn_p_serc\", \"ck_icn_apb3\", 0, GATE_SERC, SEC_RIFSC(110)),\n++\tSTM32_GATE(CK_BUS_SERC, \"ck_icn_p_serc\", IDX_ICN_APB3, 0, GATE_SERC, SEC_RIFSC(110)),\n+ \n+ \t/* SPDIF */\n+-\tSTM32_GATE(CK_KER_SPDIFRX, \"ck_ker_spdifrx\", \"ck_flexgen_11\", 0, GATE_SPDIFRX,\n++\tSTM32_GATE(CK_KER_SPDIFRX, \"ck_ker_spdifrx\", IDX_FLEXGEN_11, 0, GATE_SPDIFRX,\n+ \t\t SEC_RIFSC(30)),\n+ \n+ \t/* SPI */\n+-\tSTM32_GATE(CK_KER_SPI1, \"ck_ker_spi1\", \"ck_flexgen_16\", 0, GATE_SPI1, SEC_RIFSC(22)),\n+-\tSTM32_GATE(CK_KER_SPI2, \"ck_ker_spi2\", \"ck_flexgen_10\", 0, GATE_SPI2, SEC_RIFSC(23)),\n+-\tSTM32_GATE(CK_KER_SPI3, \"ck_ker_spi3\", \"ck_flexgen_10\", 0, GATE_SPI3, SEC_RIFSC(24)),\n+-\tSTM32_GATE(CK_KER_SPI4, \"ck_ker_spi4\", \"ck_flexgen_17\", 0, GATE_SPI4, SEC_RIFSC(25)),\n+-\tSTM32_GATE(CK_KER_SPI5, \"ck_ker_spi5\", \"ck_flexgen_17\", 0, GATE_SPI5, SEC_RIFSC(26)),\n+-\tSTM32_GATE(CK_KER_SPI6, \"ck_ker_spi6\", \"ck_flexgen_18\", 0, GATE_SPI6, SEC_RIFSC(27)),\n+-\tSTM32_GATE(CK_KER_SPI7, \"ck_ker_spi7\", \"ck_flexgen_18\", 0, GATE_SPI7, SEC_RIFSC(28)),\n+-\tSTM32_GATE(CK_KER_SPI8, \"ck_ker_spi8\", \"ck_flexgen_37\", 0, GATE_SPI8, SEC_RIFSC(29)),\n++\tSTM32_GATE(CK_KER_SPI1, \"ck_ker_spi1\", IDX_FLEXGEN_16, 0, GATE_SPI1, SEC_RIFSC(22)),\n++\tSTM32_GATE(CK_KER_SPI2, \"ck_ker_spi2\", IDX_FLEXGEN_10, 0, GATE_SPI2, SEC_RIFSC(23)),\n++\tSTM32_GATE(CK_KER_SPI3, \"ck_ker_spi3\", IDX_FLEXGEN_10, 0, GATE_SPI3, SEC_RIFSC(24)),\n++\tSTM32_GATE(CK_KER_SPI4, \"ck_ker_spi4\", IDX_FLEXGEN_17, 0, GATE_SPI4, SEC_RIFSC(25)),\n++\tSTM32_GATE(CK_KER_SPI5, \"ck_ker_spi5\", IDX_FLEXGEN_17, 0, GATE_SPI5, SEC_RIFSC(26)),\n++\tSTM32_GATE(CK_KER_SPI6, \"ck_ker_spi6\", IDX_FLEXGEN_18, 0, GATE_SPI6, SEC_RIFSC(27)),\n++\tSTM32_GATE(CK_KER_SPI7, \"ck_ker_spi7\", IDX_FLEXGEN_18, 0, GATE_SPI7, SEC_RIFSC(28)),\n++\tSTM32_GATE(CK_KER_SPI8, \"ck_ker_spi8\", IDX_FLEXGEN_37, 0, GATE_SPI8, SEC_RIFSC(29)),\n+ \n+ \t/* STGEN */\n+-\tSTM32_GATE(CK_KER_STGEN, \"ck_ker_stgen\", \"ck_flexgen_33\", CLK_IGNORE_UNUSED, GATE_STGEN,\n++\tSTM32_GATE(CK_KER_STGEN, \"ck_ker_stgen\", IDX_FLEXGEN_33, CLK_IGNORE_UNUSED, GATE_STGEN,\n+ \t\t SEC_RIFSC(73)),\n+ \n+ \t/* Timers */\n+-\tSTM32_GATE(CK_KER_TIM2, \"ck_ker_tim2\", \"timg1_ck\", 0, GATE_TIM2, SEC_RIFSC(1)),\n+-\tSTM32_GATE(CK_KER_TIM3, \"ck_ker_tim3\", \"timg1_ck\", 0, GATE_TIM3, SEC_RIFSC(2)),\n+-\tSTM32_GATE(CK_KER_TIM4, \"ck_ker_tim4\", \"timg1_ck\", 0, GATE_TIM4, SEC_RIFSC(3)),\n+-\tSTM32_GATE(CK_KER_TIM5, \"ck_ker_tim5\", \"timg1_ck\", 0, GATE_TIM5, SEC_RIFSC(4)),\n+-\tSTM32_GATE(CK_KER_TIM6, \"ck_ker_tim6\", \"timg1_ck\", 0, GATE_TIM6, SEC_RIFSC(5)),\n+-\tSTM32_GATE(CK_KER_TIM7, \"ck_ker_tim7\", \"timg1_ck\", 0, GATE_TIM7, SEC_RIFSC(6)),\n+-\tSTM32_GATE(CK_KER_TIM10, \"ck_ker_tim10\", \"timg1_ck\", 0, GATE_TIM10, SEC_RIFSC(8)),\n+-\tSTM32_GATE(CK_KER_TIM11, \"ck_ker_tim11\", \"timg1_ck\", 0, GATE_TIM11, SEC_RIFSC(9)),\n+-\tSTM32_GATE(CK_KER_TIM12, \"ck_ker_tim12\", \"timg1_ck\", 0, GATE_TIM12, SEC_RIFSC(10)),\n+-\tSTM32_GATE(CK_KER_TIM13, \"ck_ker_tim13\", \"timg1_ck\", 0, GATE_TIM13, SEC_RIFSC(11)),\n+-\tSTM32_GATE(CK_KER_TIM14, \"ck_ker_tim14\", \"timg1_ck\", 0, GATE_TIM14, SEC_RIFSC(12)),\n+-\n+-\tSTM32_GATE(CK_KER_TIM1, \"ck_ker_tim1\", \"timg2_ck\", 0, GATE_TIM1, SEC_RIFSC(0)),\n+-\tSTM32_GATE(CK_KER_TIM8, \"ck_ker_tim8\", \"timg2_ck\", 0, GATE_TIM8, SEC_RIFSC(7)),\n+-\tSTM32_GATE(CK_KER_TIM15, \"ck_ker_tim15\", \"timg2_ck\", 0, GATE_TIM15, SEC_RIFSC(13)),\n+-\tSTM32_GATE(CK_KER_TIM16, \"ck_ker_tim16\", \"timg2_ck\", 0, GATE_TIM16, SEC_RIFSC(14)),\n+-\tSTM32_GATE(CK_KER_TIM17, \"ck_ker_tim17\", \"timg2_ck\", 0, GATE_TIM17, SEC_RIFSC(15)),\n+-\tSTM32_GATE(CK_KER_TIM20, \"ck_ker_tim20\", \"timg2_ck\", 0, GATE_TIM20, SEC_RIFSC(20)),\n++\tSTM32_GATE(CK_KER_TIM2, \"ck_ker_tim2\", IDX_TIMG1, 0, GATE_TIM2, SEC_RIFSC(1)),\n++\tSTM32_GATE(CK_KER_TIM3, \"ck_ker_tim3\", IDX_TIMG1, 0, GATE_TIM3, SEC_RIFSC(2)),\n++\tSTM32_GATE(CK_KER_TIM4, \"ck_ker_tim4\", IDX_TIMG1, 0, GATE_TIM4, SEC_RIFSC(3)),\n++\tSTM32_GATE(CK_KER_TIM5, \"ck_ker_tim5\", IDX_TIMG1, 0, GATE_TIM5, SEC_RIFSC(4)),\n++\tSTM32_GATE(CK_KER_TIM6, \"ck_ker_tim6\", IDX_TIMG1, 0, GATE_TIM6, SEC_RIFSC(5)),\n++\tSTM32_GATE(CK_KER_TIM7, \"ck_ker_tim7\", IDX_TIMG1, 0, GATE_TIM7, SEC_RIFSC(6)),\n++\tSTM32_GATE(CK_KER_TIM10, \"ck_ker_tim10\", IDX_TIMG1, 0, GATE_TIM10, SEC_RIFSC(8)),\n++\tSTM32_GATE(CK_KER_TIM11, \"ck_ker_tim11\", IDX_TIMG1, 0, GATE_TIM11, SEC_RIFSC(9)),\n++\tSTM32_GATE(CK_KER_TIM12, \"ck_ker_tim12\", IDX_TIMG1, 0, GATE_TIM12, SEC_RIFSC(10)),\n++\tSTM32_GATE(CK_KER_TIM13, \"ck_ker_tim13\", IDX_TIMG1, 0, GATE_TIM13, SEC_RIFSC(11)),\n++\tSTM32_GATE(CK_KER_TIM14, \"ck_ker_tim14\", IDX_TIMG1, 0, GATE_TIM14, SEC_RIFSC(12)),\n++\n++\tSTM32_GATE(CK_KER_TIM1, \"ck_ker_tim1\", IDX_TIMG2, 0, GATE_TIM1, SEC_RIFSC(0)),\n++\tSTM32_GATE(CK_KER_TIM8, \"ck_ker_tim8\", IDX_TIMG2, 0, GATE_TIM8, SEC_RIFSC(7)),\n++\tSTM32_GATE(CK_KER_TIM15, \"ck_ker_tim15\", IDX_TIMG2, 0, GATE_TIM15, SEC_RIFSC(13)),\n++\tSTM32_GATE(CK_KER_TIM16, \"ck_ker_tim16\", IDX_TIMG2, 0, GATE_TIM16, SEC_RIFSC(14)),\n++\tSTM32_GATE(CK_KER_TIM17, \"ck_ker_tim17\", IDX_TIMG2, 0, GATE_TIM17, SEC_RIFSC(15)),\n++\tSTM32_GATE(CK_KER_TIM20, \"ck_ker_tim20\", IDX_TIMG2, 0, GATE_TIM20, SEC_RIFSC(20)),\n+ \n+ \t/* UART/USART */\n+-\tSTM32_GATE(CK_KER_USART2, \"ck_ker_usart2\", \"ck_flexgen_08\", 0, GATE_USART2,\n++\tSTM32_GATE(CK_KER_USART2, \"ck_ker_usart2\", IDX_FLEXGEN_08, 0, GATE_USART2,\n+ \t\t SEC_RIFSC(32)),\n+-\tSTM32_GATE(CK_KER_UART4, \"ck_ker_uart4\", \"ck_flexgen_08\", 0, GATE_UART4,\n++\tSTM32_GATE(CK_KER_UART4, \"ck_ker_uart4\", IDX_FLEXGEN_08, 0, GATE_UART4,\n+ \t\t SEC_RIFSC(34)),\n+-\tSTM32_GATE(CK_KER_USART3, \"ck_ker_usart3\", \"ck_flexgen_09\", 0, GATE_USART3,\n++\tSTM32_GATE(CK_KER_USART3, \"ck_ker_usart3\", IDX_FLEXGEN_09, 0, GATE_USART3,\n+ \t\t SEC_RIFSC(33)),\n+-\tSTM32_GATE(CK_KER_UART5, \"ck_ker_uart5\", \"ck_flexgen_09\", 0, GATE_UART5,\n++\tSTM32_GATE(CK_KER_UART5, \"ck_ker_uart5\", IDX_FLEXGEN_09, 0, GATE_UART5,\n+ \t\t SEC_RIFSC(35)),\n+-\tSTM32_GATE(CK_KER_USART1, \"ck_ker_usart1\", \"ck_flexgen_19\", 0, GATE_USART1,\n++\tSTM32_GATE(CK_KER_USART1, \"ck_ker_usart1\", IDX_FLEXGEN_19, 0, GATE_USART1,\n+ \t\t SEC_RIFSC(31)),\n+-\tSTM32_GATE(CK_KER_USART6, \"ck_ker_usart6\", \"ck_flexgen_20\", 0, GATE_USART6,\n++\tSTM32_GATE(CK_KER_USART6, \"ck_ker_usart6\", IDX_FLEXGEN_20, 0, GATE_USART6,\n+ \t\t SEC_RIFSC(36)),\n+-\tSTM32_GATE(CK_KER_UART7, \"ck_ker_uart7\", \"ck_flexgen_21\", 0, GATE_UART7,\n++\tSTM32_GATE(CK_KER_UART7, \"ck_ker_uart7\", IDX_FLEXGEN_21, 0, GATE_UART7,\n+ \t\t SEC_RIFSC(37)),\n+-\tSTM32_GATE(CK_KER_UART8, \"ck_ker_uart8\", \"ck_flexgen_21\", 0, GATE_UART8,\n++\tSTM32_GATE(CK_KER_UART8, \"ck_ker_uart8\", IDX_FLEXGEN_21, 0, GATE_UART8,\n+ \t\t SEC_RIFSC(38)),\n+-\tSTM32_GATE(CK_KER_UART9, \"ck_ker_uart9\", \"ck_flexgen_22\", 0, GATE_UART9,\n++\tSTM32_GATE(CK_KER_UART9, \"ck_ker_uart9\", IDX_FLEXGEN_22, 0, GATE_UART9,\n+ \t\t SEC_RIFSC(39)),\n+ \n+ \t/* USB2PHY1 */\n+@@ -702,9 +797,9 @@ static const struct clock_config stm32mp25_clock_cfg[] = {\n+ \t\t\t GATE_USB2PHY1, MUX_USB2PHY1),\n+ \n+ \t/* USBH */\n+-\tSTM32_GATE(CK_BUS_USB2OHCI, \"ck_icn_m_usb2ohci\", \"ck_icn_hsl\", 0, GATE_USBH,\n++\tSTM32_GATE(CK_BUS_USB2OHCI, \"ck_icn_m_usb2ohci\", IDX_ICN_HSL, 0, GATE_USBH,\n+ \t\t SEC_RIFSC(63)),\n+-\tSTM32_GATE(CK_BUS_USB2EHCI, \"ck_icn_m_usb2ehci\", \"ck_icn_hsl\", 0, GATE_USBH,\n++\tSTM32_GATE(CK_BUS_USB2EHCI, \"ck_icn_m_usb2ehci\", IDX_ICN_HSL, 0, GATE_USBH,\n+ \t\t SEC_RIFSC(63)),\n+ \n+ \t/* USB2PHY2 */\n+@@ -712,36 +807,36 @@ static const struct clock_config stm32mp25_clock_cfg[] = {\n+ \t\t\t GATE_USB2PHY2, MUX_USB2PHY2),\n+ \n+ \t/* USB3 PCIe COMBOPHY */\n+-\tSTM32_GATE(CK_BUS_USB3PCIEPHY, \"ck_icn_p_usb3pciephy\", \"ck_icn_apb4\", 0, GATE_USB3PCIEPHY,\n+-\t\t SEC_RIFSC(67)),\n++\tSTM32_GATE(CK_BUS_USB3PCIEPHY, \"ck_icn_p_usb3pciephy\", IDX_ICN_APB4, 0,\n++\t\t GATE_USB3PCIEPHY, SEC_RIFSC(67)),\n+ \n+ \tSTM32_COMPOSITE_NODIV(CK_KER_USB3PCIEPHY, \"ck_ker_usb3pciephy\", 0, SEC_RIFSC(67),\n+ \t\t\t GATE_USB3PCIEPHY, MUX_USB3PCIEPHY),\n+ \n+ \t/* USB3 DRD */\n+-\tSTM32_GATE(CK_BUS_USB3DR, \"ck_icn_m_usb3dr\", \"ck_icn_hsl\", 0, GATE_USB3DR,\n++\tSTM32_GATE(CK_BUS_USB3DR, \"ck_icn_m_usb3dr\", IDX_ICN_HSL, 0, GATE_USB3DR,\n+ \t\t SEC_RIFSC(66)),\n+-\tSTM32_GATE(CK_KER_USB2PHY2, \"ck_ker_usb2phy2\", \"ck_flexgen_58\", 0, GATE_USB3DR,\n++\tSTM32_GATE(CK_KER_USB2PHY2, \"ck_ker_usb2phy2\", IDX_FLEXGEN_58, 0, GATE_USB3DR,\n+ \t\t SEC_RIFSC(66)),\n+ \n+ \t/* UCPD */\n+-\tSTM32_GATE(CK_BUS_USBTC, \"ck_icn_p_usbtc\", \"ck_flexgen_35\", 0, GATE_USBTC,\n++\tSTM32_GATE(CK_BUS_USBTC, \"ck_icn_p_usbtc\", IDX_FLEXGEN_35, 0, GATE_USBTC,\n+ \t\t SEC_RIFSC(69)),\n+-\tSTM32_GATE(CK_KER_USBTC, \"ck_ker_usbtc\", \"ck_flexgen_35\", 0, GATE_USBTC,\n++\tSTM32_GATE(CK_KER_USBTC, \"ck_ker_usbtc\", IDX_FLEXGEN_35, 0, GATE_USBTC,\n+ \t\t SEC_RIFSC(69)),\n+ \n+ \t/* VDEC / VENC */\n+-\tSTM32_GATE(CK_BUS_VDEC, \"ck_icn_p_vdec\", \"ck_icn_apb4\", 0, GATE_VDEC, SEC_RIFSC(89)),\n+-\tSTM32_GATE(CK_BUS_VENC, \"ck_icn_p_venc\", \"ck_icn_apb4\", 0, GATE_VENC, SEC_RIFSC(90)),\n++\tSTM32_GATE(CK_BUS_VDEC, \"ck_icn_p_vdec\", IDX_ICN_APB4, 0, GATE_VDEC, SEC_RIFSC(89)),\n++\tSTM32_GATE(CK_BUS_VENC, \"ck_icn_p_venc\", IDX_ICN_APB4, 0, GATE_VENC, SEC_RIFSC(90)),\n+ \n+ \t/* VREF */\n+-\tSTM32_GATE(CK_BUS_VREF, \"ck_icn_p_vref\", \"ck_icn_apb3\", 0, RCC_VREFCFGR,\n++\tSTM32_GATE(CK_BUS_VREF, \"ck_icn_p_vref\", IDX_ICN_APB3, 0, RCC_VREFCFGR,\n+ \t\t SEC_RIFSC(106)),\n+ \n+ \t/* WWDG */\n+-\tSTM32_GATE(CK_BUS_WWDG1, \"ck_icn_p_wwdg1\", \"ck_icn_apb3\", 0, GATE_WWDG1,\n++\tSTM32_GATE(CK_BUS_WWDG1, \"ck_icn_p_wwdg1\", IDX_ICN_APB3, 0, GATE_WWDG1,\n+ \t\t SEC_RIFSC(103)),\n+-\tSTM32_GATE(CK_BUS_WWDG2, \"ck_icn_p_wwdg2\", \"ck_icn_ls_mcu\", 0, GATE_WWDG2,\n++\tSTM32_GATE(CK_BUS_WWDG2, \"ck_icn_p_wwdg2\", IDX_ICN_LS_MCU, 0, GATE_WWDG2,\n+ \t\t SEC_RIFSC(104)),\n+ };\n+ \n+-- \n+2.51.0\n+\n", "prefixes": [ "1/1" ] }