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GET /api/patches/2195173/?format=api
{ "id": 2195173, "url": "http://patchwork.ozlabs.org/api/patches/2195173/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210135206.229528-18-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210135206.229528-18-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-02-10T13:51:57", "name": "[PULL,17/26] whpx: arm64: clamp down IPA size", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "ab48211fc58ddf8c63e86947f346f1a14d36a2b6", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210135206.229528-18-peter.maydell@linaro.org/mbox/", "series": [ { "id": 491680, "url": "http://patchwork.ozlabs.org/api/series/491680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491680", "date": "2026-02-10T13:51:40", "name": "[PULL,01/26] target/arm/kvm: add constants for new PSCI versions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195173/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195173/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=IeldHlK0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9NP253Mcz1xtr\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 11 Feb 2026 00:55:18 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpoAH-0002BJ-2w; Tue, 10 Feb 2026 08:52:29 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1vpoAE-00028g-O8\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:26 -0500", "from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1vpoAB-0006M0-LI\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:26 -0500", "by mail-wm1-x32c.google.com with SMTP id\n 5b1f17b1804b1-480142406b3so43928015e9.1\n for <qemu-devel@nongnu.org>; Tue, 10 Feb 2026 05:52:23 -0800 (PST)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.21\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 10 Feb 2026 05:52:21 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1770731542; x=1771336342; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=wdfCt/hYND0Wf2q+qK3U6LW7wpQkulM9WJ6MRgTXjCM=;\n b=IeldHlK0Bl+95Tg8R0uGVWTWEr9hEmF47bIvO+3i6PBnWQIg/AuG2Vh7wL6SOpwFzh\n U70GsckX8f+TKWRcu9lqmA8vetT2Q/CiE2IiJEu9N3Ir/7EP/murEVckumoN6ixxfNM5\n 6wMMha5ZUVvnBAu3dh0fKaqHG8P6g113pBPc3szkRZcF3/4W1WlA/SbFiMqvVUYQ6fHY\n mUqBONc146WGMGCkpeX9MXmNqImjquonJcIGfdoRbeBADfZ9PFUxaDf+OYQByNKLNixT\n EUnX6wThEG+VigITEbdeCDV8pWKPOJNATJdhOccgoK3IvV/ESEd2TSzOTJiyqVxbVqf2\n B6PQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1770731542; x=1771336342;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=wdfCt/hYND0Wf2q+qK3U6LW7wpQkulM9WJ6MRgTXjCM=;\n b=vzSFedYPCOJwT1tj3PSlMhBh9Hny24fs/opwQQq/xLnkQoqhQfyqbCes38oHOXpK+s\n KC5a3BfpWoF5czxRQrYZ33n1gabv3ZVdwYYLOSM0ef/9PmMQFaKblZ8aVKpClhbKXh1s\n eIKy10VL1LzB1bVX+113VwA/mhzZ8nnuz/OExnbp4XDViuGmFZwDXYM9irZHc9CBqX17\n RFQAYpAw/oMiHkPh/4scOTsWVbA2vwD5CKibb6bmVatm453KB7bU+uVf3kZTRBURWOql\n WiYMS449bYf3t8VeQl5nJ5mGTTENDOH5csAc9mWmS9QIXudxtRv2pgIjVC0rhnMbbl82\n O4Qg==", "X-Gm-Message-State": "AOJu0Yw2MqXt+1gun527YOwMA9dzY50gSp8tgpilDit2IoBVxMxzAG1N\n mNy6OrChPnIM+FekRQZYLtSrkXf3pAZ/lwH/ogRBIYOw6Hdi3nB+rePwqmu05kBuptQYTYYqfA5\n +6PT0", "X-Gm-Gg": "AZuq6aIcQQ8SuR/DHvGhzlHob426eP57UPdTwqClt9S/l2vWxbduAKI3MjhUweYpW5o\n +tqv+uyxt2W6YMB7WA+pqGqvEDyCjXO03XnB033ui6rIBuiHmwt+VOb5gUFGoHcZG81XX1NXaM3\n KORDKt+zpdEtt4JUud5Dnrb6BFHP3rGiXQ7mtFinkkJb8w1oQWiMyBHsbFv+Npu8jwSXAjElgb/\n SePFj3eniNkphNALM7NOeTkn09BQlq2tiOCUuQ/F9fs0du6/PUKH6ZWDgT4hCS+uwXgECixqWcq\n aRSq6to+vDvvJuiF7vrAHy+gBo8y/llzzPj+YppGgkPTw8qZgnNMcPNyH3o00zO/jeSYJNaOBM7\n uIHNebbRQt8JBArut5UXVXQIxJsXIC9F+z+YYS86WimByISlvKdmrEeq0OGc2t7k5hUoEA33bdT\n 5C2lLuPwrwjvle4GkBVMHUyLny6BGJgT7yoCOhEs9j+uKADpW888dzS6uOmOgvPXnlSOupFFMNh\n 7mwRPmEupm/kK3nv+piqLwYnbTSlSg=", "X-Received": "by 2002:a05:600c:190f:b0:480:52fd:d2e4 with SMTP id\n 5b1f17b1804b1-4835056df77mr29591855e9.0.1770731542010;\n Tue, 10 Feb 2026 05:52:22 -0800 (PST)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 17/26] whpx: arm64: clamp down IPA size", "Date": "Tue, 10 Feb 2026 13:51:57 +0000", "Message-ID": "<20260210135206.229528-18-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210135206.229528-1-peter.maydell@linaro.org>", "References": "<20260210135206.229528-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32c;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nCode taken from HVF and adapted for WHPX use. Note that WHPX doesn't\nhave a default vs maximum IPA distinction.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nReviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/virt.c | 32 ++++++++++++++++++++++++++\n include/hw/core/boards.h | 1 +\n target/arm/whpx/meson.build | 2 ++\n target/arm/whpx/whpx-all.c | 45 +++++++++++++++++++++++++++++++++++++\n target/arm/whpx/whpx-stub.c | 15 +++++++++++++\n target/arm/whpx_arm.h | 16 +++++++++++++\n 6 files changed, 111 insertions(+)\n create mode 100644 target/arm/whpx/whpx-stub.c\n create mode 100644 target/arm/whpx_arm.h", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex b7eb0cec5e..77832b566e 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -72,6 +72,7 @@\n #include \"hw/core/irq.h\"\n #include \"kvm_arm.h\"\n #include \"hvf_arm.h\"\n+#include \"whpx_arm.h\"\n #include \"hw/firmware/smbios.h\"\n #include \"qapi/visitor.h\"\n #include \"qapi/qapi-visit-common.h\"\n@@ -3360,6 +3361,36 @@ static int virt_kvm_type(MachineState *ms, const char *type_str)\n return fixed_ipa ? 0 : requested_pa_size;\n }\n \n+static int virt_whpx_get_physical_address_range(MachineState *ms)\n+{\n+ VirtMachineState *vms = VIRT_MACHINE(ms);\n+\n+ int max_ipa_size = whpx_arm_get_ipa_bit_size();\n+\n+ /* We freeze the memory map to compute the highest gpa */\n+ virt_set_memmap(vms, max_ipa_size);\n+\n+ int requested_ipa_size = 64 - clz64(vms->highest_gpa);\n+\n+ /*\n+ * If we're <= the default IPA size just use the default.\n+ * If we're above the default but below the maximum, round up to\n+ * the maximum. whpx_arm_get_max_ipa_bit_size() conveniently only\n+ * returns values that are valid ARM PARange values.\n+ */\n+ if (requested_ipa_size <= max_ipa_size) {\n+ requested_ipa_size = max_ipa_size;\n+ } else {\n+ error_report(\"-m and ,maxmem option values \"\n+ \"require an IPA range (%d bits) larger than \"\n+ \"the one supported by the host (%d bits)\",\n+ requested_ipa_size, max_ipa_size);\n+ return -1;\n+ }\n+\n+ return requested_ipa_size;\n+}\n+\n static int virt_hvf_get_physical_address_range(MachineState *ms)\n {\n VirtMachineState *vms = VIRT_MACHINE(ms);\n@@ -3459,6 +3490,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)\n mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;\n mc->kvm_type = virt_kvm_type;\n mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;\n+ mc->whpx_get_physical_address_range = virt_whpx_get_physical_address_range;\n assert(!mc->get_hotplug_handler);\n mc->get_hotplug_handler = virt_machine_get_hotplug_handler;\n hc->pre_plug = virt_machine_device_pre_plug_cb;\ndiff --git a/include/hw/core/boards.h b/include/hw/core/boards.h\nindex 07f8938752..0b2aefb126 100644\n--- a/include/hw/core/boards.h\n+++ b/include/hw/core/boards.h\n@@ -278,6 +278,7 @@ struct MachineClass {\n void (*wakeup)(MachineState *state);\n int (*kvm_type)(MachineState *machine, const char *arg);\n int (*hvf_get_physical_address_range)(MachineState *machine);\n+ int (*whpx_get_physical_address_range)(MachineState *machine);\n \n BlockInterfaceType block_default_type;\n int units_per_default_bus;\ndiff --git a/target/arm/whpx/meson.build b/target/arm/whpx/meson.build\nindex 1de2ef0283..3df632c9d3 100644\n--- a/target/arm/whpx/meson.build\n+++ b/target/arm/whpx/meson.build\n@@ -1,3 +1,5 @@\n arm_system_ss.add(when: 'CONFIG_WHPX', if_true: files(\n 'whpx-all.c',\n ))\n+\n+arm_common_system_ss.add(when: 'CONFIG_WHPX', if_false: files('whpx-stub.c'))\ndiff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c\nindex 192d7ec7a8..850f6ec81f 100644\n--- a/target/arm/whpx/whpx-all.c\n+++ b/target/arm/whpx/whpx-all.c\n@@ -35,6 +35,7 @@\n #include \"system/whpx-accel-ops.h\"\n #include \"system/whpx-all.h\"\n #include \"system/whpx-common.h\"\n+#include \"whpx_arm.h\"\n #include \"hw/arm/bsa.h\"\n #include \"arm-powerctl.h\"\n \n@@ -633,6 +634,40 @@ static void whpx_cpu_update_state(void *opaque, bool running, RunState state)\n {\n }\n \n+uint32_t whpx_arm_get_ipa_bit_size(void)\n+{\n+ WHV_CAPABILITY whpx_cap;\n+ UINT32 whpx_cap_size;\n+ HRESULT hr;\n+ hr = whp_dispatch.WHvGetCapability(\n+ WHvCapabilityCodePhysicalAddressWidth, &whpx_cap,\n+ sizeof(whpx_cap), &whpx_cap_size);\n+ if (FAILED(hr)) {\n+ error_report(\"WHPX: failed to get supported \"\n+ \"physical address width, hr=%08lx\", hr);\n+ }\n+\n+ /*\n+ * We clamp any IPA size we want to back the VM with to a valid PARange\n+ * value so the guest doesn't try and map memory outside of the valid range.\n+ * This logic just clamps the passed in IPA bit size to the first valid\n+ * PARange value <= to it.\n+ */\n+ return round_down_to_parange_bit_size(whpx_cap.PhysicalAddressWidth);\n+}\n+\n+static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar)\n+{\n+ uint32_t ipa_size = whpx_arm_get_ipa_bit_size();\n+ uint64_t id_aa64mmfr0;\n+\n+ /* Clamp down the PARange to the IPA size the kernel supports. */\n+ uint8_t index = round_down_to_parange_index(ipa_size);\n+ id_aa64mmfr0 = GET_IDREG(isar, ID_AA64MMFR0);\n+ id_aa64mmfr0 = (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index;\n+ SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0);\n+}\n+\n int whpx_init_vcpu(CPUState *cpu)\n {\n HRESULT hr;\n@@ -706,6 +741,7 @@ int whpx_init_vcpu(CPUState *cpu)\n val.Reg64 = deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */);\n whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, val);\n \n+ clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar);\n return 0;\n }\n \n@@ -722,6 +758,8 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n UINT32 whpx_cap_size;\n WHV_PARTITION_PROPERTY prop;\n WHV_CAPABILITY_FEATURES features;\n+ MachineClass *mc = MACHINE_GET_CLASS(ms);\n+ int pa_range = 0;\n \n whpx = &whpx_global;\n /* on arm64 Windows Hypervisor Platform, vGICv3 always used */\n@@ -732,6 +770,13 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n goto error;\n }\n \n+ if (mc->whpx_get_physical_address_range) {\n+ pa_range = mc->whpx_get_physical_address_range(ms);\n+ if (pa_range < 0) {\n+ return -EINVAL;\n+ }\n+ }\n+\n whpx->mem_quota = ms->ram_size;\n \n hr = whp_dispatch.WHvGetCapability(\ndiff --git a/target/arm/whpx/whpx-stub.c b/target/arm/whpx/whpx-stub.c\nnew file mode 100644\nindex 0000000000..32e434a5f6\n--- /dev/null\n+++ b/target/arm/whpx/whpx-stub.c\n@@ -0,0 +1,15 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * WHPX stubs for ARM\n+ *\n+ * Copyright (c) 2025 Mohamed Mediouni\n+ *\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"whpx_arm.h\"\n+\n+uint32_t whpx_arm_get_ipa_bit_size(void)\n+{\n+ g_assert_not_reached();\n+}\ndiff --git a/target/arm/whpx_arm.h b/target/arm/whpx_arm.h\nnew file mode 100644\nindex 0000000000..de7406b66f\n--- /dev/null\n+++ b/target/arm/whpx_arm.h\n@@ -0,0 +1,16 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * WHPX support -- ARM specifics\n+ *\n+ * Copyright (c) 2025 Mohamed Mediouni\n+ *\n+ */\n+\n+#ifndef QEMU_WHPX_ARM_H\n+#define QEMU_WHPX_ARM_H\n+\n+#include \"target/arm/cpu-qom.h\"\n+\n+uint32_t whpx_arm_get_ipa_bit_size(void);\n+\n+#endif\n", "prefixes": [ "PULL", "17/26" ] }