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GET /api/patches/2195168/?format=api
{ "id": 2195168, "url": "http://patchwork.ozlabs.org/api/patches/2195168/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210135206.229528-20-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210135206.229528-20-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-02-10T13:51:59", "name": "[PULL,19/26] whpx: arm64: implement -cpu host", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "221a2cb41dabfaf9700e7383a26571d2474c738d", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210135206.229528-20-peter.maydell@linaro.org/mbox/", "series": [ { "id": 491680, "url": "http://patchwork.ozlabs.org/api/series/491680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491680", "date": "2026-02-10T13:51:40", "name": "[PULL,01/26] target/arm/kvm: add constants for new PSCI versions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195168/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195168/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=VeMHsaF9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9NNj4j3Sz1xtV\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 11 Feb 2026 00:55:01 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpoAI-0002CF-HU; Tue, 10 Feb 2026 08:52:30 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1vpoAG-0002As-GM\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:28 -0500", "from mail-wm1-x343.google.com ([2a00:1450:4864:20::343])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1vpoAD-0006MN-R9\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:28 -0500", "by mail-wm1-x343.google.com with SMTP id\n 5b1f17b1804b1-480706554beso43998855e9.1\n for <qemu-devel@nongnu.org>; Tue, 10 Feb 2026 05:52:25 -0800 (PST)", "from lanath.. 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helo=mail-wm1-x343.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nLogic to fetch MIDR_EL1 for cpu 0 adapted from:\nhttps://github.com/FEX-Emu/FEX/blob/e6de17e72ef03aa88ba14fa0ec13163061608c74/Source/Windows/Common/CPUFeatures.cpp#L62\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nReviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\nReviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/cpu64.c | 17 +++---\n target/arm/whpx/whpx-all.c | 104 +++++++++++++++++++++++++++++++++++++\n target/arm/whpx_arm.h | 1 +\n 3 files changed, 116 insertions(+), 6 deletions(-)", "diff": "diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex 4dfc03973e..5d7c6b7fbb 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -26,10 +26,13 @@\n #include \"qemu/units.h\"\n #include \"system/kvm.h\"\n #include \"system/hvf.h\"\n+#include \"system/whpx.h\"\n+#include \"system/hw_accel.h\"\n #include \"system/qtest.h\"\n #include \"system/tcg.h\"\n #include \"kvm_arm.h\"\n #include \"hvf_arm.h\"\n+#include \"whpx_arm.h\"\n #include \"qapi/visitor.h\"\n #include \"hw/core/qdev-properties.h\"\n #include \"internals.h\"\n@@ -521,7 +524,7 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)\n isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0);\n isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0);\n \n- if (kvm_enabled() || hvf_enabled()) {\n+ if (hwaccel_enabled()) {\n /*\n * Exit early if PAuth is enabled and fall through to disable it.\n * The algorithm selection properties are not present.\n@@ -598,10 +601,10 @@ void aarch64_add_pauth_properties(Object *obj)\n \n /* Default to PAUTH on, with the architected algorithm on TCG. */\n qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);\n- if (kvm_enabled() || hvf_enabled()) {\n+ if (hwaccel_enabled()) {\n /*\n * Mirror PAuth support from the probed sysregs back into the\n- * property for KVM or hvf. Is it just a bit backward? Yes it is!\n+ * property for HW accel. Is it just a bit backward? Yes it is!\n * Note that prop_pauth is true whether the host CPU supports the\n * architected QARMA5 algorithm or the IMPDEF one. We don't\n * provide the separate pauth-impdef property for KVM or hvf,\n@@ -769,6 +772,8 @@ static void aarch64_host_initfn(Object *obj)\n }\n #elif defined(CONFIG_HVF)\n hvf_arm_set_cpu_features_from_host(cpu);\n+#elif defined(CONFIG_WHPX)\n+ whpx_arm_set_cpu_features_from_host(cpu);\n #else\n g_assert_not_reached();\n #endif\n@@ -779,8 +784,8 @@ static void aarch64_host_initfn(Object *obj)\n \n static void aarch64_max_initfn(Object *obj)\n {\n- if (kvm_enabled() || hvf_enabled()) {\n- /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */\n+ if (hwaccel_enabled()) {\n+ /* When hardware acceleration enabled, '-cpu max' is identical to '-cpu host' */\n aarch64_host_initfn(obj);\n return;\n }\n@@ -799,7 +804,7 @@ static const ARMCPUInfo aarch64_cpus[] = {\n { .name = \"cortex-a57\", .initfn = aarch64_a57_initfn },\n { .name = \"cortex-a53\", .initfn = aarch64_a53_initfn },\n { .name = \"max\", .initfn = aarch64_max_initfn },\n-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)\n+#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX)\n { .name = \"host\", .initfn = aarch64_host_initfn },\n #endif\n };\ndiff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c\nindex 6067918b27..c88c67a9e2 100644\n--- a/target/arm/whpx/whpx-all.c\n+++ b/target/arm/whpx/whpx-all.c\n@@ -41,6 +41,17 @@\n \n #include <winhvplatform.h>\n #include <winhvplatformdefs.h>\n+#include <winreg.h>\n+\n+typedef struct ARMHostCPUFeatures {\n+ ARMISARegisters isar;\n+ uint64_t features;\n+ uint64_t midr;\n+ uint32_t reset_sctlr;\n+ const char *dtb_compatible;\n+} ARMHostCPUFeatures;\n+\n+static ARMHostCPUFeatures arm_host_cpu_features;\n \n typedef struct WHPXRegMatch {\n WHV_REGISTER_NAME reg;\n@@ -668,6 +679,99 @@ static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar)\n SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0);\n }\n \n+static uint64_t whpx_read_midr(void)\n+{\n+ HKEY key;\n+ uint64_t midr_el1;\n+ DWORD size = sizeof(midr_el1);\n+ const char *path = \"Hardware\\\\Description\\\\System\\\\CentralProcessor\\\\0\\\\\";\n+ assert(!RegOpenKeyExA(HKEY_LOCAL_MACHINE, path, 0, KEY_READ, &key));\n+ assert(!RegGetValueA(key, NULL, \"CP 4000\", RRF_RT_REG_QWORD, NULL, &midr_el1, &size));\n+ RegCloseKey(key);\n+ return midr_el1;\n+}\n+\n+static bool whpx_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n+{\n+ const struct isar_regs {\n+ WHV_REGISTER_NAME reg;\n+ uint64_t *val;\n+ } regs[] = {\n+ { WHvArm64RegisterIdAa64Pfr0El1, &ahcf->isar.idregs[ID_AA64PFR0_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Pfr1El1, &ahcf->isar.idregs[ID_AA64PFR1_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Dfr0El1, &ahcf->isar.idregs[ID_AA64DFR0_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Dfr1El1 , &ahcf->isar.idregs[ID_AA64DFR1_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Isar0El1, &ahcf->isar.idregs[ID_AA64ISAR0_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Isar1El1, &ahcf->isar.idregs[ID_AA64ISAR1_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Isar2El1, &ahcf->isar.idregs[ID_AA64ISAR2_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Mmfr0El1, &ahcf->isar.idregs[ID_AA64MMFR0_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Mmfr1El1, &ahcf->isar.idregs[ID_AA64MMFR1_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Mmfr2El1, &ahcf->isar.idregs[ID_AA64MMFR2_EL1_IDX] },\n+ { WHvArm64RegisterIdAa64Mmfr3El1, &ahcf->isar.idregs[ID_AA64MMFR2_EL1_IDX] }\n+ };\n+\n+ int i;\n+ WHV_REGISTER_VALUE val;\n+\n+ ahcf->dtb_compatible = \"arm,armv8\";\n+ ahcf->features = (1ULL << ARM_FEATURE_V8) |\n+ (1ULL << ARM_FEATURE_NEON) |\n+ (1ULL << ARM_FEATURE_AARCH64) |\n+ (1ULL << ARM_FEATURE_PMU) |\n+ (1ULL << ARM_FEATURE_GENERIC_TIMER);\n+\n+ for (i = 0; i < ARRAY_SIZE(regs); i++) {\n+ clean_whv_register_value(&val);\n+ whpx_get_global_reg(regs[i].reg, &val);\n+ *regs[i].val = val.Reg64;\n+ }\n+\n+ /*\n+ * MIDR_EL1 is not a global register on WHPX\n+ * As such, read the CPU0 from the registry to get a consistent value.\n+ * Otherwise, on heterogenous systems, you'll get variance between CPUs.\n+ */\n+ ahcf->midr = whpx_read_midr();\n+\n+ clamp_id_aa64mmfr0_parange_to_ipa_size(&ahcf->isar);\n+\n+ /*\n+ * Disable SVE, which is not supported by QEMU whpx yet.\n+ * Work needed for SVE support:\n+ * - SVE state save/restore\n+ * - any potentially needed VL management\n+ * Also disable SME at the same time. (not currently supported by Hyper-V)\n+ */\n+ SET_IDREG(&ahcf->isar, ID_AA64PFR0,\n+ GET_IDREG(&ahcf->isar, ID_AA64PFR0) & ~R_ID_AA64PFR0_SVE_MASK);\n+\n+ SET_IDREG(&ahcf->isar, ID_AA64PFR1,\n+ GET_IDREG(&ahcf->isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK);\n+\n+ return true;\n+}\n+\n+void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu)\n+{\n+ if (!arm_host_cpu_features.dtb_compatible) {\n+ if (!whpx_enabled() ||\n+ !whpx_arm_get_host_cpu_features(&arm_host_cpu_features)) {\n+ /*\n+ * We can't report this error yet, so flag that we need to\n+ * in arm_cpu_realizefn().\n+ */\n+ cpu->host_cpu_probe_failed = true;\n+ return;\n+ }\n+ }\n+\n+ cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;\n+ cpu->isar = arm_host_cpu_features.isar;\n+ cpu->env.features = arm_host_cpu_features.features;\n+ cpu->midr = arm_host_cpu_features.midr;\n+ cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;\n+}\n+\n int whpx_init_vcpu(CPUState *cpu)\n {\n HRESULT hr;\ndiff --git a/target/arm/whpx_arm.h b/target/arm/whpx_arm.h\nindex de7406b66f..df65fd753c 100644\n--- a/target/arm/whpx_arm.h\n+++ b/target/arm/whpx_arm.h\n@@ -12,5 +12,6 @@\n #include \"target/arm/cpu-qom.h\"\n \n uint32_t whpx_arm_get_ipa_bit_size(void);\n+void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu);\n \n #endif\n", "prefixes": [ "PULL", "19/26" ] }