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GET /api/patches/2195163/?format=api
{ "id": 2195163, "url": "http://patchwork.ozlabs.org/api/patches/2195163/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210135206.229528-5-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210135206.229528-5-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-02-10T13:51:44", "name": "[PULL,04/26] hw: arm: virt: rework MSI-X configuration", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "9bf6d0a699ce20d8d9e6c3467f758d5298c42e44", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210135206.229528-5-peter.maydell@linaro.org/mbox/", "series": [ { "id": 491680, "url": "http://patchwork.ozlabs.org/api/series/491680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491680", "date": "2026-02-10T13:51:40", "name": "[PULL,01/26] target/arm/kvm: add constants for new PSCI versions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195163/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195163/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=E+GGB2sp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9NMj6whVz1xtV\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 11 Feb 2026 00:54:09 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpoAC-00022V-G4; Tue, 10 Feb 2026 08:52:24 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1vpoA3-0001wc-Gh\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:15 -0500", "from mail-wm1-x332.google.com ([2a00:1450:4864:20::332])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1vpoA1-0006JY-Du\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:15 -0500", "by mail-wm1-x332.google.com with SMTP id\n 5b1f17b1804b1-47edd6111b4so82572605e9.1\n for <qemu-devel@nongnu.org>; Tue, 10 Feb 2026 05:52:12 -0800 (PST)", "from lanath.. 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helo=mail-wm1-x332.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nIntroduce a -M msi= argument to be able to control MSI-X support independently\nfrom ITS, as part of supporting GICv3 + GICv2m platforms.\n\nRemove vms->its as it's no longer needed after that change.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/virt-acpi-build.c | 20 ++++---\n hw/arm/virt.c | 119 ++++++++++++++++++++++++++++++++++++---\n include/hw/arm/virt.h | 5 +-\n 3 files changed, 128 insertions(+), 16 deletions(-)", "diff": "diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex c145678185..544004615d 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -569,7 +569,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n nb_nodes = num_smmus + 1; /* RC and SMMUv3 */\n rc_mapping_count = rc_smmu_idmaps_len;\n \n- if (vms->its) {\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n /*\n * Knowing the ID ranges from the RC to the SMMU, it's possible to\n * determine the ID ranges from RC that go directly to ITS.\n@@ -590,7 +590,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n }\n }\n } else {\n- if (vms->its) {\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n nb_nodes = 2; /* RC and ITS */\n rc_mapping_count = 1; /* Direct map to ITS */\n } else {\n@@ -605,7 +605,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);\n build_append_int_noprefix(table_data, 0, 4); /* Reserved */\n \n- if (vms->its) {\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n /* Table 12 ITS Group Format */\n build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */\n node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;\n@@ -624,7 +624,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n int smmu_mapping_count, offset_to_id_array;\n int irq = sdev->irq;\n \n- if (vms->its) {\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n smmu_mapping_count = 1; /* ITS Group node */\n offset_to_id_array = SMMU_V3_ENTRY_SIZE; /* Just after the header */\n } else {\n@@ -717,7 +717,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n }\n }\n \n- if (vms->its) {\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n /*\n * Map bypassed (don't go through the SMMU) RIDs (input) to\n * ITS Group node directly: RC -> ITS.\n@@ -735,7 +735,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n * SMMU: RC -> ITS.\n * Output IORT node is the ITS Group node (the first node).\n */\n- build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET, 0);\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n+ build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET, 0);\n+ }\n }\n \n build_iort_rmr_nodes(table_data, smmuv3_devs, &id);\n@@ -1053,7 +1055,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n memmap[VIRT_HIGH_GIC_REDIST2].size);\n }\n \n- if (vms->its) {\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n /*\n * ACPI spec, Revision 6.0 Errata A\n * (original 6.0 definition has invalid Length)\n@@ -1067,7 +1069,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);\n build_append_int_noprefix(table_data, 0, 4); /* Reserved */\n }\n- } else {\n+ }\n+\n+ if (vms->msi_controller == VIRT_MSI_CTRL_GICV2M) {\n const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;\n \n /* 5.2.12.16 GIC MSI Frame Structure */\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 390845c503..aa5e992712 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -737,7 +737,6 @@ static void create_its(VirtMachineState *vms)\n {\n DeviceState *dev;\n \n- assert(vms->its);\n if (!kvm_irqchip_in_kernel() && !vms->tcg_its) {\n /*\n * Do nothing if ITS is neither supported by the host nor emulated by\n@@ -957,9 +956,9 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n \n fdt_add_gic_node(vms);\n \n- if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n create_its(vms);\n- } else if (vms->gic_version == VIRT_GIC_VERSION_2) {\n+ } else if (vms->msi_controller == VIRT_MSI_CTRL_GICV2M) {\n create_v2m(vms);\n }\n }\n@@ -2137,6 +2136,44 @@ static void finalize_gic_version(VirtMachineState *vms)\n gics_supported, max_cpus);\n }\n \n+static void finalize_msi_controller(VirtMachineState *vms)\n+{\n+ /*\n+ * VIRT_MSI_LEGACY_OPT_ITS_OFF is an option to replicate\n+ * behavior of its=off when running with a GICv2, where a\n+ * GICv2m is still present. Otherwise, it behaves the same\n+ * as msi=off.\n+ */\n+ if (vms->msi_controller == VIRT_MSI_LEGACY_OPT_ITS_OFF) {\n+ if (vms->gic_version == 2) {\n+ vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n+ } else {\n+ vms->msi_controller = VIRT_MSI_CTRL_NONE;\n+ }\n+ }\n+ if (vms->msi_controller == VIRT_MSI_CTRL_AUTO) {\n+ if (vms->gic_version == VIRT_GIC_VERSION_2) {\n+ vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n+ } else {\n+ vms->msi_controller = VIRT_MSI_CTRL_ITS;\n+ }\n+ }\n+\n+ if (vms->msi_controller == VIRT_MSI_CTRL_ITS) {\n+ if (vms->gic_version == VIRT_GIC_VERSION_2) {\n+ /*\n+ * The legacy its= option in earlier releases allowed specifying\n+ * this configuration and treated it as GICv3 + GICv2m.\n+ * Diagnose it as an error even for that case.\n+ */\n+ error_report(\"GICv2 + ITS is an invalid configuration.\");\n+ exit(1);\n+ }\n+ }\n+\n+ assert(vms->msi_controller != VIRT_MSI_CTRL_AUTO);\n+}\n+\n /*\n * virt_post_cpus_gic_realized() must be called after the CPUs and\n * the GIC have both been realized.\n@@ -2256,6 +2293,7 @@ static void machvirt_init(MachineState *machine)\n * KVM is not available yet\n */\n finalize_gic_version(vms);\n+ finalize_msi_controller(vms);\n \n if (vms->secure) {\n /*\n@@ -2705,18 +2743,76 @@ static void virt_set_highmem_mmio_size(Object *obj, Visitor *v,\n extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size;\n }\n \n+static char *virt_get_msi(Object *obj, Error **errp)\n+{\n+ VirtMachineState *vms = VIRT_MACHINE(obj);\n+ const char *val;\n+\n+ switch (vms->msi_controller) {\n+ case VIRT_MSI_CTRL_NONE:\n+ case VIRT_MSI_LEGACY_OPT_ITS_OFF:\n+ val = \"off\";\n+ break;\n+ case VIRT_MSI_CTRL_ITS:\n+ val = \"its\";\n+ break;\n+ case VIRT_MSI_CTRL_GICV2M:\n+ val = \"gicv2m\";\n+ break;\n+ case VIRT_MSI_CTRL_AUTO:\n+ val = \"auto\";\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+ return g_strdup(val);\n+}\n+\n+static void virt_set_msi(Object *obj, const char *value, Error **errp)\n+{\n+ ERRP_GUARD();\n+ VirtMachineState *vms = VIRT_MACHINE(obj);\n+\n+ if (!strcmp(value, \"auto\")) {\n+ vms->msi_controller = VIRT_MSI_CTRL_AUTO; /* Will be overriden later */\n+ } else if (!strcmp(value, \"its\")) {\n+ vms->msi_controller = VIRT_MSI_CTRL_ITS;\n+ } else if (!strcmp(value, \"gicv2m\")) {\n+ vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n+ } else if (!strcmp(value, \"off\")) {\n+ vms->msi_controller = VIRT_MSI_CTRL_NONE;\n+ } else {\n+ error_setg(errp, \"Invalid msi value\");\n+ error_append_hint(errp, \"Valid values are auto, gicv2m, its, off\\n\");\n+ }\n+}\n+\n static bool virt_get_its(Object *obj, Error **errp)\n {\n VirtMachineState *vms = VIRT_MACHINE(obj);\n \n- return vms->its;\n+ switch (vms->msi_controller) {\n+ case VIRT_MSI_CTRL_AUTO:\n+ case VIRT_MSI_CTRL_ITS:\n+ return true;\n+ case VIRT_MSI_CTRL_NONE:\n+ case VIRT_MSI_CTRL_GICV2M:\n+ case VIRT_MSI_LEGACY_OPT_ITS_OFF:\n+ return false;\n+ default:\n+ g_assert_not_reached();\n+ }\n }\n \n static void virt_set_its(Object *obj, bool value, Error **errp)\n {\n VirtMachineState *vms = VIRT_MACHINE(obj);\n \n- vms->its = value;\n+ if (value) {\n+ vms->msi_controller = VIRT_MSI_CTRL_ITS;\n+ } else {\n+ vms->msi_controller = VIRT_MSI_LEGACY_OPT_ITS_OFF;\n+ }\n }\n \n static bool virt_get_dtb_randomness(Object *obj, Error **errp)\n@@ -3043,6 +3139,9 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,\n db_start = base_memmap[VIRT_GIC_V2M].base;\n db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;\n break;\n+ case VIRT_MSI_CTRL_AUTO:\n+ case VIRT_MSI_LEGACY_OPT_ITS_OFF:\n+ g_assert_not_reached();\n }\n resv_prop_str = g_strdup_printf(\"0x%\"PRIx64\":0x%\"PRIx64\":%u\",\n db_start, db_end,\n@@ -3463,6 +3562,12 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)\n \"Set on/off to enable/disable \"\n \"ITS instantiation\");\n \n+ object_class_property_add_str(oc, \"msi\", virt_get_msi,\n+ virt_set_msi);\n+ object_class_property_set_description(oc, \"msi\",\n+ \"Set MSI settings. \"\n+ \"Valid values are auto, gicv2m, its and off\");\n+\n object_class_property_add_bool(oc, \"dtb-randomness\",\n virt_get_dtb_randomness,\n virt_set_dtb_randomness);\n@@ -3518,8 +3623,8 @@ static void virt_instance_init(Object *obj)\n vms->highmem_mmio = true;\n vms->highmem_redists = true;\n \n- /* Default allows ITS instantiation */\n- vms->its = true;\n+ /* Default allows ITS instantiation if available */\n+ vms->msi_controller = VIRT_MSI_CTRL_AUTO;\n /* Allow ITS emulation if the machine version supports it */\n vms->tcg_its = !vmc->no_tcg_its;\n \ndiff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex 3b382bdf49..8069422769 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -101,6 +101,10 @@ typedef enum VirtIOMMUType {\n \n typedef enum VirtMSIControllerType {\n VIRT_MSI_CTRL_NONE,\n+ /* This value is overriden at runtime.*/\n+ VIRT_MSI_CTRL_AUTO,\n+ /* Legacy option: its=off provides a GICv2m when using GICv2 */\n+ VIRT_MSI_LEGACY_OPT_ITS_OFF,\n VIRT_MSI_CTRL_GICV2M,\n VIRT_MSI_CTRL_ITS,\n } VirtMSIControllerType;\n@@ -146,7 +150,6 @@ struct VirtMachineState {\n bool highmem_ecam;\n bool highmem_mmio;\n bool highmem_redists;\n- bool its;\n bool tcg_its;\n bool virt;\n bool ras;\n", "prefixes": [ "PULL", "04/26" ] }