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GET /api/patches/2195161/?format=api
{ "id": 2195161, "url": "http://patchwork.ozlabs.org/api/patches/2195161/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210135206.229528-27-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210135206.229528-27-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-02-10T13:52:06", "name": "[PULL,26/26] target/arm: implement FEAT_E2H0", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "40272ffda28753582cf2e336c3718228cde51462", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210135206.229528-27-peter.maydell@linaro.org/mbox/", "series": [ { "id": 491680, "url": "http://patchwork.ozlabs.org/api/series/491680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491680", "date": "2026-02-10T13:51:40", "name": "[PULL,01/26] target/arm/kvm: add constants for new PSCI versions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195161/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195161/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=vUIuzON0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9NML5PJmz1xwH\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 11 Feb 2026 00:53:50 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpoAP-0002Gd-J6; Tue, 10 Feb 2026 08:52:37 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1vpoAN-0002FN-Ce\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:35 -0500", "from mail-wm1-x329.google.com ([2a00:1450:4864:20::329])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1vpoAK-0006OY-OQ\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:35 -0500", "by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-47ee76e8656so12865285e9.0\n for <qemu-devel@nongnu.org>; Tue, 10 Feb 2026 05:52:32 -0800 (PST)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.30\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 10 Feb 2026 05:52:30 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1770731551; x=1771336351; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=GgDAOb9kz7PXxXREyH/qdM2DkTVepbIG5XlZE6jyCCk=;\n b=vUIuzON0vegThJgtJIReirLzbG6t7jrszieT2YbLribSD8lKITi4tlfCqLX9WPKX3S\n 51AYX64xfsnQOaNk4D2LMrdC5J0MZqeIW1mNg88LPRXNOXtXl+RrmGLCZvQuSeNDOVd/\n 4u894uPnaMqPtU/FXzM6SfeypSoGMsOVyMju4bmLZkkTM1upDQJ3YlB7nAcTLqWI15Aq\n HjxkmQ5S4RGU4yiVZAJCvkbLmqsB9kQlAIYuMTXMJvWdfKi81cGxMRa5kt/HOR5mLSgD\n +s+Fcnbs75u9Pnk4/UnVJkxLlEdKAlkGkdRc2NVf4RywibCSvcLQWPMBRQDc50cnHOKZ\n 4fHQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1770731551; x=1771336351;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=GgDAOb9kz7PXxXREyH/qdM2DkTVepbIG5XlZE6jyCCk=;\n b=HYbSQO/T3BRhSXzaLdByAa71NCG8VpkfkKcziogg45uBCn3/PBDIc/cYt3tqDwsG5d\n hbK7B6GD+s5qRE0BWR1H32Z1Xh9aXmcbNAqJdJGKyuuklr2Or7Q2IFxSorp8gQG3sPdi\n fOFUUYR1nlcHkDkTztyy6yxTrx3AWad2GL01qAiukP8sn+WA9ZXOqxRR+3g04nxWumCv\n kO2T4GZzwqa9CEdfheC8juyUz4GmQCKjlf87CZrs4ST2SENoTdJXwGMtKFl/2n83FEoG\n Fu04Za37D9Y1C//VPY4LRbHobfD7JFGWGqBoz6C6+Fh+8/3Nj0mBxgd7OveHe3ch+2XF\n mVUg==", "X-Gm-Message-State": "AOJu0YyDg0I3AuwT7s/O2/Qreuh/wanQKorxxpk1Q54HmaqPoYj+B7vI\n cmVjrnfQhOLqXCZRuPX0pu3zGSFcidIa0TIiryBS7EtofftezymsPQU5in+/QItd3Tkj+D/musN\n LaYA2", "X-Gm-Gg": "AZuq6aJTU/dQ0EbTnPpkick8oiIl7K9/a+XxwkjS0oqp9OPuJwt5xKjm6c/6IHk597f\n dU8+mP2/PkM/7ebbPz7vLEihW9tOwjshBTpxXTBLKnU5ImQ/P5L6CmUx9Nb36XQmaxml+KrPPSJ\n bNmaVHbxa4QCdSNVZCQfUXNoctCcpWOi5Uqu5lq1u0I/LvkWiKpfKygL6m5egN/VqkChAzEuOe4\n cyG4szB3LpEGu29PTepjB4jJyEQWARQT8jFHGdxne4PdEJQk1m9pSE4WhZxshB6I6X5iZmbpW1e\n 6XTqk/GTlQYBBQwOCE0gfVD2NAYUE+lacBf8VM4+rm4V/tFJIdngkw5+DUyTimGhKyq6jd+m8YG\n jmVPE2LxYvZI+TF8JfH43Gm0X6zYWRPuM9BYws/oKJjbz+K/uQo3K1+bumFJlLXQukkYnTalE0L\n vLLsg+Xj2pZaEMIJ95ucrvLNqDdTq/0ED+0uMnaNzVrss6C0Px6L0vKnG7RFlKefFU7BR/+YGWc\n JiVp4Vt1mJNheB5EYetDwbbWDrM0MQ=", "X-Received": "by 2002:a05:600c:3590:b0:477:79c7:8994 with SMTP id\n 5b1f17b1804b1-48320236b01mr234506765e9.30.1770731551153;\n Tue, 10 Feb 2026 05:52:31 -0800 (PST)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 26/26] target/arm: implement FEAT_E2H0", "Date": "Tue, 10 Feb 2026 13:52:06 +0000", "Message-ID": "<20260210135206.229528-27-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210135206.229528-1-peter.maydell@linaro.org>", "References": "<20260210135206.229528-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::329;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Alex Bennée <alex.bennee@linaro.org>\n\nFEAT_E2H0 is a formalisation of the existing behaviour of HCR_EL2.E2H\nbeing programmable to switch between EL2 host mode and the\n\"traditional\" nVHE EL2 mode. This implies at some point we might want\nto model CPUs without FEAT_E2H0 which will always have EL2 host mode\nenabled.\n\nThere are two values to represent no E2H0 systems of which 0b1110 will\nmake HCR_EL2.NV1 RES0 for FEAT_NV systems. For FEAT_NV2 the NV1 bit is\nalways valid.\n\nMessage-ID: <20260130181648.628364-1-alex.bennee@linaro.org>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nMessage-id: 20260205210231.888199-1-alex.bennee@linaro.org\n\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n docs/system/arm/emulation.rst | 1 +\n target/arm/cpu-features.h | 15 +++++++++++++++\n target/arm/helper.c | 21 +++++++++++++++------\n 3 files changed, 31 insertions(+), 6 deletions(-)", "diff": "diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst\nindex e0d5f9886e..7787691853 100644\n--- a/docs/system/arm/emulation.rst\n+++ b/docs/system/arm/emulation.rst\n@@ -54,6 +54,7 @@ the following architecture extensions:\n - FEAT_DotProd (Advanced SIMD dot product instructions)\n - FEAT_DoubleFault (Double Fault Extension)\n - FEAT_E0PD (Preventing EL0 access to halves of address maps)\n+- FEAT_E2H0 (Programming of HCR_EL2.E2H)\n - FEAT_EBF16 (AArch64 Extended BFloat16 instructions)\n - FEAT_ECV (Enhanced Counter Virtualization)\n - FEAT_EL0 (Support for execution at EL0)\ndiff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex f7b1437340..49c50e850a 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -347,6 +347,7 @@ FIELD(ID_AA64MMFR3, ADERR, 56, 4)\n FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)\n \n FIELD(ID_AA64MMFR4, ASID2, 8, 4)\n+FIELD(ID_AA64MMFR4, E2H0, 24, 4)\n \n FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)\n FIELD(ID_AA64DFR0, TRACEVER, 4, 4)\n@@ -1376,6 +1377,20 @@ static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) != 0;\n }\n \n+/*\n+ * Note the E2H0 ID fields is signed, increasingly negative as more\n+ * isn't implemented.\n+ */\n+static inline bool isar_feature_aa64_e2h0(const ARMISARegisters *id)\n+{\n+ return FIELD_SEX64_IDREG(id, ID_AA64MMFR4, E2H0) >= 0;\n+}\n+\n+static inline bool isar_feature_aa64_nv1_res0(const ARMISARegisters *id)\n+{\n+ return FIELD_SEX64_IDREG(id, ID_AA64MMFR4, E2H0) <= -2;\n+}\n+\n static inline bool isar_feature_aa64_mec(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0;\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex e86ceb130c..8c5769477c 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -3776,7 +3776,8 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)\n }\n \n if (arm_feature(env, ARM_FEATURE_AARCH64)) {\n- if (cpu_isar_feature(aa64_vh, cpu)) {\n+ if (cpu_isar_feature(aa64_vh, cpu) &&\n+ cpu_isar_feature(aa64_e2h0, cpu)) {\n valid_mask |= HCR_E2H;\n }\n if (cpu_isar_feature(aa64_ras, cpu)) {\n@@ -3801,7 +3802,10 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)\n valid_mask |= HCR_GPF;\n }\n if (cpu_isar_feature(aa64_nv, cpu)) {\n- valid_mask |= HCR_NV | HCR_NV1 | HCR_AT;\n+ valid_mask |= HCR_NV | HCR_AT;\n+ if (!cpu_isar_feature(aa64_nv1_res0, cpu)) {\n+ valid_mask |= HCR_NV1;\n+ }\n }\n if (cpu_isar_feature(aa64_nv2, cpu)) {\n valid_mask |= HCR_NV2;\n@@ -3817,10 +3821,15 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)\n /* Clear RES0 bits. */\n value &= valid_mask;\n \n- /* RW is RAO/WI if EL1 is AArch64 only */\n- if (arm_feature(env, ARM_FEATURE_AARCH64) &&\n- !cpu_isar_feature(aa64_aa32_el1, cpu)) {\n- value |= HCR_RW;\n+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {\n+ /* RW is RAO/WI if EL1 is AArch64 only */\n+ if (!cpu_isar_feature(aa64_aa32_el1, cpu)) {\n+ value |= HCR_RW;\n+ }\n+ /* Strictly E2H is RES1 unless FEAT_E2H0 relaxes the requirement */\n+ if (!cpu_isar_feature(aa64_e2h0, cpu)) {\n+ value |= HCR_E2H;\n+ }\n }\n \n /*\n", "prefixes": [ "PULL", "26/26" ] }