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GET /api/patches/2195148/?format=api
{ "id": 2195148, "url": "http://patchwork.ozlabs.org/api/patches/2195148/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260210134647.2050821-3-calebs@linux.ibm.com/", "project": { "id": 69, "url": "http://patchwork.ozlabs.org/api/projects/69/?format=api", "name": "QEMU powerpc development", "link_name": "qemu-ppc", "list_id": "qemu-ppc.nongnu.org", "list_email": "qemu-ppc@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210134647.2050821-3-calebs@linux.ibm.com>", "list_archive_url": null, "date": "2026-02-10T13:46:46", "name": "[v2,2/3] ppc/pnv: Add unimplemented quad and core regs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1a6c8d8c2d916e7925c1d112c48bd271b51fde4e", "submitter": { "id": 90855, "url": "http://patchwork.ozlabs.org/api/people/90855/?format=api", "name": "Caleb Schlossin", "email": "calebs@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260210134647.2050821-3-calebs@linux.ibm.com/mbox/", "series": [ { "id": 491678, "url": "http://patchwork.ozlabs.org/api/series/491678/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-ppc/list/?series=491678", "date": "2026-02-10T13:46:45", "name": "Power10 PowerVM bringup fixes", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491678/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195148/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195148/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com 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:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=pp1; bh=r64brsEFXIrJYIYqV\n v1xKmVK++ZiYAxOnnPBb59Azso=; b=NFvQ3BdAwpvnVIYJJyKIZOlZIbvHP8TOu\n qPQJfOnMcu9/BcDFsau4gFOW3FFLFj8c1F8/EYtOBrYqujJwEy/phufoB129qdiI\n WgcoMn/Z7wak6IC2LsGIHOcGu41danyurIQPrglljns+Fk/iiBbH6g9Bf477f3bz\n cZHwB65Ctbx6gI4IZbm4hlUVrSQj82gtkDF6+MtIZnAtXBfhkgujWNyTIkDFfloc\n XXUU/gD39IvsngrK1CNS2S+Isim50cBtNpLjnxN7vV5d2XfeTAv89Gp0K08rsCWi\n HIFkppc4LkqNo2d82BH4KN/k6S/AqTTdXOFkeFNVw/1OQPVDUK0XA==", "From": "Caleb Schlossin <calebs@linux.ibm.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-ppc@nongnu.org, npiggin@gmail.com, adityag@linux.ibm.com,\n milesg@linux.ibm.com, chalapathi.v@linux.ibm.com,\n harshpb@linux.ibm.com, calebs@linux.ibm.com", "Subject": "[PATCH v2 2/3] ppc/pnv: Add unimplemented quad and core regs", "Date": "Tue, 10 Feb 2026 07:46:46 -0600", "Message-ID": "<20260210134647.2050821-3-calebs@linux.ibm.com>", "X-Mailer": "git-send-email 2.47.3", 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"X-Spam_score_int": "-19", "X-Spam_score": "-2.0", "X-Spam_bar": "--", "X-Spam_report": "(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-ppc@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-ppc.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-ppc>", "List-Post": "<mailto:qemu-ppc@nongnu.org>", "List-Help": "<mailto:qemu-ppc-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This commit adds the read/write functionality for few core and\nquad registers for Power Hypervisor development.\n\nReviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com\nReviewed-by: Glenn Miles <milesg@linux.ibm.com>\nReviewed-by: Aditya Gupta <adityag@linux.ibm.com>\nSigned-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>\nSigned-off-by: Caleb Schlossin <calebs@linux.ibm.com>\n---\n hw/ppc/pnv_core.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 87 insertions(+)", "diff": "diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c\nindex 8939515c2c..a95934710f 100644\n--- a/hw/ppc/pnv_core.c\n+++ b/hw/ppc/pnv_core.c\n@@ -183,12 +183,22 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {\n \n /*\n * POWER10 core controls\n+ * Adding additional SCOM register support needed by the\n+ * Power Hypervisor team for their development\n */\n \n+#define PNV10_XSCOM_EC_IMA_EVENT_MASK 0x400\n #define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412\n #define PNV10_XSCOM_EC_CORE_THREAD_INFO 0x413\n+#define PNV10_XSCOM_EC_CORE_FIRMASK 0x443\n+#define PNV10_XSCOM_EC_CORE_FIRMASK_AND 0x444\n+#define PNV10_XSCOM_EC_CORE_FIRMASK_OR 0x445\n #define PNV10_XSCOM_EC_CORE_DIRECT_CONTROLS 0x449\n #define PNV10_XSCOM_EC_CORE_RAS_STATUS 0x454\n+#define PNV10_XSCOM_EC_SPATTN_OR 0x497\n+#define PNV10_XSCOM_EC_SPATTN_AND 0x498\n+#define PNV10_XSCOM_EC_SPATTN 0x499\n+#define PNV10_XSCOM_EC_SPATTN_MASK 0x49A\n \n static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,\n unsigned int width)\n@@ -224,6 +234,19 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,\n }\n }\n break;\n+ case PNV10_XSCOM_EC_IMA_EVENT_MASK:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK:\n+ return 0;\n+ case PNV10_XSCOM_EC_CORE_FIRMASK_OR:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK_AND:\n+ case PNV10_XSCOM_EC_SPATTN_OR:\n+ case PNV10_XSCOM_EC_SPATTN_AND:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: Write only register, ignoring \"\n+ \"xscom read at 0x%08x\\n\", __func__, offset);\n+ break;\n+ case PNV10_XSCOM_EC_SPATTN:\n+ case PNV10_XSCOM_EC_SPATTN_MASK:\n+ return 0;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s: unimp read 0x%08x\\n\", __func__,\n offset);\n@@ -284,6 +307,19 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,\n }\n break;\n \n+ /*\n+ * Allow writes to these SCOMs for Power Hypervisor development.\n+ * Behavior is not needed, just to allow writes to these SCOMs.\n+ */\n+ case PNV10_XSCOM_EC_IMA_EVENT_MASK:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK_OR:\n+ case PNV10_XSCOM_EC_CORE_FIRMASK_AND:\n+ case PNV10_XSCOM_EC_SPATTN_OR:\n+ case PNV10_XSCOM_EC_SPATTN_AND:\n+ case PNV10_XSCOM_EC_SPATTN:\n+ case PNV10_XSCOM_EC_SPATTN_MASK:\n+ break;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s: unimp write 0x%08x\\n\", __func__,\n offset);\n@@ -579,6 +615,23 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {\n * POWER10 Quads\n */\n \n+#define P10_XSCOM_EQ3_MODE_REG1 0x1160a\n+#define P10_XSCOM_EQ3_NCU_SPEC_BAR_REG 0x11650\n+#define P10_XSCOM_EQ3_HTM_MODE 0x11680\n+#define P10_XSCOM_EQ3_HTM_IMA_PDBAR 0x1168b\n+#define P10_XSCOM_EQ2_MODE_REG1 0x1260a\n+#define P10_XSCOM_EQ2_NCU_SPEC_BAR_REG 0x12650\n+#define P10_XSCOM_EQ2_HTM_MODE 0x12680\n+#define P10_XSCOM_EQ2_HTM_IMA_PDBAR 0x1268b\n+#define P10_XSCOM_EQ1_MODE_REG1 0x1460a\n+#define P10_XSCOM_EQ1_NCU_SPEC_BAR_REG 0x14650\n+#define P10_XSCOM_EQ1_HTM_MODE 0x14680\n+#define P10_XSCOM_EQ1_HTM_IMA_PDBAR 0x1468b\n+#define P10_XSCOM_EQ0_MODE_REG1 0x1860a\n+#define P10_XSCOM_EQ0_NCU_SPEC_BAR_REG 0x18650\n+#define P10_XSCOM_EQ0_HTM_MODE 0x18680\n+#define P10_XSCOM_EQ0_HTM_IMA_PDBAR 0x1868b\n+\n static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,\n unsigned int width)\n {\n@@ -586,6 +639,23 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,\n uint64_t val = -1;\n \n switch (offset) {\n+ case P10_XSCOM_EQ0_MODE_REG1:\n+ case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ0_HTM_MODE:\n+ case P10_XSCOM_EQ0_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ1_MODE_REG1:\n+ case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ1_HTM_MODE:\n+ case P10_XSCOM_EQ1_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ2_MODE_REG1:\n+ case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ2_HTM_MODE:\n+ case P10_XSCOM_EQ2_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ3_MODE_REG1:\n+ case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ3_HTM_MODE:\n+ case P10_XSCOM_EQ3_HTM_IMA_PDBAR:\n+ return 0;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s: unimp read 0x%08x\\n\", __func__,\n offset);\n@@ -600,6 +670,23 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,\n uint32_t offset = addr >> 3;\n \n switch (offset) {\n+ case P10_XSCOM_EQ0_MODE_REG1:\n+ case P10_XSCOM_EQ0_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ0_HTM_MODE:\n+ case P10_XSCOM_EQ0_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ1_MODE_REG1:\n+ case P10_XSCOM_EQ1_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ1_HTM_MODE:\n+ case P10_XSCOM_EQ1_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ2_MODE_REG1:\n+ case P10_XSCOM_EQ2_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ2_HTM_MODE:\n+ case P10_XSCOM_EQ2_HTM_IMA_PDBAR:\n+ case P10_XSCOM_EQ3_MODE_REG1:\n+ case P10_XSCOM_EQ3_NCU_SPEC_BAR_REG:\n+ case P10_XSCOM_EQ3_HTM_MODE:\n+ case P10_XSCOM_EQ3_HTM_IMA_PDBAR:\n+ break;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s: unimp write 0x%08x\\n\", __func__,\n offset);\n", "prefixes": [ "v2", "2/3" ] }